ROM_CTRL/64KB Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 39.850s 4.596ms 50 50 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 17.060s 10.998ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 15.930s 2.516ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 17.190s 18.952ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 14.960s 1.881ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 17.070s 17.472ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 15.930s 2.516ms 20 20 100.00
rom_ctrl_csr_aliasing 14.960s 1.881ms 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 12.900s 1.579ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 14.550s 16.891ms 5 5 100.00
V1 TOTAL 115 115 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 17.690s 3.959ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 1.606m 10.650ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 31.770s 4.019ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 16.720s 8.551ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 19.250s 4.169ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 19.250s 4.169ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 17.060s 10.998ms 5 5 100.00
rom_ctrl_csr_rw 15.930s 2.516ms 20 20 100.00
rom_ctrl_csr_aliasing 14.960s 1.881ms 5 5 100.00
rom_ctrl_same_csr_outstanding 18.120s 7.554ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 17.060s 10.998ms 5 5 100.00
rom_ctrl_csr_rw 15.930s 2.516ms 20 20 100.00
rom_ctrl_csr_aliasing 14.960s 1.881ms 5 5 100.00
rom_ctrl_same_csr_outstanding 18.120s 7.554ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 10.132m 276.335ms 49 50 98.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 1.605m 24.614ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.710m 1.856ms 5 5 100.00
rom_ctrl_tl_intg_err 1.315m 4.469ms 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.710m 1.856ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 10.132m 276.335ms 49 50 98.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 10.132m 276.335ms 49 50 98.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 10.132m 276.335ms 49 50 98.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 10.132m 276.335ms 49 50 98.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 10.132m 276.335ms 49 50 98.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.710m 1.856ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.710m 1.856ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 39.850s 4.596ms 50 50 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 39.850s 4.596ms 50 50 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 39.850s 4.596ms 50 50 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.315m 4.469ms 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 10.132m 276.335ms 49 50 98.00
rom_ctrl_kmac_err_chk 31.770s 4.019ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 10.132m 276.335ms 49 50 98.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 10.132m 276.335ms 49 50 98.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 10.132m 276.335ms 49 50 98.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 1.605m 24.614ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.710m 1.856ms 5 5 100.00
V2S TOTAL 94 95 98.95
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.869h 308.151ms 24 50 48.00
V3 TOTAL 24 50 48.00
TOTAL 473 500 94.60

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 3 75.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.72 96.96 93.40 97.88 100.00 98.68 98.04 99.07

Failure Buckets

Past Results