ROM_CTRL Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: `f8b3c19a2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1284268927

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	37.580s	18.698ms	46	50	92.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.320s	18.543ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.230s	2.128ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.970s	2.036ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.940s	8.539ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.020s	2.142ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.230s	2.128ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.940s	8.539ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.170s	1.638ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.630s	1.872ms	5	5	100.00
V1		TOTAL			111	115	96.52
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.470s	15.873ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.832m	33.000ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	28.430s	3.897ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.970s	29.618ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.380s	2.155ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.380s	2.155ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.320s	18.543ms	5	5	100.00
		rom_ctrl_csr_rw	14.230s	2.128ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.940s	8.539ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.750s	1.833ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.320s	18.543ms	5	5	100.00
		rom_ctrl_csr_rw	14.230s	2.128ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.940s	8.539ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.750s	1.833ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.531m	33.368ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.983m	93.562ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.635m	343.420us	5	5	100.00
		rom_ctrl_tl_intg_err	1.236m	2.202ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.635m	343.420us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.531m	33.368ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.531m	33.368ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.531m	33.368ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.531m	33.368ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.531m	33.368ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.635m	343.420us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.635m	343.420us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	37.580s	18.698ms	46	50	92.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	37.580s	18.698ms	46	50	92.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	37.580s	18.698ms	46	50	92.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.236m	2.202ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.531m	33.368ms	49	50	98.00
		rom_ctrl_kmac_err_chk	28.430s	3.897ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.531m	33.368ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.531m	33.368ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.531m	33.368ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.983m	93.562ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.635m	343.420us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.421h	59.357ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			481	500	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.74	97.16	93.12	97.88	86.67	98.68	98.04	98.61

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 12 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.2299169817
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1758fde7-841f-4969-824a-d6728f78478e
```
  - 13.rom_ctrl_stress_all_with_rand_reset.1688457419
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:eec9c14c-f629-4b9b-b203-75c5cba00297
```
  - ... and 10 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 6 failures:

Test rom_ctrl_smoke has 4 failures.

2.rom_ctrl_smoke.4294024855
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10010496347 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe5354252
  UVM_INFO @ 10010496347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.rom_ctrl_smoke.224816838
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10012630315 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x1e72864
  UVM_INFO @ 10012630315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rom_ctrl_stress_all has 1 failures.

5.rom_ctrl_stress_all.4057413203
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10005877792 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf7dd6faf
  UVM_INFO @ 10005877792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

17.rom_ctrl_stress_all_with_rand_reset.1987546356
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10011936321 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x42525fd9
  UVM_INFO @ 10011936321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 13.rom_ctrl_corrupt_sig_fatal_chk.3545829823
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```