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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.68 97.11 93.27 97.88 100.00 99.02 97.89 98.61


Total test records in report: 480
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T277 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1739256209 Sep 27 01:11:21 PM PDT 23 Sep 27 01:15:28 PM PDT 23 328299767823 ps
T278 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3308226756 Sep 27 01:11:56 PM PDT 23 Sep 27 01:16:09 PM PDT 23 41798276109 ps
T279 /workspace/coverage/default/35.rom_ctrl_stress_all.2014299043 Sep 27 01:11:49 PM PDT 23 Sep 27 01:12:41 PM PDT 23 37227378542 ps
T280 /workspace/coverage/default/46.rom_ctrl_stress_all.3860905796 Sep 27 01:12:12 PM PDT 23 Sep 27 01:12:45 PM PDT 23 5880116201 ps
T281 /workspace/coverage/default/22.rom_ctrl_stress_all.440809643 Sep 27 01:12:14 PM PDT 23 Sep 27 01:12:57 PM PDT 23 32007946313 ps
T282 /workspace/coverage/default/6.rom_ctrl_smoke.90264911 Sep 27 01:11:52 PM PDT 23 Sep 27 01:12:15 PM PDT 23 7876928558 ps
T283 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.429509403 Sep 27 01:12:04 PM PDT 23 Sep 27 01:12:18 PM PDT 23 1634941825 ps
T284 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3808133548 Sep 27 01:11:43 PM PDT 23 Sep 27 01:11:52 PM PDT 23 1549097291 ps
T285 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3354143678 Sep 27 01:11:57 PM PDT 23 Sep 27 01:12:25 PM PDT 23 36772533985 ps
T41 /workspace/coverage/default/2.rom_ctrl_sec_cm.3779096335 Sep 27 01:11:53 PM PDT 23 Sep 27 01:12:59 PM PDT 23 3519668317 ps
T286 /workspace/coverage/default/12.rom_ctrl_alert_test.120210501 Sep 27 01:22:09 PM PDT 23 Sep 27 01:22:15 PM PDT 23 538886658 ps
T16 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2855053527 Sep 27 01:22:13 PM PDT 23 Sep 27 02:12:48 PM PDT 23 83728934803 ps
T287 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.113269722 Sep 27 01:11:48 PM PDT 23 Sep 27 01:12:04 PM PDT 23 1811794281 ps
T288 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3120561986 Sep 27 01:11:50 PM PDT 23 Sep 27 01:11:56 PM PDT 23 617311636 ps
T289 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1732495419 Sep 27 01:12:19 PM PDT 23 Sep 27 01:15:58 PM PDT 23 26033667794 ps
T290 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1833236970 Sep 27 01:11:46 PM PDT 23 Sep 27 01:12:02 PM PDT 23 1840142268 ps
T291 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2112302951 Sep 27 01:12:08 PM PDT 23 Sep 27 01:12:39 PM PDT 23 3621975697 ps
T292 /workspace/coverage/default/31.rom_ctrl_alert_test.1865995085 Sep 27 01:11:36 PM PDT 23 Sep 27 01:11:48 PM PDT 23 1284277564 ps
T293 /workspace/coverage/default/1.rom_ctrl_stress_all.1401533005 Sep 27 01:11:39 PM PDT 23 Sep 27 01:11:58 PM PDT 23 1433241431 ps
T294 /workspace/coverage/default/26.rom_ctrl_smoke.543044198 Sep 27 01:11:57 PM PDT 23 Sep 27 01:12:21 PM PDT 23 5101948670 ps
T295 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3934571102 Sep 27 01:11:55 PM PDT 23 Sep 27 01:18:17 PM PDT 23 37917047048 ps
T296 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.234429736 Sep 27 01:12:20 PM PDT 23 Sep 27 01:18:46 PM PDT 23 40032137206 ps
T297 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1421977755 Sep 27 01:11:42 PM PDT 23 Sep 27 01:59:26 PM PDT 23 34234094143 ps
T298 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3375233616 Sep 27 01:11:35 PM PDT 23 Sep 27 02:48:20 PM PDT 23 25870374905 ps
T299 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2955304973 Sep 27 01:11:56 PM PDT 23 Sep 27 01:12:13 PM PDT 23 12371625133 ps
T300 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.922795414 Sep 27 01:17:38 PM PDT 23 Sep 27 01:22:53 PM PDT 23 146682055678 ps
T301 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.6612447 Sep 27 01:11:35 PM PDT 23 Sep 27 01:15:27 PM PDT 23 29827122192 ps
T302 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4137002963 Sep 27 01:12:01 PM PDT 23 Sep 27 01:15:14 PM PDT 23 167034755253 ps
T303 /workspace/coverage/default/11.rom_ctrl_smoke.3379280999 Sep 27 01:12:18 PM PDT 23 Sep 27 01:12:53 PM PDT 23 7185691618 ps
T304 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.839720534 Sep 27 01:11:52 PM PDT 23 Sep 27 01:12:04 PM PDT 23 1858418211 ps
T305 /workspace/coverage/default/21.rom_ctrl_smoke.3766726646 Sep 27 01:12:05 PM PDT 23 Sep 27 01:12:32 PM PDT 23 2979710207 ps
T306 /workspace/coverage/default/38.rom_ctrl_alert_test.1493531466 Sep 27 01:11:52 PM PDT 23 Sep 27 01:11:56 PM PDT 23 346597635 ps
T307 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.100965526 Sep 27 01:12:02 PM PDT 23 Sep 27 01:14:15 PM PDT 23 27136430757 ps
T308 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2902873175 Sep 27 01:11:53 PM PDT 23 Sep 27 01:12:02 PM PDT 23 2421016840 ps
T309 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.350474389 Sep 27 01:12:03 PM PDT 23 Sep 27 01:12:30 PM PDT 23 15101404329 ps
T310 /workspace/coverage/default/45.rom_ctrl_alert_test.2220099248 Sep 27 01:12:15 PM PDT 23 Sep 27 01:12:26 PM PDT 23 4983629160 ps
T42 /workspace/coverage/default/1.rom_ctrl_sec_cm.3469124603 Sep 27 01:11:41 PM PDT 23 Sep 27 01:12:45 PM PDT 23 12221980567 ps
T49 /workspace/coverage/default/8.rom_ctrl_alert_test.3808743422 Sep 27 01:21:12 PM PDT 23 Sep 27 01:21:17 PM PDT 23 168649741 ps
T50 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3318976755 Sep 27 01:11:17 PM PDT 23 Sep 27 01:15:09 PM PDT 23 187983697199 ps
T51 /workspace/coverage/default/42.rom_ctrl_alert_test.3588336517 Sep 27 01:12:14 PM PDT 23 Sep 27 01:12:30 PM PDT 23 8582631920 ps
T52 /workspace/coverage/default/19.rom_ctrl_alert_test.1841924937 Sep 27 01:11:48 PM PDT 23 Sep 27 01:12:02 PM PDT 23 1835740556 ps
T53 /workspace/coverage/default/38.rom_ctrl_smoke.1727088192 Sep 27 01:11:52 PM PDT 23 Sep 27 01:12:02 PM PDT 23 380834607 ps
T54 /workspace/coverage/default/37.rom_ctrl_stress_all.1187508681 Sep 27 01:11:48 PM PDT 23 Sep 27 01:12:08 PM PDT 23 309245439 ps
T55 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4284480328 Sep 27 01:11:36 PM PDT 23 Sep 27 01:11:46 PM PDT 23 665482085 ps
T56 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3828641334 Sep 27 01:11:15 PM PDT 23 Sep 27 01:11:41 PM PDT 23 10626581575 ps
T311 /workspace/coverage/default/15.rom_ctrl_alert_test.26062779 Sep 27 01:11:40 PM PDT 23 Sep 27 01:11:55 PM PDT 23 9866715741 ps
T312 /workspace/coverage/default/24.rom_ctrl_stress_all.2360109838 Sep 27 01:12:01 PM PDT 23 Sep 27 01:12:18 PM PDT 23 1273839718 ps
T313 /workspace/coverage/default/49.rom_ctrl_alert_test.236990659 Sep 27 01:12:28 PM PDT 23 Sep 27 01:12:42 PM PDT 23 6318218436 ps
T43 /workspace/coverage/default/3.rom_ctrl_sec_cm.97307697 Sep 27 01:11:17 PM PDT 23 Sep 27 01:12:28 PM PDT 23 4117929625 ps
T314 /workspace/coverage/default/15.rom_ctrl_smoke.1706961610 Sep 27 01:11:44 PM PDT 23 Sep 27 01:11:56 PM PDT 23 563589222 ps
T315 /workspace/coverage/default/27.rom_ctrl_stress_all.1633224798 Sep 27 01:11:38 PM PDT 23 Sep 27 01:12:33 PM PDT 23 12706735417 ps
T316 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2267197767 Sep 27 01:11:57 PM PDT 23 Sep 27 01:12:07 PM PDT 23 175379515 ps
T317 /workspace/coverage/default/42.rom_ctrl_smoke.894480776 Sep 27 01:12:06 PM PDT 23 Sep 27 01:12:39 PM PDT 23 28755430039 ps
T318 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2957867118 Sep 27 01:12:13 PM PDT 23 Sep 27 01:44:01 PM PDT 23 187552915650 ps
T319 /workspace/coverage/default/19.rom_ctrl_stress_all.2186781090 Sep 27 01:11:46 PM PDT 23 Sep 27 01:11:58 PM PDT 23 1165378973 ps
T320 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.82759709 Sep 27 01:11:46 PM PDT 23 Sep 27 01:12:11 PM PDT 23 9439202778 ps
T321 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.637494563 Sep 27 01:11:55 PM PDT 23 Sep 27 01:48:14 PM PDT 23 17984318803 ps
T322 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.845585773 Sep 27 01:12:06 PM PDT 23 Sep 27 01:12:23 PM PDT 23 1811092683 ps
T323 /workspace/coverage/default/28.rom_ctrl_smoke.2561176846 Sep 27 01:12:58 PM PDT 23 Sep 27 01:13:28 PM PDT 23 3475672052 ps
T324 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4245644124 Sep 27 01:11:52 PM PDT 23 Sep 27 01:13:04 PM PDT 23 1250423778 ps
T325 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.324273964 Sep 27 01:11:04 PM PDT 23 Sep 27 01:11:39 PM PDT 23 17729495881 ps
T15 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3765643256 Sep 27 01:11:55 PM PDT 23 Sep 27 01:35:59 PM PDT 23 24358300441 ps
T326 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4115124946 Sep 27 01:12:11 PM PDT 23 Sep 27 01:12:41 PM PDT 23 6398780195 ps
T327 /workspace/coverage/default/35.rom_ctrl_smoke.2070396663 Sep 27 01:11:50 PM PDT 23 Sep 27 01:12:24 PM PDT 23 3403760201 ps
T328 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2197075931 Sep 27 01:12:15 PM PDT 23 Sep 27 01:12:31 PM PDT 23 1888018051 ps
T329 /workspace/coverage/default/3.rom_ctrl_alert_test.3244859822 Sep 27 01:11:19 PM PDT 23 Sep 27 01:11:26 PM PDT 23 387569473 ps
T330 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2077500644 Sep 27 01:11:47 PM PDT 23 Sep 27 01:33:16 PM PDT 23 101712438017 ps
T331 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1730849212 Sep 27 01:12:06 PM PDT 23 Sep 27 01:12:20 PM PDT 23 6900623095 ps
T332 /workspace/coverage/default/29.rom_ctrl_smoke.992372251 Sep 27 01:11:56 PM PDT 23 Sep 27 01:12:24 PM PDT 23 12085459768 ps
T333 /workspace/coverage/default/26.rom_ctrl_alert_test.480944755 Sep 27 01:11:46 PM PDT 23 Sep 27 01:11:57 PM PDT 23 7364405660 ps
T334 /workspace/coverage/default/10.rom_ctrl_stress_all.2222501388 Sep 27 01:12:00 PM PDT 23 Sep 27 01:14:00 PM PDT 23 46348439563 ps
T335 /workspace/coverage/default/40.rom_ctrl_smoke.956808411 Sep 27 01:11:52 PM PDT 23 Sep 27 01:12:03 PM PDT 23 958549381 ps
T336 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2680667443 Sep 27 01:13:05 PM PDT 23 Sep 27 01:15:22 PM PDT 23 12927540990 ps
T337 /workspace/coverage/default/0.rom_ctrl_stress_all.2998157193 Sep 27 01:20:48 PM PDT 23 Sep 27 01:21:23 PM PDT 23 3932288350 ps
T338 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.202507429 Sep 27 01:11:48 PM PDT 23 Sep 27 01:15:02 PM PDT 23 15015572157 ps
T339 /workspace/coverage/default/48.rom_ctrl_stress_all.4176915197 Sep 27 01:11:59 PM PDT 23 Sep 27 01:13:00 PM PDT 23 28313598699 ps
T36 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3816505685 Sep 27 01:11:05 PM PDT 23 Sep 27 01:11:24 PM PDT 23 7751153733 ps
T340 /workspace/coverage/default/14.rom_ctrl_alert_test.1002727547 Sep 27 01:11:49 PM PDT 23 Sep 27 01:11:54 PM PDT 23 132172266 ps
T341 /workspace/coverage/default/38.rom_ctrl_stress_all.4165152339 Sep 27 01:11:48 PM PDT 23 Sep 27 01:12:20 PM PDT 23 12903935984 ps
T342 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1748882459 Sep 27 01:14:06 PM PDT 23 Sep 27 01:14:32 PM PDT 23 10489801719 ps
T343 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.377014172 Sep 27 01:12:15 PM PDT 23 Sep 27 01:12:21 PM PDT 23 190433861 ps
T344 /workspace/coverage/default/43.rom_ctrl_stress_all.2699991748 Sep 27 01:11:52 PM PDT 23 Sep 27 01:12:05 PM PDT 23 1091290432 ps
T345 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3569406823 Sep 27 01:12:10 PM PDT 23 Sep 27 01:57:29 PM PDT 23 246986420333 ps
T346 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1780186422 Sep 27 01:14:07 PM PDT 23 Sep 27 03:51:17 PM PDT 23 121871589374 ps
T347 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3285116931 Sep 27 01:11:33 PM PDT 23 Sep 27 01:44:39 PM PDT 23 46683720361 ps
T348 /workspace/coverage/default/37.rom_ctrl_smoke.3921803386 Sep 27 01:12:18 PM PDT 23 Sep 27 01:12:44 PM PDT 23 2157735609 ps
T349 /workspace/coverage/default/5.rom_ctrl_smoke.23912298 Sep 27 01:12:01 PM PDT 23 Sep 27 01:12:31 PM PDT 23 16401956448 ps
T350 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1204589097 Sep 27 01:11:48 PM PDT 23 Sep 27 01:12:24 PM PDT 23 5291872293 ps
T351 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.315356911 Sep 27 01:11:47 PM PDT 23 Sep 27 02:12:37 PM PDT 23 137615626249 ps
T352 /workspace/coverage/default/17.rom_ctrl_stress_all.2567312677 Sep 27 01:11:51 PM PDT 23 Sep 27 01:12:39 PM PDT 23 23762500608 ps
T353 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.503413509 Sep 27 01:11:19 PM PDT 23 Sep 27 01:11:34 PM PDT 23 6439884399 ps
T354 /workspace/coverage/default/14.rom_ctrl_stress_all.455660722 Sep 27 01:11:45 PM PDT 23 Sep 27 01:12:37 PM PDT 23 3990047930 ps
T355 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3400116790 Sep 27 01:11:20 PM PDT 23 Sep 27 01:13:13 PM PDT 23 4863377858 ps
T356 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1367531615 Sep 27 01:11:34 PM PDT 23 Sep 27 01:15:13 PM PDT 23 21392513610 ps
T357 /workspace/coverage/default/49.rom_ctrl_stress_all.34694401 Sep 27 01:12:01 PM PDT 23 Sep 27 01:12:25 PM PDT 23 1575064488 ps
T358 /workspace/coverage/default/33.rom_ctrl_alert_test.3137440958 Sep 27 01:11:37 PM PDT 23 Sep 27 01:11:43 PM PDT 23 174910536 ps
T359 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2028863385 Sep 27 01:12:16 PM PDT 23 Sep 27 01:12:30 PM PDT 23 2480279224 ps
T360 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3977598147 Sep 27 01:11:03 PM PDT 23 Sep 27 01:11:20 PM PDT 23 3755018403 ps
T361 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.451976152 Sep 27 01:12:00 PM PDT 23 Sep 27 01:13:51 PM PDT 23 15956604688 ps
T362 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3692094359 Sep 27 01:14:24 PM PDT 23 Sep 27 01:14:37 PM PDT 23 1077569151 ps
T363 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2807484598 Sep 27 01:11:53 PM PDT 23 Sep 27 01:12:11 PM PDT 23 4129549947 ps
T364 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.924564623 Sep 27 01:12:07 PM PDT 23 Sep 27 01:12:20 PM PDT 23 3996017134 ps
T365 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2160323837 Sep 27 01:11:53 PM PDT 23 Sep 27 01:12:12 PM PDT 23 1509887797 ps
T366 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.898525317 Sep 27 01:11:36 PM PDT 23 Sep 27 01:12:05 PM PDT 23 7978957511 ps
T367 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2751210595 Sep 27 01:11:58 PM PDT 23 Sep 27 01:17:21 PM PDT 23 134707387690 ps
T368 /workspace/coverage/default/18.rom_ctrl_smoke.3430713374 Sep 27 01:11:44 PM PDT 23 Sep 27 01:11:58 PM PDT 23 692701608 ps
T369 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1144287005 Sep 27 01:17:04 PM PDT 23 Sep 27 01:17:10 PM PDT 23 532910497 ps
T47 /workspace/coverage/default/0.rom_ctrl_sec_cm.3348722765 Sep 27 01:11:47 PM PDT 23 Sep 27 01:12:50 PM PDT 23 1178589928 ps
T370 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.288198414 Sep 27 01:11:45 PM PDT 23 Sep 27 01:14:54 PM PDT 23 12019529896 ps
T371 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4052229524 Sep 27 01:11:50 PM PDT 23 Sep 27 01:16:21 PM PDT 23 22312403076 ps
T372 /workspace/coverage/default/44.rom_ctrl_stress_all.341491670 Sep 27 01:11:52 PM PDT 23 Sep 27 01:12:31 PM PDT 23 19386481620 ps
T373 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.978661727 Sep 27 01:12:04 PM PDT 23 Sep 27 01:12:11 PM PDT 23 379814113 ps
T374 /workspace/coverage/default/42.rom_ctrl_stress_all.110930137 Sep 27 01:11:54 PM PDT 23 Sep 27 01:12:44 PM PDT 23 16729447248 ps
T375 /workspace/coverage/default/5.rom_ctrl_stress_all.3720084862 Sep 27 01:12:16 PM PDT 23 Sep 27 01:13:39 PM PDT 23 40359239958 ps
T376 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1993944555 Sep 27 01:12:05 PM PDT 23 Sep 27 01:12:11 PM PDT 23 539835113 ps
T377 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1270724191 Sep 27 01:11:21 PM PDT 23 Sep 27 01:11:37 PM PDT 23 940480625 ps
T378 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.985072888 Sep 27 01:11:46 PM PDT 23 Sep 27 01:34:03 PM PDT 23 40853798448 ps
T379 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4238445773 Sep 27 01:12:12 PM PDT 23 Sep 27 01:12:40 PM PDT 23 3021924120 ps
T380 /workspace/coverage/default/4.rom_ctrl_stress_all.292418529 Sep 27 01:11:51 PM PDT 23 Sep 27 01:12:18 PM PDT 23 387435023 ps
T381 /workspace/coverage/default/46.rom_ctrl_smoke.2121374551 Sep 27 01:12:15 PM PDT 23 Sep 27 01:12:41 PM PDT 23 9919708944 ps
T382 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2256680035 Sep 27 01:11:20 PM PDT 23 Sep 27 01:14:21 PM PDT 23 16014136216 ps
T383 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2053128747 Sep 27 01:11:17 PM PDT 23 Sep 27 01:54:06 PM PDT 23 132750506305 ps
T384 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2442622002 Sep 27 01:12:08 PM PDT 23 Sep 27 01:12:24 PM PDT 23 1867990270 ps
T385 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3904237533 Sep 27 01:12:41 PM PDT 23 Sep 27 01:44:37 PM PDT 23 35046509650 ps
T386 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.776596227 Sep 27 01:19:44 PM PDT 23 Sep 27 01:20:19 PM PDT 23 27371270154 ps
T387 /workspace/coverage/default/4.rom_ctrl_alert_test.860348480 Sep 27 01:11:54 PM PDT 23 Sep 27 01:12:09 PM PDT 23 1859312216 ps
T388 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1235046553 Sep 27 01:11:53 PM PDT 23 Sep 27 01:19:13 PM PDT 23 237727465103 ps
T389 /workspace/coverage/default/37.rom_ctrl_alert_test.1577506818 Sep 27 01:11:48 PM PDT 23 Sep 27 01:12:05 PM PDT 23 19593619832 ps
T390 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1694598900 Sep 27 01:22:29 PM PDT 23 Sep 27 01:28:17 PM PDT 23 619257006533 ps
T391 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2102657335 Sep 27 01:11:50 PM PDT 23 Sep 27 02:13:28 PM PDT 23 354316543202 ps
T392 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2445748187 Sep 27 01:11:51 PM PDT 23 Sep 27 01:12:00 PM PDT 23 591705918 ps
T393 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2622948110 Sep 27 01:12:08 PM PDT 23 Sep 27 01:15:33 PM PDT 23 19907390895 ps
T394 /workspace/coverage/default/41.rom_ctrl_stress_all.3899094255 Sep 27 01:12:08 PM PDT 23 Sep 27 01:13:14 PM PDT 23 5861122011 ps
T395 /workspace/coverage/default/31.rom_ctrl_smoke.2356309299 Sep 27 01:11:35 PM PDT 23 Sep 27 01:12:04 PM PDT 23 11778651368 ps
T396 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2275053829 Sep 27 01:12:05 PM PDT 23 Sep 27 01:12:37 PM PDT 23 3762438833 ps
T397 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2504176705 Sep 27 01:12:11 PM PDT 23 Sep 27 01:15:48 PM PDT 23 246475553644 ps
T398 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1215961544 Sep 27 01:11:14 PM PDT 23 Sep 27 01:11:47 PM PDT 23 4065982617 ps
T399 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2803978141 Sep 27 01:12:07 PM PDT 23 Sep 27 01:15:03 PM PDT 23 9539943129 ps
T400 /workspace/coverage/default/30.rom_ctrl_stress_all.1358673696 Sep 27 01:11:57 PM PDT 23 Sep 27 01:12:17 PM PDT 23 4410207719 ps
T401 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4172382439 Sep 27 01:28:58 PM PDT 23 Sep 27 01:29:15 PM PDT 23 25367112699 ps
T402 /workspace/coverage/default/43.rom_ctrl_smoke.341639642 Sep 27 01:11:50 PM PDT 23 Sep 27 01:12:17 PM PDT 23 18729687648 ps
T403 /workspace/coverage/default/34.rom_ctrl_alert_test.1252427369 Sep 27 01:12:08 PM PDT 23 Sep 27 01:12:13 PM PDT 23 85779126 ps
T404 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2374238480 Sep 27 01:11:46 PM PDT 23 Sep 27 01:13:45 PM PDT 23 11647102998 ps
T405 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3128693179 Sep 27 01:12:47 PM PDT 23 Sep 27 01:13:09 PM PDT 23 1911196574 ps
T406 /workspace/coverage/default/39.rom_ctrl_alert_test.4057810817 Sep 27 01:11:55 PM PDT 23 Sep 27 01:12:00 PM PDT 23 89149377 ps
T407 /workspace/coverage/default/11.rom_ctrl_alert_test.1177625448 Sep 27 01:21:12 PM PDT 23 Sep 27 01:21:17 PM PDT 23 689557393 ps
T408 /workspace/coverage/default/19.rom_ctrl_smoke.4193084985 Sep 27 01:12:09 PM PDT 23 Sep 27 01:12:20 PM PDT 23 360804416 ps
T409 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2801341558 Sep 27 01:12:01 PM PDT 23 Sep 27 01:12:37 PM PDT 23 18287060146 ps
T410 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2749846457 Sep 27 01:12:11 PM PDT 23 Sep 27 01:12:37 PM PDT 23 43405458116 ps
T411 /workspace/coverage/default/36.rom_ctrl_alert_test.3113897172 Sep 27 01:11:55 PM PDT 23 Sep 27 01:12:00 PM PDT 23 93011375 ps
T412 /workspace/coverage/default/39.rom_ctrl_smoke.3651819474 Sep 27 01:11:49 PM PDT 23 Sep 27 01:12:14 PM PDT 23 3937150124 ps
T413 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3472178292 Sep 27 01:11:03 PM PDT 23 Sep 27 01:11:15 PM PDT 23 4683506408 ps
T414 /workspace/coverage/default/3.rom_ctrl_smoke.50049342 Sep 27 01:11:53 PM PDT 23 Sep 27 01:12:04 PM PDT 23 343960334 ps
T415 /workspace/coverage/default/40.rom_ctrl_stress_all.2922906683 Sep 27 01:11:58 PM PDT 23 Sep 27 01:12:05 PM PDT 23 134915233 ps
T416 /workspace/coverage/default/44.rom_ctrl_alert_test.2456867223 Sep 27 01:11:58 PM PDT 23 Sep 27 01:12:08 PM PDT 23 1064445347 ps
T417 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.364047126 Sep 27 01:11:19 PM PDT 23 Sep 27 01:15:38 PM PDT 23 282835250828 ps
T418 /workspace/coverage/default/8.rom_ctrl_smoke.144931528 Sep 27 01:20:40 PM PDT 23 Sep 27 01:20:53 PM PDT 23 1686018448 ps
T419 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3210635248 Sep 27 01:11:55 PM PDT 23 Sep 27 01:12:11 PM PDT 23 1999015430 ps
T420 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2663546775 Sep 27 01:12:01 PM PDT 23 Sep 27 01:12:12 PM PDT 23 168414290 ps
T421 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3484230774 Sep 27 01:11:51 PM PDT 23 Sep 27 01:20:24 PM PDT 23 88939053740 ps
T422 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1891991769 Sep 27 01:11:05 PM PDT 23 Sep 27 01:13:54 PM PDT 23 49926314007 ps
T423 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1778804434 Sep 27 01:12:13 PM PDT 23 Sep 27 01:12:19 PM PDT 23 1137131760 ps
T424 /workspace/coverage/default/13.rom_ctrl_smoke.4224650020 Sep 27 01:13:21 PM PDT 23 Sep 27 01:13:31 PM PDT 23 943913957 ps
T425 /workspace/coverage/default/41.rom_ctrl_smoke.3650344504 Sep 27 01:11:59 PM PDT 23 Sep 27 01:12:32 PM PDT 23 3842329305 ps
T426 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1224663654 Sep 27 01:11:53 PM PDT 23 Sep 27 02:10:56 PM PDT 23 374792268423 ps
T427 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3924407818 Sep 27 01:11:20 PM PDT 23 Sep 27 04:03:33 PM PDT 23 241857532831 ps
T48 /workspace/coverage/default/4.rom_ctrl_sec_cm.311193933 Sep 27 01:11:54 PM PDT 23 Sep 27 01:13:57 PM PDT 23 2328374290 ps
T428 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.841990692 Sep 27 12:38:07 PM PDT 23 Sep 27 12:38:14 PM PDT 23 475059833 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.961984899 Sep 27 12:37:14 PM PDT 23 Sep 27 12:37:30 PM PDT 23 3853310387 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3196367449 Sep 27 12:46:48 PM PDT 23 Sep 27 12:47:04 PM PDT 23 2025597184 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.535332996 Sep 27 12:43:28 PM PDT 23 Sep 27 12:45:48 PM PDT 23 24344372177 ps
T431 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2092221254 Sep 27 12:38:40 PM PDT 23 Sep 27 12:38:49 PM PDT 23 1900662366 ps
T120 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3730697219 Sep 27 12:37:52 PM PDT 23 Sep 27 12:39:14 PM PDT 23 1383851925 ps
T432 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4124671730 Sep 27 12:37:24 PM PDT 23 Sep 27 12:37:38 PM PDT 23 931052299 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2562755709 Sep 27 12:35:18 PM PDT 23 Sep 27 12:35:33 PM PDT 23 1825450058 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3330438535 Sep 27 12:40:15 PM PDT 23 Sep 27 12:41:07 PM PDT 23 2242868542 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3589889817 Sep 27 12:37:37 PM PDT 23 Sep 27 12:37:53 PM PDT 23 7890346688 ps
T435 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1383892637 Sep 27 12:38:07 PM PDT 23 Sep 27 12:38:22 PM PDT 23 1933707851 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.528621328 Sep 27 12:39:08 PM PDT 23 Sep 27 12:39:12 PM PDT 23 85534322 ps
T119 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.961726694 Sep 27 12:42:51 PM PDT 23 Sep 27 12:44:05 PM PDT 23 779233333 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.795691937 Sep 27 12:36:00 PM PDT 23 Sep 27 12:36:08 PM PDT 23 2143183662 ps
T94 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.574268878 Sep 27 12:53:45 PM PDT 23 Sep 27 12:58:48 PM PDT 23 57009653496 ps
T438 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1646840520 Sep 27 12:35:59 PM PDT 23 Sep 27 12:36:48 PM PDT 23 3931634803 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3210153310 Sep 27 12:36:23 PM PDT 23 Sep 27 12:36:30 PM PDT 23 171731727 ps
T440 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2833575129 Sep 27 12:37:08 PM PDT 23 Sep 27 12:37:21 PM PDT 23 4079846020 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2469668135 Sep 27 12:42:51 PM PDT 23 Sep 27 12:43:09 PM PDT 23 2214707942 ps
T442 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.369168660 Sep 27 12:38:13 PM PDT 23 Sep 27 12:38:32 PM PDT 23 2234838977 ps
T443 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3255293850 Sep 27 12:54:06 PM PDT 23 Sep 27 12:54:14 PM PDT 23 595313998 ps
T95 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2714652393 Sep 27 12:38:46 PM PDT 23 Sep 27 12:39:01 PM PDT 23 6966985550 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3502542696 Sep 27 12:57:52 PM PDT 23 Sep 27 12:57:57 PM PDT 23 89299735 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1156452274 Sep 27 12:37:36 PM PDT 23 Sep 27 12:37:41 PM PDT 23 827035142 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.141821020 Sep 27 12:40:18 PM PDT 23 Sep 27 12:41:41 PM PDT 23 5597628822 ps
T447 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2171026007 Sep 27 12:37:02 PM PDT 23 Sep 27 12:37:41 PM PDT 23 822868553 ps
T448 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.105254003 Sep 27 12:39:27 PM PDT 23 Sep 27 12:39:39 PM PDT 23 4761462126 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3064946232 Sep 27 12:44:58 PM PDT 23 Sep 27 12:45:13 PM PDT 23 7028908922 ps
T450 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1229985668 Sep 27 12:36:15 PM PDT 23 Sep 27 12:36:24 PM PDT 23 841538520 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2052235790 Sep 27 12:50:03 PM PDT 23 Sep 27 12:50:21 PM PDT 23 6810898287 ps
T452 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2027823795 Sep 27 12:42:40 PM PDT 23 Sep 27 12:43:35 PM PDT 23 3890066025 ps
T96 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.465196212 Sep 27 12:44:05 PM PDT 23 Sep 27 12:44:09 PM PDT 23 89172573 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.994543831 Sep 27 12:50:28 PM PDT 23 Sep 27 12:50:35 PM PDT 23 1977301364 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4130526561 Sep 27 12:35:03 PM PDT 23 Sep 27 12:36:27 PM PDT 23 2239332969 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1124876764 Sep 27 12:39:52 PM PDT 23 Sep 27 12:40:04 PM PDT 23 1251636095 ps
T456 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3445619923 Sep 27 12:35:58 PM PDT 23 Sep 27 12:36:43 PM PDT 23 2277246411 ps
T457 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1547785496 Sep 27 12:40:05 PM PDT 23 Sep 27 12:40:18 PM PDT 23 1179142476 ps
T458 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.364226743 Sep 27 12:51:32 PM PDT 23 Sep 27 12:51:49 PM PDT 23 2923875374 ps
T121 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3217139329 Sep 27 12:39:56 PM PDT 23 Sep 27 12:41:17 PM PDT 23 375780298 ps
T459 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4095791040 Sep 27 12:39:01 PM PDT 23 Sep 27 12:39:06 PM PDT 23 569397556 ps
T460 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3714975144 Sep 27 12:40:21 PM PDT 23 Sep 27 12:41:28 PM PDT 23 9726795785 ps
T461 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4109227854 Sep 27 12:45:27 PM PDT 23 Sep 27 12:45:31 PM PDT 23 168122620 ps
T462 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.639494468 Sep 27 12:37:26 PM PDT 23 Sep 27 12:37:31 PM PDT 23 439206244 ps
T463 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3493253676 Sep 27 12:38:42 PM PDT 23 Sep 27 12:38:53 PM PDT 23 6451113165 ps
T464 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1794601441 Sep 27 12:41:31 PM PDT 23 Sep 27 12:41:40 PM PDT 23 689950560 ps
T465 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1881612527 Sep 27 12:44:59 PM PDT 23 Sep 27 12:45:16 PM PDT 23 11998481066 ps
T466 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4260943307 Sep 27 12:35:17 PM PDT 23 Sep 27 12:35:35 PM PDT 23 8814558097 ps
T109 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3847392734 Sep 27 12:35:47 PM PDT 23 Sep 27 12:35:56 PM PDT 23 126873881 ps
T467 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.195570076 Sep 27 12:35:18 PM PDT 23 Sep 27 12:35:25 PM PDT 23 878415150 ps
T468 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.217558224 Sep 27 12:36:15 PM PDT 23 Sep 27 12:37:04 PM PDT 23 3294128760 ps
T469 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1859168722 Sep 27 12:36:55 PM PDT 23 Sep 27 12:37:10 PM PDT 23 11802766226 ps
T470 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.762738727 Sep 27 12:36:23 PM PDT 23 Sep 27 12:36:27 PM PDT 23 563420475 ps
T471 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3635609416 Sep 27 12:43:18 PM PDT 23 Sep 27 12:43:23 PM PDT 23 177622409 ps
T472 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4097008047 Sep 27 12:45:27 PM PDT 23 Sep 27 12:45:45 PM PDT 23 8914905339 ps
T473 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2806894777 Sep 27 12:39:05 PM PDT 23 Sep 27 12:39:16 PM PDT 23 9356899815 ps
T474 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3336010849 Sep 27 12:35:58 PM PDT 23 Sep 27 12:40:42 PM PDT 23 31490134687 ps
T475 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1463721694 Sep 27 12:38:20 PM PDT 23 Sep 27 12:38:33 PM PDT 23 10220406791 ps
T476 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3326597838 Sep 27 12:37:27 PM PDT 23 Sep 27 12:37:38 PM PDT 23 4485992933 ps
T477 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2134623475 Sep 27 12:42:51 PM PDT 23 Sep 27 12:43:01 PM PDT 23 2391460405 ps
T478 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1869997341 Sep 27 12:34:58 PM PDT 23 Sep 27 12:35:11 PM PDT 23 3283514231 ps
T479 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2998505305 Sep 27 12:35:53 PM PDT 23 Sep 27 12:39:24 PM PDT 23 20981981913 ps
T122 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1730563898 Sep 27 12:46:43 PM PDT 23 Sep 27 12:47:57 PM PDT 23 1712412541 ps
T480 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2075661698 Sep 27 12:36:21 PM PDT 23 Sep 27 12:40:59 PM PDT 23 120914721137 ps

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2372784077
Short name T22
Test name
Test status
Simulation time 2123223422 ps
CPU time 16.92 seconds
Started Sep 27 12:43:16 PM PDT 23
Finished Sep 27 12:43:33 PM PDT 23
Peak memory 217276 kb
Host smart-cc36f9a0-ad5d-4d70-af48-b531e10d36b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372784077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2372784077
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3675962266
Short name T5
Test name
Test status
Simulation time 9147912955 ps
CPU time 59.22 seconds
Started Sep 27 01:12:06 PM PDT 23
Finished Sep 27 01:13:05 PM PDT 23
Peak memory 214992 kb
Host smart-f8e284e7-1594-44ff-a153-11d4a52376d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675962266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3675962266
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.76120076
Short name T23
Test name
Test status
Simulation time 37940778388 ps
CPU time 379.07 seconds
Started Sep 27 12:45:33 PM PDT 23
Finished Sep 27 12:51:53 PM PDT 23
Peak memory 210720 kb
Host smart-6a909122-96ed-4a6f-bb99-5f1aa98450e6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76120076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pas
sthru_mem_tl_intg_err.76120076
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1467166179
Short name T25
Test name
Test status
Simulation time 1275133655 ps
CPU time 10.61 seconds
Started Sep 27 12:36:04 PM PDT 23
Finished Sep 27 12:36:15 PM PDT 23
Peak memory 218812 kb
Host smart-a52caad4-b3a0-43bd-8af2-eabbb8bd0a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467166179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1467166179
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1841284819
Short name T67
Test name
Test status
Simulation time 4377115096 ps
CPU time 88.88 seconds
Started Sep 27 12:38:35 PM PDT 23
Finished Sep 27 12:40:04 PM PDT 23
Peak memory 218860 kb
Host smart-3d102360-d5d6-4cc3-beb5-7a3298ccc196
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841284819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1841284819
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3991902832
Short name T8
Test name
Test status
Simulation time 21483736503 ps
CPU time 167.35 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:14:35 PM PDT 23
Peak memory 237936 kb
Host smart-45a4841b-8f58-4dcf-8fd4-a34faa7d96dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991902832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3991902832
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3840922566
Short name T14
Test name
Test status
Simulation time 74425356624 ps
CPU time 1378.63 seconds
Started Sep 27 01:11:55 PM PDT 23
Finished Sep 27 01:34:54 PM PDT 23
Peak memory 235824 kb
Host smart-5b66b233-bb6b-49e9-b1bb-3a73397cb901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840922566 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3840922566
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2991628151
Short name T69
Test name
Test status
Simulation time 2283610089 ps
CPU time 19.24 seconds
Started Sep 27 12:55:52 PM PDT 23
Finished Sep 27 12:56:12 PM PDT 23
Peak memory 219076 kb
Host smart-4d3ff684-402e-4bb4-b6a2-8fd8efcf7080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991628151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2991628151
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.961726694
Short name T119
Test name
Test status
Simulation time 779233333 ps
CPU time 73.71 seconds
Started Sep 27 12:42:51 PM PDT 23
Finished Sep 27 12:44:05 PM PDT 23
Peak memory 212172 kb
Host smart-0e9bb577-3d64-4278-8351-6a559a7b44b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961726694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.961726694
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3348722765
Short name T47
Test name
Test status
Simulation time 1178589928 ps
CPU time 62.51 seconds
Started Sep 27 01:11:47 PM PDT 23
Finished Sep 27 01:12:50 PM PDT 23
Peak memory 234960 kb
Host smart-7dc62f34-36f4-485e-91b6-2c0930eef176
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348722765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3348722765
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2855053527
Short name T16
Test name
Test status
Simulation time 83728934803 ps
CPU time 3033.8 seconds
Started Sep 27 01:22:13 PM PDT 23
Finished Sep 27 02:12:48 PM PDT 23
Peak memory 245928 kb
Host smart-d123cd35-fbed-4d48-8657-e0606c81d3ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855053527 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2855053527
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1730563898
Short name T122
Test name
Test status
Simulation time 1712412541 ps
CPU time 74.12 seconds
Started Sep 27 12:46:43 PM PDT 23
Finished Sep 27 12:47:57 PM PDT 23
Peak memory 212216 kb
Host smart-6636f339-db7d-4796-a772-77016f96cf3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730563898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1730563898
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2711497188
Short name T169
Test name
Test status
Simulation time 4095364584 ps
CPU time 21.81 seconds
Started Sep 27 01:19:55 PM PDT 23
Finished Sep 27 01:20:19 PM PDT 23
Peak memory 211252 kb
Host smart-7de5e288-dda9-48d1-9144-5993ff970c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711497188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2711497188
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3816505685
Short name T36
Test name
Test status
Simulation time 7751153733 ps
CPU time 18.6 seconds
Started Sep 27 01:11:05 PM PDT 23
Finished Sep 27 01:11:24 PM PDT 23
Peak memory 211856 kb
Host smart-8039e2ee-d141-4ede-a996-962a6b56a026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816505685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3816505685
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2801341558
Short name T409
Test name
Test status
Simulation time 18287060146 ps
CPU time 35.61 seconds
Started Sep 27 01:12:01 PM PDT 23
Finished Sep 27 01:12:37 PM PDT 23
Peak memory 211596 kb
Host smart-30ec9c3b-47e8-4fa9-be59-62fedbc81f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801341558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2801341558
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3377288993
Short name T136
Test name
Test status
Simulation time 544083543 ps
CPU time 6.87 seconds
Started Sep 27 12:38:42 PM PDT 23
Finished Sep 27 12:38:49 PM PDT 23
Peak memory 210612 kb
Host smart-7affb423-9092-4cfb-8bf6-2b4a3c13d516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377288993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3377288993
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.606654059
Short name T124
Test name
Test status
Simulation time 617241342 ps
CPU time 10.97 seconds
Started Sep 27 12:35:58 PM PDT 23
Finished Sep 27 12:36:09 PM PDT 23
Peak memory 218844 kb
Host smart-0fa52759-84b8-4980-8e63-13d513c04d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606654059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.606654059
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1297380525
Short name T9
Test name
Test status
Simulation time 168072152 ps
CPU time 4.26 seconds
Started Sep 27 01:11:42 PM PDT 23
Finished Sep 27 01:11:47 PM PDT 23
Peak memory 211084 kb
Host smart-a5a42a52-4c2a-4186-8385-70b9ad6d75de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297380525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1297380525
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3847392734
Short name T109
Test name
Test status
Simulation time 126873881 ps
CPU time 8.56 seconds
Started Sep 27 12:35:47 PM PDT 23
Finished Sep 27 12:35:56 PM PDT 23
Peak memory 218872 kb
Host smart-e569d32f-8a87-4928-ac30-459ec4d9eaa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847392734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3847392734
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3217139329
Short name T121
Test name
Test status
Simulation time 375780298 ps
CPU time 80.24 seconds
Started Sep 27 12:39:56 PM PDT 23
Finished Sep 27 12:41:17 PM PDT 23
Peak memory 211848 kb
Host smart-7863ebf0-e8c5-4cc0-8d7a-55e521cda672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217139329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3217139329
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.508176442
Short name T111
Test name
Test status
Simulation time 23063054030 ps
CPU time 6433.85 seconds
Started Sep 27 01:11:47 PM PDT 23
Finished Sep 27 02:59:02 PM PDT 23
Peak memory 229560 kb
Host smart-6253ac4e-d747-402b-9d89-4540b3d1f9fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508176442 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.508176442
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3879872128
Short name T75
Test name
Test status
Simulation time 663896359 ps
CPU time 8.88 seconds
Started Sep 27 12:40:05 PM PDT 23
Finished Sep 27 12:40:14 PM PDT 23
Peak memory 215680 kb
Host smart-be40e610-a21b-4f31-88a0-6c546ea2bcce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879872128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3879872128
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2674370062
Short name T138
Test name
Test status
Simulation time 2916550139 ps
CPU time 17.07 seconds
Started Sep 27 12:36:10 PM PDT 23
Finished Sep 27 12:36:27 PM PDT 23
Peak memory 210688 kb
Host smart-952b3e06-9dba-4ba3-9148-48129c69cc86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674370062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2674370062
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3589889817
Short name T93
Test name
Test status
Simulation time 7890346688 ps
CPU time 15.25 seconds
Started Sep 27 12:37:37 PM PDT 23
Finished Sep 27 12:37:53 PM PDT 23
Peak memory 210784 kb
Host smart-b6657201-81ce-49d8-b5ab-351fede6e877
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589889817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3589889817
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1869997341
Short name T478
Test name
Test status
Simulation time 3283514231 ps
CPU time 12.52 seconds
Started Sep 27 12:34:58 PM PDT 23
Finished Sep 27 12:35:11 PM PDT 23
Peak memory 218352 kb
Host smart-048eafee-409f-4176-b380-007c06e0c919
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869997341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1869997341
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1124876764
Short name T455
Test name
Test status
Simulation time 1251636095 ps
CPU time 11.93 seconds
Started Sep 27 12:39:52 PM PDT 23
Finished Sep 27 12:40:04 PM PDT 23
Peak memory 218868 kb
Host smart-3ef081c3-ee57-4960-ac82-d37f8698680d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124876764 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1124876764
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1794601441
Short name T464
Test name
Test status
Simulation time 689950560 ps
CPU time 8.7 seconds
Started Sep 27 12:41:31 PM PDT 23
Finished Sep 27 12:41:40 PM PDT 23
Peak memory 210620 kb
Host smart-d5bea9b7-e16c-4c34-92c0-f4c1cb75719c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794601441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1794601441
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1129969790
Short name T132
Test name
Test status
Simulation time 3847277420 ps
CPU time 15.32 seconds
Started Sep 27 12:50:05 PM PDT 23
Finished Sep 27 12:50:21 PM PDT 23
Peak memory 210764 kb
Host smart-35bbdf09-e54f-4d54-9ccc-b018beb56258
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129969790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1129969790
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.722071112
Short name T146
Test name
Test status
Simulation time 85537195 ps
CPU time 4.39 seconds
Started Sep 27 12:36:08 PM PDT 23
Finished Sep 27 12:36:13 PM PDT 23
Peak memory 210736 kb
Host smart-26261e8d-a6b0-4242-ab0b-a23ec2f8cb11
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722071112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
722071112
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.574268878
Short name T94
Test name
Test status
Simulation time 57009653496 ps
CPU time 302.15 seconds
Started Sep 27 12:53:45 PM PDT 23
Finished Sep 27 12:58:48 PM PDT 23
Peak memory 218896 kb
Host smart-cc112946-6f6d-44b0-9215-46961a73326c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574268878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.574268878
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1156452274
Short name T445
Test name
Test status
Simulation time 827035142 ps
CPU time 4.29 seconds
Started Sep 27 12:37:36 PM PDT 23
Finished Sep 27 12:37:41 PM PDT 23
Peak memory 210640 kb
Host smart-523483b7-4d90-4984-b1cd-bdcf7ff52b61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156452274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1156452274
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2052235790
Short name T451
Test name
Test status
Simulation time 6810898287 ps
CPU time 18.27 seconds
Started Sep 27 12:50:03 PM PDT 23
Finished Sep 27 12:50:21 PM PDT 23
Peak memory 219088 kb
Host smart-3c2794f8-84d4-434e-842b-e23bf64b4370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052235790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2052235790
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3330438535
Short name T434
Test name
Test status
Simulation time 2242868542 ps
CPU time 51.19 seconds
Started Sep 27 12:40:15 PM PDT 23
Finished Sep 27 12:41:07 PM PDT 23
Peak memory 211864 kb
Host smart-22139d0e-34df-458a-bccb-b53cc0d48ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330438535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3330438535
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1356706060
Short name T84
Test name
Test status
Simulation time 3911565506 ps
CPU time 15.67 seconds
Started Sep 27 12:35:10 PM PDT 23
Finished Sep 27 12:35:26 PM PDT 23
Peak memory 210692 kb
Host smart-0d67af65-a75f-441c-b11c-aaea0abf9261
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356706060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1356706060
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3354132236
Short name T141
Test name
Test status
Simulation time 3585765275 ps
CPU time 14.9 seconds
Started Sep 27 12:49:55 PM PDT 23
Finished Sep 27 12:50:10 PM PDT 23
Peak memory 210840 kb
Host smart-5134d544-5e46-47f5-8acc-66337b3d6a43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354132236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3354132236
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3871095506
Short name T130
Test name
Test status
Simulation time 167588300 ps
CPU time 7.53 seconds
Started Sep 27 12:37:48 PM PDT 23
Finished Sep 27 12:37:56 PM PDT 23
Peak memory 210732 kb
Host smart-c673d32e-feee-4151-9a70-036ac0acfbd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871095506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3871095506
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.195570076
Short name T467
Test name
Test status
Simulation time 878415150 ps
CPU time 6.15 seconds
Started Sep 27 12:35:18 PM PDT 23
Finished Sep 27 12:35:25 PM PDT 23
Peak memory 218844 kb
Host smart-5b28ac07-c58e-40a5-bc04-f7e03b6ba9f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195570076 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.195570076
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.994543831
Short name T453
Test name
Test status
Simulation time 1977301364 ps
CPU time 7.15 seconds
Started Sep 27 12:50:28 PM PDT 23
Finished Sep 27 12:50:35 PM PDT 23
Peak memory 216136 kb
Host smart-342a73e2-db8c-4fc8-8c2a-47b709327d3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994543831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.994543831
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3196367449
Short name T430
Test name
Test status
Simulation time 2025597184 ps
CPU time 15.66 seconds
Started Sep 27 12:46:48 PM PDT 23
Finished Sep 27 12:47:04 PM PDT 23
Peak memory 210732 kb
Host smart-4256682b-a293-4e57-b9f5-0bdb9dcf4d6e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196367449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3196367449
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3131453393
Short name T31
Test name
Test status
Simulation time 8483156012 ps
CPU time 15.82 seconds
Started Sep 27 12:37:49 PM PDT 23
Finished Sep 27 12:38:05 PM PDT 23
Peak memory 210688 kb
Host smart-9edde007-c7a5-4219-89c7-fcf31b415642
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131453393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3131453393
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.141821020
Short name T446
Test name
Test status
Simulation time 5597628822 ps
CPU time 82.81 seconds
Started Sep 27 12:40:18 PM PDT 23
Finished Sep 27 12:41:41 PM PDT 23
Peak memory 218848 kb
Host smart-ab951e87-51c1-493f-9152-2353c411c59b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141821020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.141821020
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3210153310
Short name T439
Test name
Test status
Simulation time 171731727 ps
CPU time 7.34 seconds
Started Sep 27 12:36:23 PM PDT 23
Finished Sep 27 12:36:30 PM PDT 23
Peak memory 218852 kb
Host smart-08464cb7-5197-49a8-b98f-777e3240ce06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210153310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3210153310
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4130526561
Short name T454
Test name
Test status
Simulation time 2239332969 ps
CPU time 84.18 seconds
Started Sep 27 12:35:03 PM PDT 23
Finished Sep 27 12:36:27 PM PDT 23
Peak memory 211008 kb
Host smart-d3cab79f-82f1-4928-a50e-c39e6924ed8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130526561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4130526561
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2092221254
Short name T431
Test name
Test status
Simulation time 1900662366 ps
CPU time 8.79 seconds
Started Sep 27 12:38:40 PM PDT 23
Finished Sep 27 12:38:49 PM PDT 23
Peak memory 218940 kb
Host smart-8e31ed43-d3aa-4ec7-bec3-31acb2e6c2cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092221254 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2092221254
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3894013424
Short name T73
Test name
Test status
Simulation time 6542721583 ps
CPU time 13.79 seconds
Started Sep 27 12:35:47 PM PDT 23
Finished Sep 27 12:36:01 PM PDT 23
Peak memory 210692 kb
Host smart-b3602ec2-cb6a-44e0-9f9f-86d0ba4a8e90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894013424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3894013424
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.870604863
Short name T80
Test name
Test status
Simulation time 1074170253 ps
CPU time 52.69 seconds
Started Sep 27 12:35:48 PM PDT 23
Finished Sep 27 12:36:41 PM PDT 23
Peak memory 218808 kb
Host smart-d05aa344-ed28-46a3-bec4-441deb138ec1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870604863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.870604863
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2069420945
Short name T83
Test name
Test status
Simulation time 90147425 ps
CPU time 4.49 seconds
Started Sep 27 12:35:49 PM PDT 23
Finished Sep 27 12:35:54 PM PDT 23
Peak memory 210640 kb
Host smart-44ff7983-ad18-4f0e-9324-993c551e5aee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069420945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2069420945
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1373002922
Short name T149
Test name
Test status
Simulation time 1895842710 ps
CPU time 19.24 seconds
Started Sep 27 12:39:12 PM PDT 23
Finished Sep 27 12:39:31 PM PDT 23
Peak memory 218844 kb
Host smart-5ddca042-bdfb-4228-a291-b8ff382a42ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373002922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1373002922
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.959269182
Short name T115
Test name
Test status
Simulation time 1047321560 ps
CPU time 76.84 seconds
Started Sep 27 12:37:00 PM PDT 23
Finished Sep 27 12:38:17 PM PDT 23
Peak memory 218796 kb
Host smart-8345618e-6bb2-42a3-9727-c15c0b379e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959269182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.959269182
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3493253676
Short name T463
Test name
Test status
Simulation time 6451113165 ps
CPU time 10.69 seconds
Started Sep 27 12:38:42 PM PDT 23
Finished Sep 27 12:38:53 PM PDT 23
Peak memory 213104 kb
Host smart-2761d73d-89af-49e7-ac1e-455a2faa967f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493253676 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3493253676
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1532029871
Short name T100
Test name
Test status
Simulation time 379666398 ps
CPU time 4.37 seconds
Started Sep 27 12:36:42 PM PDT 23
Finished Sep 27 12:36:46 PM PDT 23
Peak memory 210640 kb
Host smart-7c150373-0f19-4a0a-9a83-919f5a32043c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532029871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1532029871
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2998505305
Short name T479
Test name
Test status
Simulation time 20981981913 ps
CPU time 211.07 seconds
Started Sep 27 12:35:53 PM PDT 23
Finished Sep 27 12:39:24 PM PDT 23
Peak memory 210780 kb
Host smart-dbb9c7a9-db45-46bf-b645-81299ac8370a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998505305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2998505305
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4114612212
Short name T65
Test name
Test status
Simulation time 690142707 ps
CPU time 6.52 seconds
Started Sep 27 12:38:09 PM PDT 23
Finished Sep 27 12:38:16 PM PDT 23
Peak memory 214140 kb
Host smart-3bb26f71-179b-4235-956e-87a8a96f9024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114612212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4114612212
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.68106822
Short name T117
Test name
Test status
Simulation time 3067294858 ps
CPU time 80.94 seconds
Started Sep 27 12:35:52 PM PDT 23
Finished Sep 27 12:37:13 PM PDT 23
Peak memory 210932 kb
Host smart-9d0f08af-37a0-4773-8f58-790ee86bf1bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68106822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_int
g_err.68106822
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.793777268
Short name T144
Test name
Test status
Simulation time 7177924883 ps
CPU time 14.92 seconds
Started Sep 27 12:37:20 PM PDT 23
Finished Sep 27 12:37:35 PM PDT 23
Peak memory 211624 kb
Host smart-9b4c15d8-5032-40aa-9256-6fc871859230
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793777268 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.793777268
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3206503997
Short name T106
Test name
Test status
Simulation time 276086596 ps
CPU time 5.43 seconds
Started Sep 27 12:40:44 PM PDT 23
Finished Sep 27 12:40:50 PM PDT 23
Peak memory 216008 kb
Host smart-bf856bed-3112-4cb6-8966-ec098c6f6f7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206503997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3206503997
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.963096081
Short name T82
Test name
Test status
Simulation time 37398088855 ps
CPU time 130.26 seconds
Started Sep 27 12:39:54 PM PDT 23
Finished Sep 27 12:42:05 PM PDT 23
Peak memory 218792 kb
Host smart-785b61c1-0c33-48a1-a799-f42705614b82
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963096081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.963096081
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3975671043
Short name T74
Test name
Test status
Simulation time 3096024840 ps
CPU time 13.84 seconds
Started Sep 27 12:40:42 PM PDT 23
Finished Sep 27 12:40:56 PM PDT 23
Peak memory 210692 kb
Host smart-1d9106ec-d5bf-43c0-a656-8c10ca0e8ebb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975671043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3975671043
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4124671730
Short name T432
Test name
Test status
Simulation time 931052299 ps
CPU time 13.33 seconds
Started Sep 27 12:37:24 PM PDT 23
Finished Sep 27 12:37:38 PM PDT 23
Peak memory 218816 kb
Host smart-497d9da4-f74a-4253-be57-531f84778de8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124671730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4124671730
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1646840520
Short name T438
Test name
Test status
Simulation time 3931634803 ps
CPU time 48.52 seconds
Started Sep 27 12:35:59 PM PDT 23
Finished Sep 27 12:36:48 PM PDT 23
Peak memory 218960 kb
Host smart-3e74cd75-9c96-44e4-be0a-cbd907e89f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646840520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1646840520
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.153843745
Short name T152
Test name
Test status
Simulation time 1177688842 ps
CPU time 11.83 seconds
Started Sep 27 12:37:12 PM PDT 23
Finished Sep 27 12:37:24 PM PDT 23
Peak memory 213052 kb
Host smart-e0f2db8a-80a0-43dc-bfb9-6d1463fea6e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153843745 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.153843745
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1396852504
Short name T150
Test name
Test status
Simulation time 1167111359 ps
CPU time 10.92 seconds
Started Sep 27 12:35:57 PM PDT 23
Finished Sep 27 12:36:08 PM PDT 23
Peak memory 210636 kb
Host smart-f6d4c9cf-741c-452d-b644-0dba8fd3ab6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396852504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1396852504
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3714975144
Short name T460
Test name
Test status
Simulation time 9726795785 ps
CPU time 66.87 seconds
Started Sep 27 12:40:21 PM PDT 23
Finished Sep 27 12:41:28 PM PDT 23
Peak memory 210776 kb
Host smart-a9cee306-d2ba-4581-a6a2-2490cd6b5423
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714975144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3714975144
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2089159650
Short name T99
Test name
Test status
Simulation time 919575954 ps
CPU time 4.46 seconds
Started Sep 27 12:37:10 PM PDT 23
Finished Sep 27 12:37:14 PM PDT 23
Peak memory 216276 kb
Host smart-3cde6453-9b41-4c7f-bc8f-2e19e00b83c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089159650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2089159650
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3445619923
Short name T456
Test name
Test status
Simulation time 2277246411 ps
CPU time 44.57 seconds
Started Sep 27 12:35:58 PM PDT 23
Finished Sep 27 12:36:43 PM PDT 23
Peak memory 212020 kb
Host smart-16905c6e-9e99-4ac4-a77d-c28ceb8f3b66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445619923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3445619923
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4011254364
Short name T126
Test name
Test status
Simulation time 1478377740 ps
CPU time 13.07 seconds
Started Sep 27 12:41:53 PM PDT 23
Finished Sep 27 12:42:06 PM PDT 23
Peak memory 218856 kb
Host smart-eea429bd-fed6-42d6-9871-355ff5399465
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011254364 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4011254364
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.795691937
Short name T437
Test name
Test status
Simulation time 2143183662 ps
CPU time 7.52 seconds
Started Sep 27 12:36:00 PM PDT 23
Finished Sep 27 12:36:08 PM PDT 23
Peak memory 210624 kb
Host smart-48fb97a8-b18d-41a1-9afe-a5680d3d057d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795691937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.795691937
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3336010849
Short name T474
Test name
Test status
Simulation time 31490134687 ps
CPU time 284.05 seconds
Started Sep 27 12:35:58 PM PDT 23
Finished Sep 27 12:40:42 PM PDT 23
Peak memory 210672 kb
Host smart-d879f414-25e0-4ba0-86bd-6415e21349ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336010849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3336010849
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4033407261
Short name T98
Test name
Test status
Simulation time 2041104661 ps
CPU time 17.86 seconds
Started Sep 27 12:36:00 PM PDT 23
Finished Sep 27 12:36:18 PM PDT 23
Peak memory 210608 kb
Host smart-8a431802-5088-4feb-a06b-cd5634ac8ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033407261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4033407261
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2833575129
Short name T440
Test name
Test status
Simulation time 4079846020 ps
CPU time 12.72 seconds
Started Sep 27 12:37:08 PM PDT 23
Finished Sep 27 12:37:21 PM PDT 23
Peak memory 218900 kb
Host smart-dceccff0-5786-4da8-b65f-b6c2312438c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833575129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2833575129
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1296311871
Short name T68
Test name
Test status
Simulation time 704422162 ps
CPU time 40.39 seconds
Started Sep 27 12:38:07 PM PDT 23
Finished Sep 27 12:38:47 PM PDT 23
Peak memory 218792 kb
Host smart-7bf7c5a2-80f2-44a9-9978-34d89865e88f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296311871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1296311871
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1495648010
Short name T125
Test name
Test status
Simulation time 7654547379 ps
CPU time 11.77 seconds
Started Sep 27 12:48:32 PM PDT 23
Finished Sep 27 12:48:44 PM PDT 23
Peak memory 214944 kb
Host smart-002a2c2f-b2cd-414a-b0c5-a6c58614fada
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495648010 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1495648010
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2276495203
Short name T145
Test name
Test status
Simulation time 1848297768 ps
CPU time 14.63 seconds
Started Sep 27 12:39:44 PM PDT 23
Finished Sep 27 12:39:59 PM PDT 23
Peak memory 216848 kb
Host smart-e2a567dd-9a84-47b4-b7b6-2d33777e1bc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276495203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2276495203
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1881612527
Short name T465
Test name
Test status
Simulation time 11998481066 ps
CPU time 16.05 seconds
Started Sep 27 12:44:59 PM PDT 23
Finished Sep 27 12:45:16 PM PDT 23
Peak memory 217564 kb
Host smart-79a5fed0-5d34-4219-878d-e72a0194b468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881612527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1881612527
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3541080005
Short name T118
Test name
Test status
Simulation time 6799929544 ps
CPU time 82.12 seconds
Started Sep 27 12:36:05 PM PDT 23
Finished Sep 27 12:37:27 PM PDT 23
Peak memory 211252 kb
Host smart-5e1829a6-f91d-4759-8e57-f83edf16b20f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541080005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3541080005
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3635609416
Short name T471
Test name
Test status
Simulation time 177622409 ps
CPU time 4.6 seconds
Started Sep 27 12:43:18 PM PDT 23
Finished Sep 27 12:43:23 PM PDT 23
Peak memory 211104 kb
Host smart-4e4d9ebf-6132-4f49-9e0b-43ca06adbf10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635609416 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3635609416
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1749065511
Short name T91
Test name
Test status
Simulation time 11259125115 ps
CPU time 10.05 seconds
Started Sep 27 12:39:28 PM PDT 23
Finished Sep 27 12:39:38 PM PDT 23
Peak memory 210944 kb
Host smart-b686142b-003b-4035-9475-3a6c04199397
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749065511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1749065511
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.369168660
Short name T442
Test name
Test status
Simulation time 2234838977 ps
CPU time 19.15 seconds
Started Sep 27 12:38:13 PM PDT 23
Finished Sep 27 12:38:32 PM PDT 23
Peak memory 218592 kb
Host smart-06b6dbae-3c6e-492f-a517-b9b3fbed2222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369168660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.369168660
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1859168722
Short name T469
Test name
Test status
Simulation time 11802766226 ps
CPU time 14.73 seconds
Started Sep 27 12:36:55 PM PDT 23
Finished Sep 27 12:37:10 PM PDT 23
Peak memory 218892 kb
Host smart-49ad65a9-fe36-4afb-a5ab-e863b25e60bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859168722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1859168722
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.217558224
Short name T468
Test name
Test status
Simulation time 3294128760 ps
CPU time 48.14 seconds
Started Sep 27 12:36:15 PM PDT 23
Finished Sep 27 12:37:04 PM PDT 23
Peak memory 211928 kb
Host smart-260b5161-840f-4152-90ed-2b2b2eeafba6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217558224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.217558224
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2165792945
Short name T45
Test name
Test status
Simulation time 1537899987 ps
CPU time 13.19 seconds
Started Sep 27 12:36:50 PM PDT 23
Finished Sep 27 12:37:04 PM PDT 23
Peak memory 218944 kb
Host smart-d4239f97-084b-4277-8607-609bad11fb56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165792945 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2165792945
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.465196212
Short name T96
Test name
Test status
Simulation time 89172573 ps
CPU time 4.26 seconds
Started Sep 27 12:44:05 PM PDT 23
Finished Sep 27 12:44:09 PM PDT 23
Peak memory 210624 kb
Host smart-a51a43f4-baa0-4fd5-8128-499b1a09147e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465196212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.465196212
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1229985668
Short name T450
Test name
Test status
Simulation time 841538520 ps
CPU time 9.25 seconds
Started Sep 27 12:36:15 PM PDT 23
Finished Sep 27 12:36:24 PM PDT 23
Peak memory 210632 kb
Host smart-82051037-952e-4625-855b-8e6b577d1781
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229985668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1229985668
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.260979563
Short name T147
Test name
Test status
Simulation time 34826342758 ps
CPU time 17.6 seconds
Started Sep 27 12:55:06 PM PDT 23
Finished Sep 27 12:55:24 PM PDT 23
Peak memory 218960 kb
Host smart-af7179d7-80ff-4325-ae03-be0cb1aeecff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260979563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.260979563
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2171026007
Short name T447
Test name
Test status
Simulation time 822868553 ps
CPU time 39.06 seconds
Started Sep 27 12:37:02 PM PDT 23
Finished Sep 27 12:37:41 PM PDT 23
Peak memory 218924 kb
Host smart-92f7394a-5b92-441f-bcac-ab40ba07078f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171026007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2171026007
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4097008047
Short name T472
Test name
Test status
Simulation time 8914905339 ps
CPU time 17.72 seconds
Started Sep 27 12:45:27 PM PDT 23
Finished Sep 27 12:45:45 PM PDT 23
Peak memory 218956 kb
Host smart-e8644f5c-bb26-42bc-8c60-887352989bb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097008047 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4097008047
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3054356069
Short name T78
Test name
Test status
Simulation time 34284048551 ps
CPU time 152.47 seconds
Started Sep 27 12:38:30 PM PDT 23
Finished Sep 27 12:41:03 PM PDT 23
Peak memory 210680 kb
Host smart-6624463b-40c4-469f-aefc-8f7de4bd005c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054356069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3054356069
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2173985753
Short name T140
Test name
Test status
Simulation time 1779703031 ps
CPU time 14.72 seconds
Started Sep 27 12:41:44 PM PDT 23
Finished Sep 27 12:41:59 PM PDT 23
Peak memory 217452 kb
Host smart-c17bda0b-6f30-4273-a55c-5a3fa2bfe85c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173985753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2173985753
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3200787368
Short name T114
Test name
Test status
Simulation time 6845869181 ps
CPU time 44.89 seconds
Started Sep 27 12:39:04 PM PDT 23
Finished Sep 27 12:39:49 PM PDT 23
Peak memory 211112 kb
Host smart-d7f0981f-d2cd-4f09-b7b0-5e655fa2b5c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200787368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3200787368
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.762738727
Short name T470
Test name
Test status
Simulation time 563420475 ps
CPU time 4.45 seconds
Started Sep 27 12:36:23 PM PDT 23
Finished Sep 27 12:36:27 PM PDT 23
Peak memory 210688 kb
Host smart-93a6d246-24d7-443a-aad1-37fda95de105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762738727 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.762738727
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2714652393
Short name T95
Test name
Test status
Simulation time 6966985550 ps
CPU time 13.67 seconds
Started Sep 27 12:38:46 PM PDT 23
Finished Sep 27 12:39:01 PM PDT 23
Peak memory 210696 kb
Host smart-e1fd1f9e-88d5-4c10-b543-2232df81a891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714652393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2714652393
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3914672991
Short name T44
Test name
Test status
Simulation time 10869295985 ps
CPU time 161.52 seconds
Started Sep 27 12:36:21 PM PDT 23
Finished Sep 27 12:39:03 PM PDT 23
Peak memory 210692 kb
Host smart-3e73e7c2-3e4e-4487-b5ac-dbff403ee050
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914672991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3914672991
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.639494468
Short name T462
Test name
Test status
Simulation time 439206244 ps
CPU time 4.27 seconds
Started Sep 27 12:37:26 PM PDT 23
Finished Sep 27 12:37:31 PM PDT 23
Peak memory 210632 kb
Host smart-d4c14aba-f9a6-43f7-b9e3-81dfec44fd03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639494468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.639494468
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1463721694
Short name T475
Test name
Test status
Simulation time 10220406791 ps
CPU time 12.91 seconds
Started Sep 27 12:38:20 PM PDT 23
Finished Sep 27 12:38:33 PM PDT 23
Peak memory 218896 kb
Host smart-e1ce4ab3-a360-4c6a-af0f-441878dd98e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463721694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1463721694
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4260943307
Short name T466
Test name
Test status
Simulation time 8814558097 ps
CPU time 16.87 seconds
Started Sep 27 12:35:17 PM PDT 23
Finished Sep 27 12:35:35 PM PDT 23
Peak memory 210700 kb
Host smart-6d3708f2-7f1c-4758-9873-63d8375e3c14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260943307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4260943307
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2469668135
Short name T441
Test name
Test status
Simulation time 2214707942 ps
CPU time 17.7 seconds
Started Sep 27 12:42:51 PM PDT 23
Finished Sep 27 12:43:09 PM PDT 23
Peak memory 216508 kb
Host smart-a6ba3cf6-7647-4269-8577-bce4cc484836
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469668135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2469668135
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1344654898
Short name T131
Test name
Test status
Simulation time 772468548 ps
CPU time 10.56 seconds
Started Sep 27 12:37:04 PM PDT 23
Finished Sep 27 12:37:15 PM PDT 23
Peak memory 210652 kb
Host smart-786472c9-442c-4636-a7e3-4a7fd57b3d47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344654898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1344654898
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2562755709
Short name T433
Test name
Test status
Simulation time 1825450058 ps
CPU time 14.08 seconds
Started Sep 27 12:35:18 PM PDT 23
Finished Sep 27 12:35:33 PM PDT 23
Peak memory 213452 kb
Host smart-4adc97e5-2c4d-461e-bd2d-35056db3c7c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562755709 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2562755709
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3160812808
Short name T151
Test name
Test status
Simulation time 8770893786 ps
CPU time 11.2 seconds
Started Sep 27 12:35:12 PM PDT 23
Finished Sep 27 12:35:25 PM PDT 23
Peak memory 210676 kb
Host smart-3af9762f-8400-48af-a310-9c6855336573
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160812808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3160812808
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2662513757
Short name T104
Test name
Test status
Simulation time 1913404468 ps
CPU time 15.44 seconds
Started Sep 27 12:40:58 PM PDT 23
Finished Sep 27 12:41:14 PM PDT 23
Peak memory 210612 kb
Host smart-276e6456-2809-440c-a9a3-6a038c882afa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662513757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2662513757
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1749086892
Short name T127
Test name
Test status
Simulation time 9958262723 ps
CPU time 16.5 seconds
Started Sep 27 12:37:37 PM PDT 23
Finished Sep 27 12:37:54 PM PDT 23
Peak memory 210704 kb
Host smart-22c5612a-49ce-4c18-b364-3258a695065d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749086892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1749086892
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2594951642
Short name T79
Test name
Test status
Simulation time 6090028444 ps
CPU time 52.36 seconds
Started Sep 27 12:36:52 PM PDT 23
Finished Sep 27 12:37:44 PM PDT 23
Peak memory 210700 kb
Host smart-d6ca7a21-672b-44fc-b495-9b2b0025054b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594951642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2594951642
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3150040535
Short name T97
Test name
Test status
Simulation time 226260962 ps
CPU time 7.56 seconds
Started Sep 27 12:42:55 PM PDT 23
Finished Sep 27 12:43:03 PM PDT 23
Peak memory 210636 kb
Host smart-51e9f225-18d1-4148-be0b-2b5e1714c8de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150040535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3150040535
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3850795460
Short name T30
Test name
Test status
Simulation time 313456069 ps
CPU time 5.59 seconds
Started Sep 27 12:37:34 PM PDT 23
Finished Sep 27 12:37:40 PM PDT 23
Peak memory 210644 kb
Host smart-f55b314a-7e68-4a70-8c9b-f459be38bd7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850795460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3850795460
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4095791040
Short name T459
Test name
Test status
Simulation time 569397556 ps
CPU time 5.16 seconds
Started Sep 27 12:39:01 PM PDT 23
Finished Sep 27 12:39:06 PM PDT 23
Peak memory 210644 kb
Host smart-7825d3e3-c2d5-4841-a0af-397eadd6529c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095791040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4095791040
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2134623475
Short name T477
Test name
Test status
Simulation time 2391460405 ps
CPU time 9.93 seconds
Started Sep 27 12:42:51 PM PDT 23
Finished Sep 27 12:43:01 PM PDT 23
Peak memory 210696 kb
Host smart-795cb41c-dc8b-4c4d-9521-91e2876e6f0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134623475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2134623475
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.645036089
Short name T137
Test name
Test status
Simulation time 1007478256 ps
CPU time 10.44 seconds
Started Sep 27 12:35:39 PM PDT 23
Finished Sep 27 12:35:50 PM PDT 23
Peak memory 213820 kb
Host smart-a5c038bc-5be8-4cd7-848c-035526cf11f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645036089 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.645036089
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1997987826
Short name T90
Test name
Test status
Simulation time 6064220834 ps
CPU time 11.52 seconds
Started Sep 27 12:35:24 PM PDT 23
Finished Sep 27 12:35:36 PM PDT 23
Peak memory 217724 kb
Host smart-2440f33c-042d-4845-91e9-16c22eaf8230
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997987826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1997987826
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2806894777
Short name T473
Test name
Test status
Simulation time 9356899815 ps
CPU time 11 seconds
Started Sep 27 12:39:05 PM PDT 23
Finished Sep 27 12:39:16 PM PDT 23
Peak memory 210672 kb
Host smart-ff82a461-ef3c-4e8a-ac11-b7f235e82612
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806894777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2806894777
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4109227854
Short name T461
Test name
Test status
Simulation time 168122620 ps
CPU time 4.25 seconds
Started Sep 27 12:45:27 PM PDT 23
Finished Sep 27 12:45:31 PM PDT 23
Peak memory 210748 kb
Host smart-96530f3a-fc72-4ae5-9da7-76aca1ee7180
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109227854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4109227854
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2075661698
Short name T480
Test name
Test status
Simulation time 120914721137 ps
CPU time 277.28 seconds
Started Sep 27 12:36:21 PM PDT 23
Finished Sep 27 12:40:59 PM PDT 23
Peak memory 210572 kb
Host smart-c36ac534-e303-49a7-b93e-c4ee564f0ead
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075661698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2075661698
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.961984899
Short name T429
Test name
Test status
Simulation time 3853310387 ps
CPU time 15.86 seconds
Started Sep 27 12:37:14 PM PDT 23
Finished Sep 27 12:37:30 PM PDT 23
Peak memory 210688 kb
Host smart-1ce684c3-f978-4b4d-913b-a493714022dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961984899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.961984899
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2338005122
Short name T142
Test name
Test status
Simulation time 2070321788 ps
CPU time 19.8 seconds
Started Sep 27 12:36:21 PM PDT 23
Finished Sep 27 12:36:41 PM PDT 23
Peak memory 218632 kb
Host smart-44d5f906-c4e4-4b4c-9b64-c063b0a4728c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338005122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2338005122
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3480356474
Short name T113
Test name
Test status
Simulation time 154392788 ps
CPU time 39.3 seconds
Started Sep 27 12:41:34 PM PDT 23
Finished Sep 27 12:42:13 PM PDT 23
Peak memory 218904 kb
Host smart-f87d50cc-eb63-46e2-b0ef-f9d8a3f5f9d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480356474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3480356474
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.528621328
Short name T436
Test name
Test status
Simulation time 85534322 ps
CPU time 4.29 seconds
Started Sep 27 12:39:08 PM PDT 23
Finished Sep 27 12:39:12 PM PDT 23
Peak memory 210424 kb
Host smart-1fba613d-019d-4c70-aca7-55baa84f6c0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528621328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.528621328
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3643458517
Short name T105
Test name
Test status
Simulation time 1800054717 ps
CPU time 14.58 seconds
Started Sep 27 12:40:02 PM PDT 23
Finished Sep 27 12:40:18 PM PDT 23
Peak memory 210728 kb
Host smart-fd0fa371-53c2-4ec5-8cbc-3c85570534d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643458517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3643458517
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1547785496
Short name T457
Test name
Test status
Simulation time 1179142476 ps
CPU time 12.93 seconds
Started Sep 27 12:40:05 PM PDT 23
Finished Sep 27 12:40:18 PM PDT 23
Peak memory 210732 kb
Host smart-b61ad28b-8b4e-4eea-b3a4-47d6f90bc9ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547785496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1547785496
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3064946232
Short name T449
Test name
Test status
Simulation time 7028908922 ps
CPU time 14.73 seconds
Started Sep 27 12:44:58 PM PDT 23
Finished Sep 27 12:45:13 PM PDT 23
Peak memory 219048 kb
Host smart-3b6da523-8daa-4487-ad36-f51dddf996c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064946232 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3064946232
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.849650152
Short name T128
Test name
Test status
Simulation time 1851393806 ps
CPU time 15.1 seconds
Started Sep 27 12:35:26 PM PDT 23
Finished Sep 27 12:35:41 PM PDT 23
Peak memory 210712 kb
Host smart-2175f423-2ac9-4dcc-86ef-f795ceac6278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849650152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.849650152
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1918414130
Short name T135
Test name
Test status
Simulation time 352560174 ps
CPU time 6.54 seconds
Started Sep 27 12:35:24 PM PDT 23
Finished Sep 27 12:35:31 PM PDT 23
Peak memory 210628 kb
Host smart-ec5e2863-a300-4ec0-99a1-f5f9e4cb64a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918414130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1918414130
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.444926505
Short name T143
Test name
Test status
Simulation time 1881722541 ps
CPU time 9.51 seconds
Started Sep 27 12:38:07 PM PDT 23
Finished Sep 27 12:38:17 PM PDT 23
Peak memory 210744 kb
Host smart-7d148103-1283-40f3-9943-c25c0d12fec2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444926505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
444926505
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.535332996
Short name T92
Test name
Test status
Simulation time 24344372177 ps
CPU time 139.81 seconds
Started Sep 27 12:43:28 PM PDT 23
Finished Sep 27 12:45:48 PM PDT 23
Peak memory 210304 kb
Host smart-70a50193-cc8b-4360-bbf0-fe2b2fba8dc3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535332996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.535332996
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.364226743
Short name T458
Test name
Test status
Simulation time 2923875374 ps
CPU time 16.82 seconds
Started Sep 27 12:51:32 PM PDT 23
Finished Sep 27 12:51:49 PM PDT 23
Peak memory 210820 kb
Host smart-bfef8bf7-21a1-4621-9623-10d287e74757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364226743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.364226743
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3118308759
Short name T27
Test name
Test status
Simulation time 2895095086 ps
CPU time 17.5 seconds
Started Sep 27 12:41:01 PM PDT 23
Finished Sep 27 12:41:18 PM PDT 23
Peak memory 218900 kb
Host smart-788a7e33-05aa-4620-b42f-80aea7c64f8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118308759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3118308759
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2983810009
Short name T46
Test name
Test status
Simulation time 5068820475 ps
CPU time 87.83 seconds
Started Sep 27 12:35:24 PM PDT 23
Finished Sep 27 12:36:52 PM PDT 23
Peak memory 211036 kb
Host smart-6b8c8729-35e2-4e56-8631-eb441b68cc9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983810009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2983810009
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3894999340
Short name T139
Test name
Test status
Simulation time 1701186365 ps
CPU time 14.51 seconds
Started Sep 27 12:41:48 PM PDT 23
Finished Sep 27 12:42:02 PM PDT 23
Peak memory 218980 kb
Host smart-ea6de5d7-713d-4a82-ab7c-a963dcd2ba19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894999340 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3894999340
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2647757932
Short name T72
Test name
Test status
Simulation time 3104882492 ps
CPU time 11.26 seconds
Started Sep 27 12:38:43 PM PDT 23
Finished Sep 27 12:38:54 PM PDT 23
Peak memory 217408 kb
Host smart-eee64eb4-ff7c-40a4-9c5f-b8224b5b48ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647757932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2647757932
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2300196788
Short name T76
Test name
Test status
Simulation time 198200128004 ps
CPU time 323.38 seconds
Started Sep 27 12:43:35 PM PDT 23
Finished Sep 27 12:48:58 PM PDT 23
Peak memory 218640 kb
Host smart-98116fbd-136c-40bf-8822-0466825d8b6a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300196788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2300196788
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3502542696
Short name T444
Test name
Test status
Simulation time 89299735 ps
CPU time 4.27 seconds
Started Sep 27 12:57:52 PM PDT 23
Finished Sep 27 12:57:57 PM PDT 23
Peak memory 216488 kb
Host smart-7ed232b7-3a9c-42e9-9037-586274b94de7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502542696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3502542696
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2982024550
Short name T64
Test name
Test status
Simulation time 642679728 ps
CPU time 12.18 seconds
Started Sep 27 12:42:29 PM PDT 23
Finished Sep 27 12:42:42 PM PDT 23
Peak memory 218900 kb
Host smart-8f6c3f87-d9ff-4915-a3d5-3c83f8bea140
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982024550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2982024550
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3830662546
Short name T28
Test name
Test status
Simulation time 97346375 ps
CPU time 5.04 seconds
Started Sep 27 12:41:34 PM PDT 23
Finished Sep 27 12:41:39 PM PDT 23
Peak memory 213872 kb
Host smart-921c3888-6ab8-44aa-be52-68bee2365029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830662546 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3830662546
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.385485971
Short name T26
Test name
Test status
Simulation time 6985478392 ps
CPU time 14.6 seconds
Started Sep 27 12:41:56 PM PDT 23
Finished Sep 27 12:42:11 PM PDT 23
Peak memory 217356 kb
Host smart-28767e5a-754b-4e9d-bc93-18100afcc9b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385485971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.385485971
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2378486567
Short name T81
Test name
Test status
Simulation time 1939551262 ps
CPU time 103.38 seconds
Started Sep 27 12:44:52 PM PDT 23
Finished Sep 27 12:46:36 PM PDT 23
Peak memory 218432 kb
Host smart-a076c746-0e10-42e7-a32a-f1f517ca257d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378486567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2378486567
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.841990692
Short name T428
Test name
Test status
Simulation time 475059833 ps
CPU time 7.24 seconds
Started Sep 27 12:38:07 PM PDT 23
Finished Sep 27 12:38:14 PM PDT 23
Peak memory 210604 kb
Host smart-e67dc90f-d15d-467f-ab22-c212f3890772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841990692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.841990692
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1637475068
Short name T24
Test name
Test status
Simulation time 832170464 ps
CPU time 8.72 seconds
Started Sep 27 12:37:34 PM PDT 23
Finished Sep 27 12:37:43 PM PDT 23
Peak memory 218884 kb
Host smart-8ef13bc7-8927-49a7-8e52-81d54a45a6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637475068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1637475068
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3730697219
Short name T120
Test name
Test status
Simulation time 1383851925 ps
CPU time 81.2 seconds
Started Sep 27 12:37:52 PM PDT 23
Finished Sep 27 12:39:14 PM PDT 23
Peak memory 210764 kb
Host smart-b3d0d117-6014-438a-8f3e-36ddf25d795b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730697219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3730697219
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3326597838
Short name T476
Test name
Test status
Simulation time 4485992933 ps
CPU time 11.11 seconds
Started Sep 27 12:37:27 PM PDT 23
Finished Sep 27 12:37:38 PM PDT 23
Peak memory 218940 kb
Host smart-1ea15999-09a1-4196-9d73-eff21ecb3469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326597838 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3326597838
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3512622612
Short name T148
Test name
Test status
Simulation time 377837598 ps
CPU time 4.2 seconds
Started Sep 27 12:37:50 PM PDT 23
Finished Sep 27 12:37:55 PM PDT 23
Peak memory 209372 kb
Host smart-ad67b099-912d-4824-9490-1958bc5126bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512622612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3512622612
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2862001200
Short name T29
Test name
Test status
Simulation time 28251929460 ps
CPU time 101.86 seconds
Started Sep 27 12:38:53 PM PDT 23
Finished Sep 27 12:40:36 PM PDT 23
Peak memory 218092 kb
Host smart-7c4d3f86-b8e7-4d55-b183-bc1fed54dfdc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862001200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2862001200
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1383892637
Short name T435
Test name
Test status
Simulation time 1933707851 ps
CPU time 14.65 seconds
Started Sep 27 12:38:07 PM PDT 23
Finished Sep 27 12:38:22 PM PDT 23
Peak memory 210608 kb
Host smart-ccb1fff9-748a-46f8-b3f5-4f276466bc4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383892637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1383892637
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1953962769
Short name T153
Test name
Test status
Simulation time 7600372270 ps
CPU time 18.46 seconds
Started Sep 27 12:37:35 PM PDT 23
Finished Sep 27 12:37:54 PM PDT 23
Peak memory 218924 kb
Host smart-251c910f-a7bc-4ea2-997b-6da3afd4d1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953962769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1953962769
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.696029696
Short name T116
Test name
Test status
Simulation time 8684298261 ps
CPU time 51.03 seconds
Started Sep 27 12:37:50 PM PDT 23
Finished Sep 27 12:38:42 PM PDT 23
Peak memory 210704 kb
Host smart-56fb3094-504e-4bf1-959a-d77af0070c60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696029696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.696029696
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3545925598
Short name T70
Test name
Test status
Simulation time 394588629 ps
CPU time 7.18 seconds
Started Sep 27 12:52:29 PM PDT 23
Finished Sep 27 12:52:37 PM PDT 23
Peak memory 214108 kb
Host smart-b7bc8cc5-7c87-4b35-bed3-9ca114dc80b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545925598 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3545925598
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2884865694
Short name T133
Test name
Test status
Simulation time 1563669828 ps
CPU time 13.12 seconds
Started Sep 27 12:39:28 PM PDT 23
Finished Sep 27 12:39:41 PM PDT 23
Peak memory 216868 kb
Host smart-5aa5485f-87ac-41aa-9391-b007c4c46565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884865694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2884865694
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3005433936
Short name T77
Test name
Test status
Simulation time 24174597349 ps
CPU time 233.99 seconds
Started Sep 27 12:39:15 PM PDT 23
Finished Sep 27 12:43:09 PM PDT 23
Peak memory 210688 kb
Host smart-b3515992-8842-47a1-94e4-e91fceef25dd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005433936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3005433936
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.105254003
Short name T448
Test name
Test status
Simulation time 4761462126 ps
CPU time 11.65 seconds
Started Sep 27 12:39:27 PM PDT 23
Finished Sep 27 12:39:39 PM PDT 23
Peak memory 217556 kb
Host smart-8cbccf9c-9703-47cd-8325-1079563e2020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105254003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.105254003
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2942267998
Short name T129
Test name
Test status
Simulation time 3652395908 ps
CPU time 18.73 seconds
Started Sep 27 12:40:20 PM PDT 23
Finished Sep 27 12:40:39 PM PDT 23
Peak memory 218960 kb
Host smart-2f5e98bc-dc83-489a-8684-37f64dfa3bcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942267998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2942267998
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2012410385
Short name T123
Test name
Test status
Simulation time 292305447 ps
CPU time 74.68 seconds
Started Sep 27 12:37:05 PM PDT 23
Finished Sep 27 12:38:20 PM PDT 23
Peak memory 211100 kb
Host smart-8690fa25-26af-47b3-84a5-a9ea325d01e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012410385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2012410385
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2860977972
Short name T66
Test name
Test status
Simulation time 3697145754 ps
CPU time 16.24 seconds
Started Sep 27 12:41:59 PM PDT 23
Finished Sep 27 12:42:16 PM PDT 23
Peak memory 218916 kb
Host smart-59419c68-43cc-4dd3-b78e-a80b653d4bf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860977972 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2860977972
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2142790188
Short name T134
Test name
Test status
Simulation time 1434744735 ps
CPU time 6.39 seconds
Started Sep 27 12:44:10 PM PDT 23
Finished Sep 27 12:44:16 PM PDT 23
Peak memory 216320 kb
Host smart-df0ad3e6-d653-44ce-8c89-c5e6ff6aac99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142790188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2142790188
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2027823795
Short name T452
Test name
Test status
Simulation time 3890066025 ps
CPU time 54.3 seconds
Started Sep 27 12:42:40 PM PDT 23
Finished Sep 27 12:43:35 PM PDT 23
Peak memory 210728 kb
Host smart-6a4ea32a-161f-4030-826c-7572f3410de6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027823795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2027823795
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3255293850
Short name T443
Test name
Test status
Simulation time 595313998 ps
CPU time 7.97 seconds
Started Sep 27 12:54:06 PM PDT 23
Finished Sep 27 12:54:14 PM PDT 23
Peak memory 210516 kb
Host smart-98f5ace4-0773-4fd0-8589-5ae26282e74d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255293850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3255293850
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2058754521
Short name T71
Test name
Test status
Simulation time 7620655360 ps
CPU time 14.65 seconds
Started Sep 27 12:45:11 PM PDT 23
Finished Sep 27 12:45:26 PM PDT 23
Peak memory 218984 kb
Host smart-54990493-ba6f-4136-acc3-e697af38efd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058754521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2058754521
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2771428735
Short name T253
Test name
Test status
Simulation time 14049029208 ps
CPU time 9.33 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:11:57 PM PDT 23
Peak memory 211204 kb
Host smart-c4010a8b-526a-4016-8cfc-54544b7ab02f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771428735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2771428735
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1694598900
Short name T390
Test name
Test status
Simulation time 619257006533 ps
CPU time 347.96 seconds
Started Sep 27 01:22:29 PM PDT 23
Finished Sep 27 01:28:17 PM PDT 23
Peak memory 213368 kb
Host smart-fe6cabb2-2383-4008-8d57-1a5e289cdd96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694598900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1694598900
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1144287005
Short name T369
Test name
Test status
Simulation time 532910497 ps
CPU time 5.57 seconds
Started Sep 27 01:17:04 PM PDT 23
Finished Sep 27 01:17:10 PM PDT 23
Peak memory 210968 kb
Host smart-b84d8a35-2202-4310-8577-e3b454a39af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144287005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1144287005
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3387513448
Short name T212
Test name
Test status
Simulation time 16476592198 ps
CPU time 32.37 seconds
Started Sep 27 01:14:50 PM PDT 23
Finished Sep 27 01:15:22 PM PDT 23
Peak memory 213472 kb
Host smart-36be1b23-f866-429a-ae20-59594c6b1033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387513448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3387513448
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2998157193
Short name T337
Test name
Test status
Simulation time 3932288350 ps
CPU time 34.58 seconds
Started Sep 27 01:20:48 PM PDT 23
Finished Sep 27 01:21:23 PM PDT 23
Peak memory 213516 kb
Host smart-fbff7fc8-94bf-4b31-82ff-5836c597773e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998157193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2998157193
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.905915529
Short name T241
Test name
Test status
Simulation time 1672004850 ps
CPU time 7.28 seconds
Started Sep 27 01:11:38 PM PDT 23
Finished Sep 27 01:11:47 PM PDT 23
Peak memory 211048 kb
Host smart-2b77cc8f-9b07-45bd-908f-24664035b751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905915529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.905915529
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1891991769
Short name T422
Test name
Test status
Simulation time 49926314007 ps
CPU time 169.31 seconds
Started Sep 27 01:11:05 PM PDT 23
Finished Sep 27 01:13:54 PM PDT 23
Peak memory 228468 kb
Host smart-97e618fe-230e-4eee-b7cc-12b023c4f24a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891991769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1891991769
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3472178292
Short name T413
Test name
Test status
Simulation time 4683506408 ps
CPU time 11.7 seconds
Started Sep 27 01:11:03 PM PDT 23
Finished Sep 27 01:11:15 PM PDT 23
Peak memory 211172 kb
Host smart-8b35cd93-aafc-4f87-b284-35d15bf628aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472178292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3472178292
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3469124603
Short name T42
Test name
Test status
Simulation time 12221980567 ps
CPU time 63.57 seconds
Started Sep 27 01:11:41 PM PDT 23
Finished Sep 27 01:12:45 PM PDT 23
Peak memory 234136 kb
Host smart-dbc49c10-0be7-4cf2-98ce-524c5812a7ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469124603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3469124603
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3407730745
Short name T88
Test name
Test status
Simulation time 188652134 ps
CPU time 10.72 seconds
Started Sep 27 01:11:41 PM PDT 23
Finished Sep 27 01:11:52 PM PDT 23
Peak memory 212816 kb
Host smart-595adfc3-ecc6-4f56-b230-6c4359526111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407730745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3407730745
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1401533005
Short name T293
Test name
Test status
Simulation time 1433241431 ps
CPU time 18.8 seconds
Started Sep 27 01:11:39 PM PDT 23
Finished Sep 27 01:11:58 PM PDT 23
Peak memory 211132 kb
Host smart-e61c355f-ee16-49c6-8298-92e51939df0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401533005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1401533005
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.327133546
Short name T2
Test name
Test status
Simulation time 107439984 ps
CPU time 4.32 seconds
Started Sep 27 01:11:17 PM PDT 23
Finished Sep 27 01:11:22 PM PDT 23
Peak memory 210980 kb
Host smart-77d695d5-db74-4057-b122-d8bdd10237df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327133546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.327133546
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.364047126
Short name T417
Test name
Test status
Simulation time 282835250828 ps
CPU time 258.98 seconds
Started Sep 27 01:11:19 PM PDT 23
Finished Sep 27 01:15:38 PM PDT 23
Peak memory 212400 kb
Host smart-c1d84133-efbc-4434-bd1b-3c06b49266dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364047126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.364047126
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2955304973
Short name T299
Test name
Test status
Simulation time 12371625133 ps
CPU time 16.26 seconds
Started Sep 27 01:11:56 PM PDT 23
Finished Sep 27 01:12:13 PM PDT 23
Peak memory 211132 kb
Host smart-e06676dd-f561-4c3a-b034-02d477a6705a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955304973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2955304973
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1492834126
Short name T214
Test name
Test status
Simulation time 10524393168 ps
CPU time 23.23 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:12:16 PM PDT 23
Peak memory 213560 kb
Host smart-2150b64a-b645-4e58-bacb-06aaaa44e1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492834126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1492834126
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2222501388
Short name T334
Test name
Test status
Simulation time 46348439563 ps
CPU time 119.92 seconds
Started Sep 27 01:12:00 PM PDT 23
Finished Sep 27 01:14:00 PM PDT 23
Peak memory 218396 kb
Host smart-263eef00-be58-452f-b9ad-9ee974d6df66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222501388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2222501388
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1177625448
Short name T407
Test name
Test status
Simulation time 689557393 ps
CPU time 4.31 seconds
Started Sep 27 01:21:12 PM PDT 23
Finished Sep 27 01:21:17 PM PDT 23
Peak memory 210996 kb
Host smart-18871d0e-ffdd-4637-88ba-1acf2ab6028e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177625448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1177625448
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4137002963
Short name T302
Test name
Test status
Simulation time 167034755253 ps
CPU time 192.5 seconds
Started Sep 27 01:12:01 PM PDT 23
Finished Sep 27 01:15:14 PM PDT 23
Peak memory 236580 kb
Host smart-4c4e10b5-3b08-4d03-8530-9b42cbcbf718
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137002963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4137002963
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4094798544
Short name T187
Test name
Test status
Simulation time 9846146180 ps
CPU time 23.78 seconds
Started Sep 27 01:21:08 PM PDT 23
Finished Sep 27 01:21:33 PM PDT 23
Peak memory 211164 kb
Host smart-b621575b-e04b-4dad-83de-c11b0b62aef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094798544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4094798544
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.924564623
Short name T364
Test name
Test status
Simulation time 3996017134 ps
CPU time 12.31 seconds
Started Sep 27 01:12:07 PM PDT 23
Finished Sep 27 01:12:20 PM PDT 23
Peak memory 211140 kb
Host smart-bb8763c3-76ad-4c34-9847-6968a3846855
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924564623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.924564623
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3379280999
Short name T303
Test name
Test status
Simulation time 7185691618 ps
CPU time 35.17 seconds
Started Sep 27 01:12:18 PM PDT 23
Finished Sep 27 01:12:53 PM PDT 23
Peak memory 213724 kb
Host smart-3aac2181-5647-484a-91c2-48a2139c3d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379280999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3379280999
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.367158572
Short name T269
Test name
Test status
Simulation time 2187390216 ps
CPU time 16.94 seconds
Started Sep 27 01:11:49 PM PDT 23
Finished Sep 27 01:12:06 PM PDT 23
Peak memory 213548 kb
Host smart-b597b982-ac91-4fb4-9ead-12fe6c42fd8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367158572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.367158572
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1780186422
Short name T346
Test name
Test status
Simulation time 121871589374 ps
CPU time 9428.39 seconds
Started Sep 27 01:14:07 PM PDT 23
Finished Sep 27 03:51:17 PM PDT 23
Peak memory 249096 kb
Host smart-f369aed9-d0e9-4d98-87b5-017a920ec190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780186422 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1780186422
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.120210501
Short name T286
Test name
Test status
Simulation time 538886658 ps
CPU time 6.1 seconds
Started Sep 27 01:22:09 PM PDT 23
Finished Sep 27 01:22:15 PM PDT 23
Peak memory 211068 kb
Host smart-ee6e0413-93b7-4da9-a492-474990f6e1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120210501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.120210501
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3400116790
Short name T355
Test name
Test status
Simulation time 4863377858 ps
CPU time 112.83 seconds
Started Sep 27 01:11:20 PM PDT 23
Finished Sep 27 01:13:13 PM PDT 23
Peak memory 236700 kb
Host smart-4c1df5bb-32e0-46be-b88d-18bdc16e11ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400116790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3400116790
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.776596227
Short name T386
Test name
Test status
Simulation time 27371270154 ps
CPU time 34.72 seconds
Started Sep 27 01:19:44 PM PDT 23
Finished Sep 27 01:20:19 PM PDT 23
Peak memory 212416 kb
Host smart-aaff61e9-78b2-4b3e-b56c-f13daab80671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776596227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.776596227
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3692094359
Short name T362
Test name
Test status
Simulation time 1077569151 ps
CPU time 11.88 seconds
Started Sep 27 01:14:24 PM PDT 23
Finished Sep 27 01:14:37 PM PDT 23
Peak memory 211060 kb
Host smart-8086082a-3376-492d-96b0-bac3d7c8c321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692094359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3692094359
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.191823781
Short name T258
Test name
Test status
Simulation time 1025809537 ps
CPU time 16.4 seconds
Started Sep 27 01:17:37 PM PDT 23
Finished Sep 27 01:17:54 PM PDT 23
Peak memory 212404 kb
Host smart-219f2813-6be1-4f6b-8923-a23df90ddf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191823781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.191823781
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1903385037
Short name T179
Test name
Test status
Simulation time 2237286887 ps
CPU time 26.62 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:12:13 PM PDT 23
Peak memory 214032 kb
Host smart-0651d535-4e3a-4115-9906-6fbdd8364060
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903385037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1903385037
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3924407818
Short name T427
Test name
Test status
Simulation time 241857532831 ps
CPU time 10331.5 seconds
Started Sep 27 01:11:20 PM PDT 23
Finished Sep 27 04:03:33 PM PDT 23
Peak memory 234768 kb
Host smart-357e81bc-4807-4848-9c1f-085fc17a7327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924407818 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3924407818
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3592172890
Short name T21
Test name
Test status
Simulation time 856090140 ps
CPU time 9.51 seconds
Started Sep 27 01:13:59 PM PDT 23
Finished Sep 27 01:14:09 PM PDT 23
Peak memory 211012 kb
Host smart-7b6a20b4-859c-43cf-9e80-5029f0e00f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592172890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3592172890
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2680667443
Short name T336
Test name
Test status
Simulation time 12927540990 ps
CPU time 131.98 seconds
Started Sep 27 01:13:05 PM PDT 23
Finished Sep 27 01:15:22 PM PDT 23
Peak memory 236780 kb
Host smart-1417d6b7-c01e-4131-85dd-4b7a045fe021
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680667443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2680667443
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1748882459
Short name T342
Test name
Test status
Simulation time 10489801719 ps
CPU time 25.85 seconds
Started Sep 27 01:14:06 PM PDT 23
Finished Sep 27 01:14:32 PM PDT 23
Peak memory 211796 kb
Host smart-ed7eca45-94e4-4757-a357-9eb67cea334e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748882459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1748882459
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4172382439
Short name T401
Test name
Test status
Simulation time 25367112699 ps
CPU time 16.35 seconds
Started Sep 27 01:28:58 PM PDT 23
Finished Sep 27 01:29:15 PM PDT 23
Peak memory 211144 kb
Host smart-3f4d9be2-2c51-4f3b-be9e-ad867aefe927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172382439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4172382439
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.4224650020
Short name T424
Test name
Test status
Simulation time 943913957 ps
CPU time 10.29 seconds
Started Sep 27 01:13:21 PM PDT 23
Finished Sep 27 01:13:31 PM PDT 23
Peak memory 212928 kb
Host smart-2edcc77f-4863-4233-88c6-96389f3a308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224650020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.4224650020
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1936445010
Short name T189
Test name
Test status
Simulation time 16953006054 ps
CPU time 49.53 seconds
Started Sep 27 01:19:39 PM PDT 23
Finished Sep 27 01:20:29 PM PDT 23
Peak memory 213176 kb
Host smart-45e1be73-47ac-4e0a-8ce0-d67d1c06072e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936445010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1936445010
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2297155087
Short name T161
Test name
Test status
Simulation time 7083549737 ps
CPU time 108.71 seconds
Started Sep 27 01:11:21 PM PDT 23
Finished Sep 27 01:13:10 PM PDT 23
Peak memory 220780 kb
Host smart-86b1e565-5d8f-4bf0-a401-eb3f982d94e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297155087 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2297155087
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1002727547
Short name T340
Test name
Test status
Simulation time 132172266 ps
CPU time 5.11 seconds
Started Sep 27 01:11:49 PM PDT 23
Finished Sep 27 01:11:54 PM PDT 23
Peak memory 211048 kb
Host smart-39067688-6a70-412b-af3d-2dacb74a926d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002727547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1002727547
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1208720786
Short name T213
Test name
Test status
Simulation time 19029175218 ps
CPU time 129.81 seconds
Started Sep 27 01:12:15 PM PDT 23
Finished Sep 27 01:14:25 PM PDT 23
Peak memory 228368 kb
Host smart-5800ad95-2674-4953-a87d-02fb8dfde60a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208720786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1208720786
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4115124946
Short name T326
Test name
Test status
Simulation time 6398780195 ps
CPU time 29.22 seconds
Started Sep 27 01:12:11 PM PDT 23
Finished Sep 27 01:12:41 PM PDT 23
Peak memory 211896 kb
Host smart-ed9c3e4e-ddb4-499e-9865-93c7da92cebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115124946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4115124946
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1783311754
Short name T230
Test name
Test status
Simulation time 1003399475 ps
CPU time 11.69 seconds
Started Sep 27 01:11:44 PM PDT 23
Finished Sep 27 01:11:56 PM PDT 23
Peak memory 210656 kb
Host smart-5e843610-7218-458c-bf14-d80562e4ffe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1783311754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1783311754
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2019278510
Short name T176
Test name
Test status
Simulation time 40972914831 ps
CPU time 27.25 seconds
Started Sep 27 01:17:33 PM PDT 23
Finished Sep 27 01:18:01 PM PDT 23
Peak memory 213136 kb
Host smart-32fcdec6-8766-4aa8-86b3-5437213022d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019278510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2019278510
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.455660722
Short name T354
Test name
Test status
Simulation time 3990047930 ps
CPU time 51.92 seconds
Started Sep 27 01:11:45 PM PDT 23
Finished Sep 27 01:12:37 PM PDT 23
Peak memory 216048 kb
Host smart-804afac4-f653-4507-bf28-885fb6463f09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455660722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.455660722
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3569406823
Short name T345
Test name
Test status
Simulation time 246986420333 ps
CPU time 2717.91 seconds
Started Sep 27 01:12:10 PM PDT 23
Finished Sep 27 01:57:29 PM PDT 23
Peak memory 235788 kb
Host smart-86acded9-745d-40a0-bb49-dab40083a8dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569406823 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3569406823
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.26062779
Short name T311
Test name
Test status
Simulation time 9866715741 ps
CPU time 15.09 seconds
Started Sep 27 01:11:40 PM PDT 23
Finished Sep 27 01:11:55 PM PDT 23
Peak memory 211144 kb
Host smart-4563cead-cc7f-475f-9cb9-0ff5c8c7a2ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26062779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.26062779
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.529790728
Short name T58
Test name
Test status
Simulation time 4871054294 ps
CPU time 153.73 seconds
Started Sep 27 01:11:38 PM PDT 23
Finished Sep 27 01:14:13 PM PDT 23
Peak memory 237756 kb
Host smart-36d45d61-c2b0-46bf-9cea-65105bb8c5ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529790728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.529790728
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.992101531
Short name T232
Test name
Test status
Simulation time 11272954353 ps
CPU time 24.78 seconds
Started Sep 27 01:11:47 PM PDT 23
Finished Sep 27 01:12:12 PM PDT 23
Peak memory 212060 kb
Host smart-01aef436-2df6-4f70-a027-8f936966c1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992101531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.992101531
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.249844916
Short name T260
Test name
Test status
Simulation time 2159089579 ps
CPU time 17.37 seconds
Started Sep 27 01:11:45 PM PDT 23
Finished Sep 27 01:12:03 PM PDT 23
Peak memory 211180 kb
Host smart-8d1cad89-a26d-4914-8e86-f6e580e3766c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249844916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.249844916
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1706961610
Short name T314
Test name
Test status
Simulation time 563589222 ps
CPU time 10.79 seconds
Started Sep 27 01:11:44 PM PDT 23
Finished Sep 27 01:11:56 PM PDT 23
Peak memory 212204 kb
Host smart-88092fd3-a7b0-4c9a-b914-a72208b2f8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706961610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1706961610
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1389455805
Short name T173
Test name
Test status
Simulation time 43569716754 ps
CPU time 29.57 seconds
Started Sep 27 01:12:10 PM PDT 23
Finished Sep 27 01:12:40 PM PDT 23
Peak memory 215136 kb
Host smart-8bdb9e0e-018a-4825-947c-f0d96d666c0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389455805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1389455805
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.851316485
Short name T181
Test name
Test status
Simulation time 14209855167 ps
CPU time 15.61 seconds
Started Sep 27 01:12:16 PM PDT 23
Finished Sep 27 01:12:31 PM PDT 23
Peak memory 211152 kb
Host smart-347161fb-b8e9-4b08-8ff1-cfb56e46f95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851316485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.851316485
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2751210595
Short name T367
Test name
Test status
Simulation time 134707387690 ps
CPU time 323.27 seconds
Started Sep 27 01:11:58 PM PDT 23
Finished Sep 27 01:17:21 PM PDT 23
Peak memory 234824 kb
Host smart-2cc29338-87bf-464b-a47c-d08a61fc96b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751210595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2751210595
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2749846457
Short name T410
Test name
Test status
Simulation time 43405458116 ps
CPU time 25.96 seconds
Started Sep 27 01:12:11 PM PDT 23
Finished Sep 27 01:12:37 PM PDT 23
Peak memory 211396 kb
Host smart-22f99e79-94d7-4d52-96a4-1ad45c718dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749846457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2749846457
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3497643330
Short name T192
Test name
Test status
Simulation time 391332089 ps
CPU time 5.58 seconds
Started Sep 27 01:11:44 PM PDT 23
Finished Sep 27 01:11:50 PM PDT 23
Peak memory 211116 kb
Host smart-8a5fcc57-6b3a-44a0-9e46-789ef3cf8492
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497643330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3497643330
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.237289403
Short name T17
Test name
Test status
Simulation time 7700776429 ps
CPU time 33.59 seconds
Started Sep 27 01:11:34 PM PDT 23
Finished Sep 27 01:12:08 PM PDT 23
Peak memory 213412 kb
Host smart-4afc03db-89ca-4f3b-9f3f-b6626868a32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237289403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.237289403
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1551508266
Short name T103
Test name
Test status
Simulation time 2086681902 ps
CPU time 14.99 seconds
Started Sep 27 01:11:45 PM PDT 23
Finished Sep 27 01:12:00 PM PDT 23
Peak memory 211048 kb
Host smart-14c96fcc-12ce-4755-88dd-c1d312ea907a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551508266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1551508266
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1421977755
Short name T297
Test name
Test status
Simulation time 34234094143 ps
CPU time 2863.23 seconds
Started Sep 27 01:11:42 PM PDT 23
Finished Sep 27 01:59:26 PM PDT 23
Peak memory 228076 kb
Host smart-fa79816d-d97a-4638-86a1-61ad90dcfc7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421977755 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1421977755
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2068135617
Short name T188
Test name
Test status
Simulation time 332568665 ps
CPU time 4.49 seconds
Started Sep 27 01:12:12 PM PDT 23
Finished Sep 27 01:12:17 PM PDT 23
Peak memory 211096 kb
Host smart-100cbbf4-d0e6-4c8c-b393-be2921d9a608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068135617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2068135617
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1732495419
Short name T289
Test name
Test status
Simulation time 26033667794 ps
CPU time 219.48 seconds
Started Sep 27 01:12:19 PM PDT 23
Finished Sep 27 01:15:58 PM PDT 23
Peak memory 236744 kb
Host smart-054362ef-a9eb-4349-91fa-b0b87b1c0e53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732495419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1732495419
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1894800148
Short name T273
Test name
Test status
Simulation time 7824442324 ps
CPU time 31.85 seconds
Started Sep 27 01:12:08 PM PDT 23
Finished Sep 27 01:12:40 PM PDT 23
Peak memory 211836 kb
Host smart-a3a089e3-fdca-4eff-af37-aaceba1d1852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894800148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1894800148
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2179797523
Short name T243
Test name
Test status
Simulation time 100679605 ps
CPU time 6.13 seconds
Started Sep 27 01:11:36 PM PDT 23
Finished Sep 27 01:11:43 PM PDT 23
Peak memory 210804 kb
Host smart-3de52155-6163-42d5-8216-de8c3bf22a11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2179797523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2179797523
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2420850834
Short name T239
Test name
Test status
Simulation time 2504537748 ps
CPU time 29.92 seconds
Started Sep 27 01:11:42 PM PDT 23
Finished Sep 27 01:12:13 PM PDT 23
Peak memory 212304 kb
Host smart-1df09507-9308-47c9-a0c2-646ea6c76389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420850834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2420850834
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2567312677
Short name T352
Test name
Test status
Simulation time 23762500608 ps
CPU time 47.52 seconds
Started Sep 27 01:11:51 PM PDT 23
Finished Sep 27 01:12:39 PM PDT 23
Peak memory 216344 kb
Host smart-340d6f30-ce21-4e6b-9505-92d1fd1f5e9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567312677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2567312677
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.899514001
Short name T12
Test name
Test status
Simulation time 126961024324 ps
CPU time 1894.68 seconds
Started Sep 27 01:11:57 PM PDT 23
Finished Sep 27 01:43:32 PM PDT 23
Peak memory 235808 kb
Host smart-195f5b95-89f5-4ba0-ac29-63b5d2934fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899514001 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.899514001
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.100965526
Short name T307
Test name
Test status
Simulation time 27136430757 ps
CPU time 132.74 seconds
Started Sep 27 01:12:02 PM PDT 23
Finished Sep 27 01:14:15 PM PDT 23
Peak memory 213380 kb
Host smart-262ff1ca-b400-443d-ab8e-1083e696616a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100965526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.100965526
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1353665166
Short name T1
Test name
Test status
Simulation time 335275044 ps
CPU time 9.86 seconds
Started Sep 27 01:12:12 PM PDT 23
Finished Sep 27 01:12:22 PM PDT 23
Peak memory 211404 kb
Host smart-a8de26c6-8be5-43f0-93d7-1331bbaba4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353665166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1353665166
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1833236970
Short name T290
Test name
Test status
Simulation time 1840142268 ps
CPU time 15.27 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:12:02 PM PDT 23
Peak memory 211088 kb
Host smart-0df35585-471f-4dbb-a247-720e9f1ca0ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833236970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1833236970
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3430713374
Short name T368
Test name
Test status
Simulation time 692701608 ps
CPU time 13.77 seconds
Started Sep 27 01:11:44 PM PDT 23
Finished Sep 27 01:11:58 PM PDT 23
Peak memory 212004 kb
Host smart-3fc1f25e-150e-4f7d-a737-77cb10bfbaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430713374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3430713374
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.985072888
Short name T378
Test name
Test status
Simulation time 40853798448 ps
CPU time 1336.25 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:34:03 PM PDT 23
Peak memory 235728 kb
Host smart-f5bdd9ee-6adc-4951-9ca7-2541d47dca39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985072888 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.985072888
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1841924937
Short name T52
Test name
Test status
Simulation time 1835740556 ps
CPU time 14.53 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:12:02 PM PDT 23
Peak memory 211052 kb
Host smart-79143585-ce9a-47ff-90b5-28e80b8c185d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841924937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1841924937
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.324698326
Short name T238
Test name
Test status
Simulation time 47659910796 ps
CPU time 226.62 seconds
Started Sep 27 01:11:47 PM PDT 23
Finished Sep 27 01:15:34 PM PDT 23
Peak memory 228316 kb
Host smart-b80450b5-78e9-4c28-a34c-bac7bb6154d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324698326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.324698326
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3888428513
Short name T268
Test name
Test status
Simulation time 4141152462 ps
CPU time 34.3 seconds
Started Sep 27 01:11:44 PM PDT 23
Finished Sep 27 01:12:19 PM PDT 23
Peak memory 211164 kb
Host smart-2a809f4d-1b44-4162-bcb6-5b165af51ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888428513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3888428513
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1241381948
Short name T209
Test name
Test status
Simulation time 169227894 ps
CPU time 5.29 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:11:51 PM PDT 23
Peak memory 210952 kb
Host smart-8cb3489a-a383-44ff-a870-0cdc45529552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241381948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1241381948
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.4193084985
Short name T408
Test name
Test status
Simulation time 360804416 ps
CPU time 10.62 seconds
Started Sep 27 01:12:09 PM PDT 23
Finished Sep 27 01:12:20 PM PDT 23
Peak memory 213056 kb
Host smart-37f6339d-2200-4026-b41f-27b7ffb54e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193084985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.4193084985
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2186781090
Short name T319
Test name
Test status
Simulation time 1165378973 ps
CPU time 11.83 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:11:58 PM PDT 23
Peak memory 210888 kb
Host smart-be7d7954-2fdf-4af1-abb1-923f64e0ddee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186781090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2186781090
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1224663654
Short name T426
Test name
Test status
Simulation time 374792268423 ps
CPU time 3542.31 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 02:10:56 PM PDT 23
Peak memory 260392 kb
Host smart-f400122a-077a-4b27-82a9-7302ed78d937
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224663654 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1224663654
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4234024260
Short name T167
Test name
Test status
Simulation time 460884595 ps
CPU time 4.35 seconds
Started Sep 27 01:12:02 PM PDT 23
Finished Sep 27 01:12:07 PM PDT 23
Peak memory 210956 kb
Host smart-884172f1-18ab-4468-91e8-97523c941120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234024260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4234024260
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1367531615
Short name T356
Test name
Test status
Simulation time 21392513610 ps
CPU time 218.5 seconds
Started Sep 27 01:11:34 PM PDT 23
Finished Sep 27 01:15:13 PM PDT 23
Peak memory 236832 kb
Host smart-02cc43c6-6b49-4c80-8f3c-2519dbc0651b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367531615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1367531615
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3354143678
Short name T285
Test name
Test status
Simulation time 36772533985 ps
CPU time 27.66 seconds
Started Sep 27 01:11:57 PM PDT 23
Finished Sep 27 01:12:25 PM PDT 23
Peak memory 211400 kb
Host smart-577c2d3f-dc24-4aae-9fc0-3d055dc76353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354143678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3354143678
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3120561986
Short name T288
Test name
Test status
Simulation time 617311636 ps
CPU time 5.46 seconds
Started Sep 27 01:11:50 PM PDT 23
Finished Sep 27 01:11:56 PM PDT 23
Peak memory 211036 kb
Host smart-eb2b64d9-6b2b-4959-b9f7-3e883c5a1b48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120561986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3120561986
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3779096335
Short name T41
Test name
Test status
Simulation time 3519668317 ps
CPU time 65.69 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:12:59 PM PDT 23
Peak memory 237104 kb
Host smart-d968dd1a-f6bd-44b4-90a0-cdbaf91f52d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779096335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3779096335
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.432887703
Short name T3
Test name
Test status
Simulation time 10442575523 ps
CPU time 27.97 seconds
Started Sep 27 01:11:45 PM PDT 23
Finished Sep 27 01:12:13 PM PDT 23
Peak memory 213188 kb
Host smart-fb4760dc-1110-45ef-b347-d63cced45b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432887703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.432887703
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1325913197
Short name T266
Test name
Test status
Simulation time 295977497 ps
CPU time 16.11 seconds
Started Sep 27 01:11:04 PM PDT 23
Finished Sep 27 01:11:20 PM PDT 23
Peak memory 214348 kb
Host smart-337279b3-bf3b-40e4-9209-f006420882fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325913197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1325913197
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2306229773
Short name T208
Test name
Test status
Simulation time 1770906509 ps
CPU time 14.02 seconds
Started Sep 27 01:11:51 PM PDT 23
Finished Sep 27 01:12:06 PM PDT 23
Peak memory 210924 kb
Host smart-63eb2da7-e2ad-4cd1-9955-94f68d4ed0f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306229773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2306229773
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2053873211
Short name T204
Test name
Test status
Simulation time 7929093604 ps
CPU time 117.28 seconds
Started Sep 27 01:11:51 PM PDT 23
Finished Sep 27 01:13:49 PM PDT 23
Peak memory 237796 kb
Host smart-2a279f5a-3aa5-4e99-bffd-874648c463fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053873211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2053873211
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2391579333
Short name T38
Test name
Test status
Simulation time 7665310588 ps
CPU time 32.56 seconds
Started Sep 27 01:12:05 PM PDT 23
Finished Sep 27 01:12:38 PM PDT 23
Peak memory 212080 kb
Host smart-d26ed2b6-041e-43e5-85eb-135f75a9951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391579333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2391579333
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.978661727
Short name T373
Test name
Test status
Simulation time 379814113 ps
CPU time 5.88 seconds
Started Sep 27 01:12:04 PM PDT 23
Finished Sep 27 01:12:11 PM PDT 23
Peak memory 211040 kb
Host smart-6e6dc8c1-f9fb-49b0-9412-005c3114d9c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978661727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.978661727
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3917286242
Short name T162
Test name
Test status
Simulation time 5461466129 ps
CPU time 31.72 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:12:18 PM PDT 23
Peak memory 212628 kb
Host smart-dbe6d0ea-bb71-47ca-8a94-8149329cb85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917286242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3917286242
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.989253985
Short name T165
Test name
Test status
Simulation time 2047465627 ps
CPU time 18.97 seconds
Started Sep 27 01:12:01 PM PDT 23
Finished Sep 27 01:12:21 PM PDT 23
Peak memory 211252 kb
Host smart-c339ccb3-df98-493d-a26b-07d05099c74f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989253985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.989253985
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1491176920
Short name T166
Test name
Test status
Simulation time 2928583600 ps
CPU time 9.14 seconds
Started Sep 27 01:12:15 PM PDT 23
Finished Sep 27 01:12:24 PM PDT 23
Peak memory 211164 kb
Host smart-a0ce67a7-4ed4-4bbd-9341-e880c5d0b362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491176920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1491176920
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.451976152
Short name T361
Test name
Test status
Simulation time 15956604688 ps
CPU time 110.56 seconds
Started Sep 27 01:12:00 PM PDT 23
Finished Sep 27 01:13:51 PM PDT 23
Peak memory 236556 kb
Host smart-20a4e026-8d7f-4c15-849c-a615e99aab88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451976152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.451976152
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4131822540
Short name T20
Test name
Test status
Simulation time 10385701594 ps
CPU time 24.09 seconds
Started Sep 27 01:11:56 PM PDT 23
Finished Sep 27 01:12:21 PM PDT 23
Peak memory 211504 kb
Host smart-ba3ed590-3437-49ab-983f-55d74054ae89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131822540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4131822540
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1993944555
Short name T376
Test name
Test status
Simulation time 539835113 ps
CPU time 5.62 seconds
Started Sep 27 01:12:05 PM PDT 23
Finished Sep 27 01:12:11 PM PDT 23
Peak memory 210980 kb
Host smart-dcd03a17-b2c7-4b52-8b4c-a226e0e36965
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993944555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1993944555
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3766726646
Short name T305
Test name
Test status
Simulation time 2979710207 ps
CPU time 26.26 seconds
Started Sep 27 01:12:05 PM PDT 23
Finished Sep 27 01:12:32 PM PDT 23
Peak memory 212504 kb
Host smart-f27e8e25-2b0b-470f-8dfe-946cd0e80acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766726646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3766726646
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1119367768
Short name T86
Test name
Test status
Simulation time 8112588009 ps
CPU time 51.22 seconds
Started Sep 27 01:11:49 PM PDT 23
Finished Sep 27 01:12:41 PM PDT 23
Peak memory 215692 kb
Host smart-b7758f32-47dc-47ad-a5de-ee0930b5aa2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119367768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1119367768
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2957867118
Short name T318
Test name
Test status
Simulation time 187552915650 ps
CPU time 1908.07 seconds
Started Sep 27 01:12:13 PM PDT 23
Finished Sep 27 01:44:01 PM PDT 23
Peak memory 249632 kb
Host smart-54d05159-c25b-4bf8-89ef-f75fdc79892a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957867118 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2957867118
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1917353819
Short name T203
Test name
Test status
Simulation time 172078079 ps
CPU time 4.33 seconds
Started Sep 27 01:12:07 PM PDT 23
Finished Sep 27 01:12:11 PM PDT 23
Peak memory 211076 kb
Host smart-fc6207d1-0fde-47ec-8249-7686d6804b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917353819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1917353819
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.202507429
Short name T338
Test name
Test status
Simulation time 15015572157 ps
CPU time 192.31 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:15:02 PM PDT 23
Peak memory 228480 kb
Host smart-ca1ca9c0-36c0-4d00-b00c-66606258ef51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202507429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.202507429
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2275053829
Short name T396
Test name
Test status
Simulation time 3762438833 ps
CPU time 31.78 seconds
Started Sep 27 01:12:05 PM PDT 23
Finished Sep 27 01:12:37 PM PDT 23
Peak memory 211156 kb
Host smart-7f0f1c6b-7644-4c45-bf4e-daef14369745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275053829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2275053829
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4100437775
Short name T210
Test name
Test status
Simulation time 8095743987 ps
CPU time 16.56 seconds
Started Sep 27 01:12:11 PM PDT 23
Finished Sep 27 01:12:28 PM PDT 23
Peak memory 211108 kb
Host smart-1ba4e189-8f6d-4b8d-b9c2-1a63613bc1c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4100437775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4100437775
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1388767482
Short name T85
Test name
Test status
Simulation time 1055099425 ps
CPU time 10.46 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:12:04 PM PDT 23
Peak memory 212764 kb
Host smart-a639c8bb-ccb6-4bc6-a0d2-3da4a408f091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388767482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1388767482
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.440809643
Short name T281
Test name
Test status
Simulation time 32007946313 ps
CPU time 42.02 seconds
Started Sep 27 01:12:14 PM PDT 23
Finished Sep 27 01:12:57 PM PDT 23
Peak memory 213108 kb
Host smart-d202786d-d96e-4bb6-9f96-107b4bf4cde9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440809643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.440809643
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4216763723
Short name T182
Test name
Test status
Simulation time 43978565434 ps
CPU time 2628.62 seconds
Started Sep 27 01:12:09 PM PDT 23
Finished Sep 27 01:55:58 PM PDT 23
Peak memory 231864 kb
Host smart-046e5bef-3f6f-4e86-bda5-5f1d2c6693b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216763723 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.4216763723
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1450062351
Short name T215
Test name
Test status
Simulation time 2059154244 ps
CPU time 7.38 seconds
Started Sep 27 01:12:05 PM PDT 23
Finished Sep 27 01:12:13 PM PDT 23
Peak memory 211024 kb
Host smart-d21ca333-7d93-4a7a-804b-7614acbc009f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450062351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1450062351
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2622948110
Short name T393
Test name
Test status
Simulation time 19907390895 ps
CPU time 205.29 seconds
Started Sep 27 01:12:08 PM PDT 23
Finished Sep 27 01:15:33 PM PDT 23
Peak memory 213412 kb
Host smart-022ea7a4-4aff-45ea-87f6-03d4fbf49c15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622948110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2622948110
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3525986989
Short name T255
Test name
Test status
Simulation time 2298560719 ps
CPU time 23.98 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:16 PM PDT 23
Peak memory 211276 kb
Host smart-2a14776a-f1fd-4903-8b98-79dc00a7efbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525986989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3525986989
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2902873175
Short name T308
Test name
Test status
Simulation time 2421016840 ps
CPU time 8.85 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:12:02 PM PDT 23
Peak memory 211096 kb
Host smart-f9bd7d34-c179-4804-8c12-fc506a973132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902873175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2902873175
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1687306958
Short name T265
Test name
Test status
Simulation time 232588956 ps
CPU time 9.95 seconds
Started Sep 27 01:12:11 PM PDT 23
Finished Sep 27 01:12:21 PM PDT 23
Peak memory 212436 kb
Host smart-95726c9c-dea8-4b13-8099-bee6e09ff316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687306958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1687306958
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.11802976
Short name T163
Test name
Test status
Simulation time 1420098186 ps
CPU time 24.68 seconds
Started Sep 27 01:11:50 PM PDT 23
Finished Sep 27 01:12:14 PM PDT 23
Peak memory 213132 kb
Host smart-9f02a311-7348-47cf-abc3-7492ae59fdb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11802976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.rom_ctrl_stress_all.11802976
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1214808572
Short name T110
Test name
Test status
Simulation time 39896550699 ps
CPU time 818.88 seconds
Started Sep 27 01:12:09 PM PDT 23
Finished Sep 27 01:25:48 PM PDT 23
Peak memory 235740 kb
Host smart-d3f52591-6cae-4b2c-94f5-3aea53eaffc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214808572 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1214808572
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3366387140
Short name T196
Test name
Test status
Simulation time 6788315540 ps
CPU time 16.89 seconds
Started Sep 27 01:11:57 PM PDT 23
Finished Sep 27 01:12:14 PM PDT 23
Peak memory 211164 kb
Host smart-19795767-5083-4ae5-8111-fe938263a06d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366387140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3366387140
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2803978141
Short name T399
Test name
Test status
Simulation time 9539943129 ps
CPU time 175.56 seconds
Started Sep 27 01:12:07 PM PDT 23
Finished Sep 27 01:15:03 PM PDT 23
Peak memory 228548 kb
Host smart-7d22ed0c-733b-4e3f-a9aa-2661a8e39541
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803978141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2803978141
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4238445773
Short name T379
Test name
Test status
Simulation time 3021924120 ps
CPU time 27.67 seconds
Started Sep 27 01:12:12 PM PDT 23
Finished Sep 27 01:12:40 PM PDT 23
Peak memory 211328 kb
Host smart-1a3548d1-8e4f-4aa0-b898-939b618aba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238445773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4238445773
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3455973041
Short name T177
Test name
Test status
Simulation time 3970597815 ps
CPU time 11.73 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:04 PM PDT 23
Peak memory 211140 kb
Host smart-c7c505bc-fbe2-4a34-ab72-ceec6c390547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455973041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3455973041
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3602573339
Short name T259
Test name
Test status
Simulation time 15121204030 ps
CPU time 33.25 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:25 PM PDT 23
Peak memory 213800 kb
Host smart-2fff31fd-6cac-4249-b800-c4d518a33509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602573339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3602573339
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2360109838
Short name T312
Test name
Test status
Simulation time 1273839718 ps
CPU time 16.66 seconds
Started Sep 27 01:12:01 PM PDT 23
Finished Sep 27 01:12:18 PM PDT 23
Peak memory 213328 kb
Host smart-709e6a29-4b78-4209-a829-cf5d03e57d6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360109838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2360109838
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.676723301
Short name T170
Test name
Test status
Simulation time 85257625251 ps
CPU time 928.76 seconds
Started Sep 27 01:12:07 PM PDT 23
Finished Sep 27 01:27:36 PM PDT 23
Peak memory 228796 kb
Host smart-6c9fdb73-f500-4567-9e3a-71b80fd84990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676723301 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.676723301
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4243486477
Short name T6
Test name
Test status
Simulation time 86288863 ps
CPU time 4.35 seconds
Started Sep 27 01:12:11 PM PDT 23
Finished Sep 27 01:12:16 PM PDT 23
Peak memory 211000 kb
Host smart-87bd7bf9-829a-48b7-9bd5-ceb006d0527b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243486477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4243486477
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3308226756
Short name T278
Test name
Test status
Simulation time 41798276109 ps
CPU time 252.8 seconds
Started Sep 27 01:11:56 PM PDT 23
Finished Sep 27 01:16:09 PM PDT 23
Peak memory 212340 kb
Host smart-eac6bd82-6be0-468b-8d79-e09a7503aab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308226756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3308226756
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2663546775
Short name T420
Test name
Test status
Simulation time 168414290 ps
CPU time 10.18 seconds
Started Sep 27 01:12:01 PM PDT 23
Finished Sep 27 01:12:12 PM PDT 23
Peak memory 211056 kb
Host smart-f1e944ed-871c-4012-8857-4f49891144da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663546775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2663546775
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3164343139
Short name T198
Test name
Test status
Simulation time 1650532922 ps
CPU time 14.12 seconds
Started Sep 27 01:12:07 PM PDT 23
Finished Sep 27 01:12:21 PM PDT 23
Peak memory 211068 kb
Host smart-630f7dfb-c4b5-4cdc-b54f-f7d22fe594e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164343139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3164343139
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.462745925
Short name T197
Test name
Test status
Simulation time 15753843375 ps
CPU time 33.24 seconds
Started Sep 27 01:11:36 PM PDT 23
Finished Sep 27 01:12:09 PM PDT 23
Peak memory 213644 kb
Host smart-95b7285c-7a54-4286-9a02-e394e50e246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462745925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.462745925
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1976178093
Short name T175
Test name
Test status
Simulation time 2035954680 ps
CPU time 27.76 seconds
Started Sep 27 01:12:19 PM PDT 23
Finished Sep 27 01:12:47 PM PDT 23
Peak memory 214900 kb
Host smart-3ee3810d-e20d-4153-a103-5d83a9bec339
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976178093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1976178093
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3533508604
Short name T190
Test name
Test status
Simulation time 223008458619 ps
CPU time 10239.2 seconds
Started Sep 27 01:11:56 PM PDT 23
Finished Sep 27 04:02:37 PM PDT 23
Peak memory 246448 kb
Host smart-7d3b31d3-c51c-4e77-840f-722862346381
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533508604 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3533508604
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.480944755
Short name T333
Test name
Test status
Simulation time 7364405660 ps
CPU time 11.34 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:11:57 PM PDT 23
Peak memory 211092 kb
Host smart-5f65a15c-2119-446a-a4c8-2ef6158727ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480944755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.480944755
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.234429736
Short name T296
Test name
Test status
Simulation time 40032137206 ps
CPU time 386.41 seconds
Started Sep 27 01:12:20 PM PDT 23
Finished Sep 27 01:18:46 PM PDT 23
Peak memory 224904 kb
Host smart-732fd182-f8b1-4155-aec7-109344bfb17a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234429736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.234429736
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.82759709
Short name T320
Test name
Test status
Simulation time 9439202778 ps
CPU time 24.78 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:12:11 PM PDT 23
Peak memory 211576 kb
Host smart-e2141617-f33a-4fd9-a53c-dd7cb6750cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82759709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.82759709
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.509717798
Short name T108
Test name
Test status
Simulation time 3897063519 ps
CPU time 12.89 seconds
Started Sep 27 01:12:20 PM PDT 23
Finished Sep 27 01:12:33 PM PDT 23
Peak memory 211056 kb
Host smart-712ae449-06e2-40db-be2e-2a6a5304ee78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=509717798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.509717798
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.543044198
Short name T294
Test name
Test status
Simulation time 5101948670 ps
CPU time 24.22 seconds
Started Sep 27 01:11:57 PM PDT 23
Finished Sep 27 01:12:21 PM PDT 23
Peak memory 212868 kb
Host smart-31ec5f6a-1e4a-46cd-8e76-060637a04051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543044198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.543044198
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3220025560
Short name T264
Test name
Test status
Simulation time 15993913761 ps
CPU time 53.5 seconds
Started Sep 27 01:11:59 PM PDT 23
Finished Sep 27 01:12:53 PM PDT 23
Peak memory 216864 kb
Host smart-475cfedc-e378-4fbe-9382-e3d57a9e5d00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220025560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3220025560
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3125593796
Short name T272
Test name
Test status
Simulation time 690035407 ps
CPU time 8.67 seconds
Started Sep 27 01:12:27 PM PDT 23
Finished Sep 27 01:12:36 PM PDT 23
Peak memory 211036 kb
Host smart-74ff6d2a-fe0e-4ffd-8f40-7c9d015aa81a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125593796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3125593796
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3484230774
Short name T421
Test name
Test status
Simulation time 88939053740 ps
CPU time 512.9 seconds
Started Sep 27 01:11:51 PM PDT 23
Finished Sep 27 01:20:24 PM PDT 23
Peak memory 228124 kb
Host smart-fa313cca-5343-4214-859a-d7969f24e34f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484230774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3484230774
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3128693179
Short name T405
Test name
Test status
Simulation time 1911196574 ps
CPU time 21.45 seconds
Started Sep 27 01:12:47 PM PDT 23
Finished Sep 27 01:13:09 PM PDT 23
Peak memory 211216 kb
Host smart-be996635-0c2d-4b60-8c7b-94e90b81630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128693179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3128693179
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2587326811
Short name T231
Test name
Test status
Simulation time 1995479389 ps
CPU time 16.09 seconds
Started Sep 27 01:12:17 PM PDT 23
Finished Sep 27 01:12:33 PM PDT 23
Peak memory 210788 kb
Host smart-7e8cc674-1e22-443a-a330-5a5a9e3fcb8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587326811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2587326811
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1489130497
Short name T102
Test name
Test status
Simulation time 19189515895 ps
CPU time 29.73 seconds
Started Sep 27 01:12:41 PM PDT 23
Finished Sep 27 01:13:11 PM PDT 23
Peak memory 213048 kb
Host smart-a30214d7-c0ff-44f1-9bd3-2328a3f56094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489130497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1489130497
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1633224798
Short name T315
Test name
Test status
Simulation time 12706735417 ps
CPU time 53.21 seconds
Started Sep 27 01:11:38 PM PDT 23
Finished Sep 27 01:12:33 PM PDT 23
Peak memory 216848 kb
Host smart-8abcb52b-32ff-4d0d-829c-139a8a36c932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633224798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1633224798
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3904237533
Short name T385
Test name
Test status
Simulation time 35046509650 ps
CPU time 1915.53 seconds
Started Sep 27 01:12:41 PM PDT 23
Finished Sep 27 01:44:37 PM PDT 23
Peak memory 235728 kb
Host smart-4bfd0cd7-8a6c-49f7-8540-903f779293e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904237533 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3904237533
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1335263055
Short name T159
Test name
Test status
Simulation time 2174846736 ps
CPU time 16.14 seconds
Started Sep 27 01:11:42 PM PDT 23
Finished Sep 27 01:11:59 PM PDT 23
Peak memory 211224 kb
Host smart-9f3c9dfd-d4b4-43e8-b144-fd22816554f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335263055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1335263055
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.6612447
Short name T301
Test name
Test status
Simulation time 29827122192 ps
CPU time 232.12 seconds
Started Sep 27 01:11:35 PM PDT 23
Finished Sep 27 01:15:27 PM PDT 23
Peak memory 236864 kb
Host smart-a0b7fc97-4379-43b0-af1f-84106fd54b01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6612447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_cor
rupt_sig_fatal_chk.6612447
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1204589097
Short name T350
Test name
Test status
Simulation time 5291872293 ps
CPU time 35.32 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:12:24 PM PDT 23
Peak memory 211344 kb
Host smart-0b983eef-e1e6-4826-9688-796243c2284f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204589097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1204589097
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.716763261
Short name T217
Test name
Test status
Simulation time 984617173 ps
CPU time 10.74 seconds
Started Sep 27 01:11:38 PM PDT 23
Finished Sep 27 01:11:49 PM PDT 23
Peak memory 211028 kb
Host smart-97b4c36b-2056-43ae-9772-42af07a49a46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716763261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.716763261
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2561176846
Short name T323
Test name
Test status
Simulation time 3475672052 ps
CPU time 29.35 seconds
Started Sep 27 01:12:58 PM PDT 23
Finished Sep 27 01:13:28 PM PDT 23
Peak memory 212488 kb
Host smart-2b9ea8d4-eaf6-4c8d-8c15-a87358b75f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561176846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2561176846
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1790857664
Short name T237
Test name
Test status
Simulation time 1357263278 ps
CPU time 11.41 seconds
Started Sep 27 01:12:26 PM PDT 23
Finished Sep 27 01:12:37 PM PDT 23
Peak memory 210976 kb
Host smart-2943e343-54ed-4d0f-ae39-048f530bfbb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790857664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1790857664
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.4146428749
Short name T256
Test name
Test status
Simulation time 39656602654 ps
CPU time 2612.39 seconds
Started Sep 27 01:11:54 PM PDT 23
Finished Sep 27 01:55:32 PM PDT 23
Peak memory 235756 kb
Host smart-61165733-c6b7-4ed3-ae89-6122d0ee46cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146428749 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.4146428749
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3170751334
Short name T195
Test name
Test status
Simulation time 3800051184 ps
CPU time 7.67 seconds
Started Sep 27 01:11:36 PM PDT 23
Finished Sep 27 01:11:44 PM PDT 23
Peak memory 211160 kb
Host smart-14042b7d-10b3-4559-bebc-4c233554c442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170751334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3170751334
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1498521345
Short name T62
Test name
Test status
Simulation time 2457889904 ps
CPU time 146.04 seconds
Started Sep 27 01:11:36 PM PDT 23
Finished Sep 27 01:14:02 PM PDT 23
Peak memory 237532 kb
Host smart-2d18c658-6d4d-458c-b2b3-9da59719d058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498521345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1498521345
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1554321479
Short name T156
Test name
Test status
Simulation time 8823131781 ps
CPU time 35.15 seconds
Started Sep 27 01:11:42 PM PDT 23
Finished Sep 27 01:12:17 PM PDT 23
Peak memory 211544 kb
Host smart-61d456ad-926b-4df7-a669-c90804518666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554321479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1554321479
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2285594463
Short name T158
Test name
Test status
Simulation time 2145672684 ps
CPU time 15.29 seconds
Started Sep 27 01:11:45 PM PDT 23
Finished Sep 27 01:12:00 PM PDT 23
Peak memory 211084 kb
Host smart-ee2efb44-07a9-4e99-a04c-68ce52bcae1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285594463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2285594463
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.992372251
Short name T332
Test name
Test status
Simulation time 12085459768 ps
CPU time 27.82 seconds
Started Sep 27 01:11:56 PM PDT 23
Finished Sep 27 01:12:24 PM PDT 23
Peak memory 213832 kb
Host smart-b5d42498-149a-48d1-80f3-2b94900e65f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992372251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.992372251
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3634116809
Short name T193
Test name
Test status
Simulation time 1497394967 ps
CPU time 21.54 seconds
Started Sep 27 01:11:36 PM PDT 23
Finished Sep 27 01:11:58 PM PDT 23
Peak memory 215960 kb
Host smart-a0a678bd-dc7a-4f95-a403-5bc08031b238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634116809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3634116809
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3375233616
Short name T298
Test name
Test status
Simulation time 25870374905 ps
CPU time 5803.41 seconds
Started Sep 27 01:11:35 PM PDT 23
Finished Sep 27 02:48:20 PM PDT 23
Peak memory 235756 kb
Host smart-c6343c9c-975b-4dfe-ba28-a50486c377c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375233616 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3375233616
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3244859822
Short name T329
Test name
Test status
Simulation time 387569473 ps
CPU time 6.84 seconds
Started Sep 27 01:11:19 PM PDT 23
Finished Sep 27 01:11:26 PM PDT 23
Peak memory 211092 kb
Host smart-6a4edcc6-1817-4338-b27d-761f6715948e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244859822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3244859822
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3934571102
Short name T295
Test name
Test status
Simulation time 37917047048 ps
CPU time 381.35 seconds
Started Sep 27 01:11:55 PM PDT 23
Finished Sep 27 01:18:17 PM PDT 23
Peak memory 224948 kb
Host smart-ef025131-0b2c-418f-8698-6a99d9625af1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934571102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3934571102
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.324273964
Short name T325
Test name
Test status
Simulation time 17729495881 ps
CPU time 34.23 seconds
Started Sep 27 01:11:04 PM PDT 23
Finished Sep 27 01:11:39 PM PDT 23
Peak memory 211576 kb
Host smart-15fa8d53-ca10-4dd1-bed6-d68f3e3d9a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324273964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.324273964
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3977598147
Short name T360
Test name
Test status
Simulation time 3755018403 ps
CPU time 16.51 seconds
Started Sep 27 01:11:03 PM PDT 23
Finished Sep 27 01:11:20 PM PDT 23
Peak memory 211192 kb
Host smart-a8efebf4-76f5-4731-b23f-15d1b0bdef00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977598147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3977598147
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.97307697
Short name T43
Test name
Test status
Simulation time 4117929625 ps
CPU time 70.9 seconds
Started Sep 27 01:11:17 PM PDT 23
Finished Sep 27 01:12:28 PM PDT 23
Peak memory 236288 kb
Host smart-28f05fee-a964-4ba4-a04a-b93f1cd5bb96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97307697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.97307697
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.50049342
Short name T414
Test name
Test status
Simulation time 343960334 ps
CPU time 10.34 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:12:04 PM PDT 23
Peak memory 212884 kb
Host smart-ffd11672-b11e-4dde-95b4-06c1f8620842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50049342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.50049342
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1052178971
Short name T168
Test name
Test status
Simulation time 18446023474 ps
CPU time 51.67 seconds
Started Sep 27 01:11:03 PM PDT 23
Finished Sep 27 01:11:55 PM PDT 23
Peak memory 214112 kb
Host smart-930bab4c-e514-4a38-b6f2-a4215add9266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052178971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1052178971
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.4239875318
Short name T249
Test name
Test status
Simulation time 13423889692 ps
CPU time 498.84 seconds
Started Sep 27 01:11:03 PM PDT 23
Finished Sep 27 01:19:22 PM PDT 23
Peak memory 231484 kb
Host smart-91b1a0ab-4f45-4123-990a-f0b0cf9b9ce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239875318 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.4239875318
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2735196835
Short name T276
Test name
Test status
Simulation time 86358436 ps
CPU time 4.33 seconds
Started Sep 27 01:11:39 PM PDT 23
Finished Sep 27 01:11:44 PM PDT 23
Peak memory 211040 kb
Host smart-01365627-dd19-4d84-8c56-78b43f348364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735196835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2735196835
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3385807819
Short name T40
Test name
Test status
Simulation time 18852753739 ps
CPU time 226.3 seconds
Started Sep 27 01:11:59 PM PDT 23
Finished Sep 27 01:15:46 PM PDT 23
Peak memory 239844 kb
Host smart-3b8c2eac-9ec2-4360-9aa5-b7dd54df42e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385807819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3385807819
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4284480328
Short name T55
Test name
Test status
Simulation time 665482085 ps
CPU time 9.54 seconds
Started Sep 27 01:11:36 PM PDT 23
Finished Sep 27 01:11:46 PM PDT 23
Peak memory 211176 kb
Host smart-501c6311-271a-427b-9ad7-57d72aa50378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284480328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4284480328
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.271393131
Short name T250
Test name
Test status
Simulation time 1926833971 ps
CPU time 15.6 seconds
Started Sep 27 01:11:59 PM PDT 23
Finished Sep 27 01:12:15 PM PDT 23
Peak memory 211096 kb
Host smart-0ecf3c99-0ba1-48e7-8423-df4afd04e9d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271393131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.271393131
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.4069302309
Short name T19
Test name
Test status
Simulation time 17115350679 ps
CPU time 23.63 seconds
Started Sep 27 01:11:59 PM PDT 23
Finished Sep 27 01:12:23 PM PDT 23
Peak memory 213912 kb
Host smart-66965c87-e87f-4a28-b196-b35856d487a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069302309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.4069302309
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1358673696
Short name T400
Test name
Test status
Simulation time 4410207719 ps
CPU time 20.06 seconds
Started Sep 27 01:11:57 PM PDT 23
Finished Sep 27 01:12:17 PM PDT 23
Peak memory 211956 kb
Host smart-0c67401a-5659-46b2-bdbb-07828b774d7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358673696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1358673696
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3938448376
Short name T257
Test name
Test status
Simulation time 95369549341 ps
CPU time 1121.58 seconds
Started Sep 27 01:11:51 PM PDT 23
Finished Sep 27 01:30:33 PM PDT 23
Peak memory 229412 kb
Host smart-b719b684-53d6-4e9e-8e7b-90c748d39670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938448376 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3938448376
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1865995085
Short name T292
Test name
Test status
Simulation time 1284277564 ps
CPU time 11.73 seconds
Started Sep 27 01:11:36 PM PDT 23
Finished Sep 27 01:11:48 PM PDT 23
Peak memory 210768 kb
Host smart-77832456-dc1d-46da-85dd-aa2c7456e9ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865995085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1865995085
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2374238480
Short name T404
Test name
Test status
Simulation time 11647102998 ps
CPU time 118.71 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:13:45 PM PDT 23
Peak memory 236748 kb
Host smart-0e2c6610-6e3a-4eb3-9a2d-d4e605243d15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374238480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2374238480
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.898525317
Short name T366
Test name
Test status
Simulation time 7978957511 ps
CPU time 27.06 seconds
Started Sep 27 01:11:36 PM PDT 23
Finished Sep 27 01:12:05 PM PDT 23
Peak memory 211864 kb
Host smart-e627f04f-3bf6-44a6-92fe-3a454790b32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898525317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.898525317
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1906034040
Short name T207
Test name
Test status
Simulation time 470067371 ps
CPU time 8.89 seconds
Started Sep 27 01:11:43 PM PDT 23
Finished Sep 27 01:11:52 PM PDT 23
Peak memory 211040 kb
Host smart-5b4e51a7-c1b7-4dd7-b7bb-109e65b79239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1906034040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1906034040
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2356309299
Short name T395
Test name
Test status
Simulation time 11778651368 ps
CPU time 29.09 seconds
Started Sep 27 01:11:35 PM PDT 23
Finished Sep 27 01:12:04 PM PDT 23
Peak memory 213348 kb
Host smart-9532b253-ffb6-44ce-811a-0128de41680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356309299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2356309299
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1044275989
Short name T160
Test name
Test status
Simulation time 4193077470 ps
CPU time 52.87 seconds
Started Sep 27 01:11:43 PM PDT 23
Finished Sep 27 01:12:36 PM PDT 23
Peak memory 216972 kb
Host smart-085b0150-4c5e-4cae-8566-855347cd2eb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044275989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1044275989
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4232514650
Short name T34
Test name
Test status
Simulation time 21395645888 ps
CPU time 11.61 seconds
Started Sep 27 01:11:49 PM PDT 23
Finished Sep 27 01:12:01 PM PDT 23
Peak memory 211172 kb
Host smart-e83ad125-01a6-41a1-ad44-f2b721eb0289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232514650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4232514650
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4052229524
Short name T371
Test name
Test status
Simulation time 22312403076 ps
CPU time 271.34 seconds
Started Sep 27 01:11:50 PM PDT 23
Finished Sep 27 01:16:21 PM PDT 23
Peak memory 236568 kb
Host smart-c807b530-398b-47d2-9c21-3924890427dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052229524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.4052229524
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3561006870
Short name T227
Test name
Test status
Simulation time 13124883508 ps
CPU time 30.11 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:12:19 PM PDT 23
Peak memory 211620 kb
Host smart-3d7ff0eb-9ddb-47ae-a652-59d488b95a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561006870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3561006870
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2445748187
Short name T392
Test name
Test status
Simulation time 591705918 ps
CPU time 9.35 seconds
Started Sep 27 01:11:51 PM PDT 23
Finished Sep 27 01:12:00 PM PDT 23
Peak memory 211040 kb
Host smart-f97a19ac-26f0-4f98-9479-9f1ca5663527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2445748187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2445748187
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3652807763
Short name T245
Test name
Test status
Simulation time 8172942121 ps
CPU time 36.83 seconds
Started Sep 27 01:12:02 PM PDT 23
Finished Sep 27 01:12:39 PM PDT 23
Peak memory 213420 kb
Host smart-fed8d078-4b31-466d-96bd-a80d98c2d71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652807763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3652807763
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.828617868
Short name T89
Test name
Test status
Simulation time 5679933529 ps
CPU time 55.03 seconds
Started Sep 27 01:11:36 PM PDT 23
Finished Sep 27 01:12:31 PM PDT 23
Peak memory 215596 kb
Host smart-3cc74eba-8ea7-4b46-99bf-79c576c4a060
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828617868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.828617868
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3137440958
Short name T358
Test name
Test status
Simulation time 174910536 ps
CPU time 4.55 seconds
Started Sep 27 01:11:37 PM PDT 23
Finished Sep 27 01:11:43 PM PDT 23
Peak memory 211052 kb
Host smart-e28feb46-3883-482b-882d-0901437e4777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137440958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3137440958
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.288198414
Short name T370
Test name
Test status
Simulation time 12019529896 ps
CPU time 187.89 seconds
Started Sep 27 01:11:45 PM PDT 23
Finished Sep 27 01:14:54 PM PDT 23
Peak memory 233872 kb
Host smart-20d6463f-e90f-4116-b928-10ff81674ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288198414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.288198414
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2267197767
Short name T316
Test name
Test status
Simulation time 175379515 ps
CPU time 9.69 seconds
Started Sep 27 01:11:57 PM PDT 23
Finished Sep 27 01:12:07 PM PDT 23
Peak memory 211192 kb
Host smart-1f4fddeb-654b-4111-9e5f-6c7c19a9f91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267197767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2267197767
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3543674560
Short name T218
Test name
Test status
Simulation time 2228575261 ps
CPU time 17.17 seconds
Started Sep 27 01:11:44 PM PDT 23
Finished Sep 27 01:12:02 PM PDT 23
Peak memory 211120 kb
Host smart-5f5f0ee2-05ca-4b24-ad79-c82a6b64643d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543674560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3543674560
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1004960898
Short name T199
Test name
Test status
Simulation time 8194117657 ps
CPU time 29.57 seconds
Started Sep 27 01:11:40 PM PDT 23
Finished Sep 27 01:12:10 PM PDT 23
Peak memory 213736 kb
Host smart-a145ba9b-b025-4a2e-a6b0-8f9ed8efa788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004960898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1004960898
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3458770757
Short name T101
Test name
Test status
Simulation time 5965587523 ps
CPU time 25.33 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:12:12 PM PDT 23
Peak memory 215848 kb
Host smart-e33de7e2-acf9-4e95-9fc1-b321b6112a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458770757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3458770757
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3285116931
Short name T347
Test name
Test status
Simulation time 46683720361 ps
CPU time 1985.07 seconds
Started Sep 27 01:11:33 PM PDT 23
Finished Sep 27 01:44:39 PM PDT 23
Peak memory 234376 kb
Host smart-bac3cfae-ac48-4452-88e6-e50232fe47aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285116931 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3285116931
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1252427369
Short name T403
Test name
Test status
Simulation time 85779126 ps
CPU time 4.38 seconds
Started Sep 27 01:12:08 PM PDT 23
Finished Sep 27 01:12:13 PM PDT 23
Peak memory 211024 kb
Host smart-5418936a-60bc-494d-990f-544464303f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252427369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1252427369
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2604443353
Short name T35
Test name
Test status
Simulation time 64663202299 ps
CPU time 279.89 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:16:32 PM PDT 23
Peak memory 228544 kb
Host smart-82842b1c-9982-43fe-9125-a29485fe9a7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604443353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2604443353
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2200336644
Short name T219
Test name
Test status
Simulation time 175694647 ps
CPU time 9.5 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:11:55 PM PDT 23
Peak memory 211572 kb
Host smart-0fec0845-0a56-43e5-bc74-657f5bf5ef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200336644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2200336644
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3808133548
Short name T284
Test name
Test status
Simulation time 1549097291 ps
CPU time 9.23 seconds
Started Sep 27 01:11:43 PM PDT 23
Finished Sep 27 01:11:52 PM PDT 23
Peak memory 211024 kb
Host smart-7cd03407-1476-443c-8a62-42054ccb1da9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808133548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3808133548
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2988311121
Short name T4
Test name
Test status
Simulation time 14024079577 ps
CPU time 30.46 seconds
Started Sep 27 01:11:46 PM PDT 23
Finished Sep 27 01:12:16 PM PDT 23
Peak memory 213336 kb
Host smart-c6d75274-8526-4526-adf1-d3e8fb2548a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988311121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2988311121
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1819870208
Short name T236
Test name
Test status
Simulation time 808918585 ps
CPU time 25.95 seconds
Started Sep 27 01:11:33 PM PDT 23
Finished Sep 27 01:12:00 PM PDT 23
Peak memory 212704 kb
Host smart-34eeb6fe-1a60-4347-8120-4cb7377e3d75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819870208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1819870208
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3895160377
Short name T216
Test name
Test status
Simulation time 309704991 ps
CPU time 4.36 seconds
Started Sep 27 01:11:54 PM PDT 23
Finished Sep 27 01:11:59 PM PDT 23
Peak memory 210956 kb
Host smart-427192b3-942b-4f77-a5b6-f3d7a0b6cf91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895160377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3895160377
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1274722398
Short name T200
Test name
Test status
Simulation time 76563971809 ps
CPU time 399.01 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:18:32 PM PDT 23
Peak memory 234196 kb
Host smart-cb14c647-ac86-4153-81c9-c3c18a7bd5b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274722398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1274722398
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2471275278
Short name T37
Test name
Test status
Simulation time 5568885339 ps
CPU time 27.05 seconds
Started Sep 27 01:11:51 PM PDT 23
Finished Sep 27 01:12:18 PM PDT 23
Peak memory 211400 kb
Host smart-4f224c69-4c1a-4a44-90dc-4b943001e9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471275278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2471275278
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4170677402
Short name T252
Test name
Test status
Simulation time 4000787243 ps
CPU time 15.74 seconds
Started Sep 27 01:12:02 PM PDT 23
Finished Sep 27 01:12:17 PM PDT 23
Peak memory 211156 kb
Host smart-41360a77-aaf6-49e8-bcb5-c49f848e19fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4170677402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4170677402
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2070396663
Short name T327
Test name
Test status
Simulation time 3403760201 ps
CPU time 33.93 seconds
Started Sep 27 01:11:50 PM PDT 23
Finished Sep 27 01:12:24 PM PDT 23
Peak memory 212552 kb
Host smart-817248f4-d433-4374-85a7-83104f541b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070396663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2070396663
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2014299043
Short name T279
Test name
Test status
Simulation time 37227378542 ps
CPU time 52.26 seconds
Started Sep 27 01:11:49 PM PDT 23
Finished Sep 27 01:12:41 PM PDT 23
Peak memory 214056 kb
Host smart-c3e2b729-2e81-4f50-8ddc-b43a63e589f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014299043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2014299043
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3113897172
Short name T411
Test name
Test status
Simulation time 93011375 ps
CPU time 4.51 seconds
Started Sep 27 01:11:55 PM PDT 23
Finished Sep 27 01:12:00 PM PDT 23
Peak memory 210920 kb
Host smart-fe8294cd-fe3a-41f6-83ac-066455e96bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113897172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3113897172
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.934072307
Short name T39
Test name
Test status
Simulation time 93198887924 ps
CPU time 254.83 seconds
Started Sep 27 01:12:27 PM PDT 23
Finished Sep 27 01:16:42 PM PDT 23
Peak memory 237736 kb
Host smart-fe48723c-ca20-451b-893f-204c2c9e2b74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934072307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.934072307
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3210635248
Short name T419
Test name
Test status
Simulation time 1999015430 ps
CPU time 16.41 seconds
Started Sep 27 01:11:55 PM PDT 23
Finished Sep 27 01:12:11 PM PDT 23
Peak memory 211140 kb
Host smart-5e688710-fbdd-4ae5-a65d-3d2952eb3c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210635248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3210635248
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2442622002
Short name T384
Test name
Test status
Simulation time 1867990270 ps
CPU time 15.86 seconds
Started Sep 27 01:12:08 PM PDT 23
Finished Sep 27 01:12:24 PM PDT 23
Peak memory 211068 kb
Host smart-5a3cb7a9-b42d-4ffd-a925-19ea7d663c71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442622002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2442622002
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3753689773
Short name T267
Test name
Test status
Simulation time 16870812074 ps
CPU time 34.73 seconds
Started Sep 27 01:12:00 PM PDT 23
Finished Sep 27 01:12:35 PM PDT 23
Peak memory 213224 kb
Host smart-3660e39b-3227-4518-a81b-aeb94e9f839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753689773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3753689773
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2892469767
Short name T87
Test name
Test status
Simulation time 6103378019 ps
CPU time 20.84 seconds
Started Sep 27 01:12:07 PM PDT 23
Finished Sep 27 01:12:28 PM PDT 23
Peak memory 214160 kb
Host smart-f52adb4a-c9aa-4e64-b9b8-44c47b92e417
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892469767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2892469767
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1577506818
Short name T389
Test name
Test status
Simulation time 19593619832 ps
CPU time 16.51 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:12:05 PM PDT 23
Peak memory 211084 kb
Host smart-70decde0-b1f5-4fb6-9186-a2327c2f02d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577506818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1577506818
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3512661356
Short name T63
Test name
Test status
Simulation time 1841459922 ps
CPU time 102.08 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:13:30 PM PDT 23
Peak memory 237576 kb
Host smart-b4ab9fcf-b278-4225-a35a-bf41bae1d942
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512661356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3512661356
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.714749395
Short name T7
Test name
Test status
Simulation time 362497774 ps
CPU time 5.26 seconds
Started Sep 27 01:12:00 PM PDT 23
Finished Sep 27 01:12:06 PM PDT 23
Peak memory 211004 kb
Host smart-78039fa7-7acf-4914-9024-87765fa6e44f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=714749395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.714749395
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3921803386
Short name T348
Test name
Test status
Simulation time 2157735609 ps
CPU time 25.72 seconds
Started Sep 27 01:12:18 PM PDT 23
Finished Sep 27 01:12:44 PM PDT 23
Peak memory 212440 kb
Host smart-54d83891-0630-466b-8065-4391a7e4c942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921803386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3921803386
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1187508681
Short name T54
Test name
Test status
Simulation time 309245439 ps
CPU time 19.41 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:12:08 PM PDT 23
Peak memory 215596 kb
Host smart-2602a579-51f2-4c1d-a81b-110330e8698b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187508681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1187508681
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.315356911
Short name T351
Test name
Test status
Simulation time 137615626249 ps
CPU time 3649.09 seconds
Started Sep 27 01:11:47 PM PDT 23
Finished Sep 27 02:12:37 PM PDT 23
Peak memory 235744 kb
Host smart-701a8da6-1905-4ce4-93a3-c3ae83584048
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315356911 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.315356911
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1493531466
Short name T306
Test name
Test status
Simulation time 346597635 ps
CPU time 4.24 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:11:56 PM PDT 23
Peak memory 211084 kb
Host smart-a5ff7a5f-53d3-4af0-9384-89c1a7d7c9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493531466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1493531466
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2807484598
Short name T363
Test name
Test status
Simulation time 4129549947 ps
CPU time 17.12 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:12:11 PM PDT 23
Peak memory 211664 kb
Host smart-29c9b246-6612-40d0-845f-97e7e5977b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807484598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2807484598
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.113269722
Short name T287
Test name
Test status
Simulation time 1811794281 ps
CPU time 15.93 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:12:04 PM PDT 23
Peak memory 211216 kb
Host smart-e876daba-e60d-43e9-84ef-fcd1f0c62f4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113269722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.113269722
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1727088192
Short name T53
Test name
Test status
Simulation time 380834607 ps
CPU time 10.29 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:02 PM PDT 23
Peak memory 212872 kb
Host smart-d3f4b9d5-0abd-4a0e-89dc-aeeef780f321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727088192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1727088192
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4165152339
Short name T341
Test name
Test status
Simulation time 12903935984 ps
CPU time 31.71 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:12:20 PM PDT 23
Peak memory 213404 kb
Host smart-e223cf56-ee1e-4eaa-b1f0-81c9afc46d4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165152339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4165152339
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2077500644
Short name T330
Test name
Test status
Simulation time 101712438017 ps
CPU time 1288.72 seconds
Started Sep 27 01:11:47 PM PDT 23
Finished Sep 27 01:33:16 PM PDT 23
Peak memory 235976 kb
Host smart-6c783612-33dc-4721-8b0a-52750c305827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077500644 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2077500644
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4057810817
Short name T406
Test name
Test status
Simulation time 89149377 ps
CPU time 4.46 seconds
Started Sep 27 01:11:55 PM PDT 23
Finished Sep 27 01:12:00 PM PDT 23
Peak memory 210996 kb
Host smart-d15ca27f-d94d-442c-a0db-c2294e9e0eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057810817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4057810817
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3923981408
Short name T235
Test name
Test status
Simulation time 283119682108 ps
CPU time 529.48 seconds
Started Sep 27 01:12:01 PM PDT 23
Finished Sep 27 01:20:51 PM PDT 23
Peak memory 213320 kb
Host smart-24c4dcd2-7a39-48fb-8465-f9f6ccafd0cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923981408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3923981408
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2189298003
Short name T171
Test name
Test status
Simulation time 10648881014 ps
CPU time 20.91 seconds
Started Sep 27 01:11:59 PM PDT 23
Finished Sep 27 01:12:21 PM PDT 23
Peak memory 212816 kb
Host smart-646e91fd-b748-4d00-856a-4167fde02f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189298003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2189298003
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2440501816
Short name T271
Test name
Test status
Simulation time 1772512378 ps
CPU time 11.05 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:03 PM PDT 23
Peak memory 211040 kb
Host smart-ed231a5c-db63-424c-9d95-bd754e81c0bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440501816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2440501816
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3651819474
Short name T412
Test name
Test status
Simulation time 3937150124 ps
CPU time 24.91 seconds
Started Sep 27 01:11:49 PM PDT 23
Finished Sep 27 01:12:14 PM PDT 23
Peak memory 213612 kb
Host smart-4fad3853-61de-4905-b59c-43f5bc452e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651819474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3651819474
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2750232093
Short name T221
Test name
Test status
Simulation time 34414681686 ps
CPU time 85.02 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:13:13 PM PDT 23
Peak memory 219296 kb
Host smart-1f16de19-7333-4ed5-9d91-b2e7d7c9e442
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750232093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2750232093
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.860348480
Short name T387
Test name
Test status
Simulation time 1859312216 ps
CPU time 15.29 seconds
Started Sep 27 01:11:54 PM PDT 23
Finished Sep 27 01:12:09 PM PDT 23
Peak memory 210984 kb
Host smart-43c7a421-9bff-422d-864e-db7a43588a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860348480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.860348480
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2256680035
Short name T382
Test name
Test status
Simulation time 16014136216 ps
CPU time 180.81 seconds
Started Sep 27 01:11:20 PM PDT 23
Finished Sep 27 01:14:21 PM PDT 23
Peak memory 228476 kb
Host smart-bfb84489-5851-456e-be8f-df8c5576a992
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256680035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2256680035
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1215961544
Short name T398
Test name
Test status
Simulation time 4065982617 ps
CPU time 32.09 seconds
Started Sep 27 01:11:14 PM PDT 23
Finished Sep 27 01:11:47 PM PDT 23
Peak memory 211760 kb
Host smart-f7bc4358-89ba-4200-b4d3-2548c484a09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215961544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1215961544
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.429509403
Short name T283
Test name
Test status
Simulation time 1634941825 ps
CPU time 14.43 seconds
Started Sep 27 01:12:04 PM PDT 23
Finished Sep 27 01:12:18 PM PDT 23
Peak memory 210948 kb
Host smart-4fef87ef-f9ec-44bb-bfe1-23979c816dc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429509403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.429509403
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.311193933
Short name T48
Test name
Test status
Simulation time 2328374290 ps
CPU time 122.68 seconds
Started Sep 27 01:11:54 PM PDT 23
Finished Sep 27 01:13:57 PM PDT 23
Peak memory 236308 kb
Host smart-7d437a38-a18f-48c5-8a05-0982e47533b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311193933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.311193933
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2481788928
Short name T202
Test name
Test status
Simulation time 2507261023 ps
CPU time 23.81 seconds
Started Sep 27 01:12:11 PM PDT 23
Finished Sep 27 01:12:35 PM PDT 23
Peak memory 212292 kb
Host smart-e0052ed8-404e-446d-9ad7-45ec8f8f5f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481788928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2481788928
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.292418529
Short name T380
Test name
Test status
Simulation time 387435023 ps
CPU time 22.12 seconds
Started Sep 27 01:11:51 PM PDT 23
Finished Sep 27 01:12:18 PM PDT 23
Peak memory 215884 kb
Host smart-4e63e60b-edf8-45ba-9094-fb89ea7b7143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292418529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.292418529
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3636002832
Short name T234
Test name
Test status
Simulation time 2483064049 ps
CPU time 8.42 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:12:02 PM PDT 23
Peak memory 211080 kb
Host smart-9a682739-c59d-4fe8-a9f9-fdafdb535217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636002832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3636002832
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1010982019
Short name T205
Test name
Test status
Simulation time 44989338462 ps
CPU time 224.15 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:15:33 PM PDT 23
Peak memory 212328 kb
Host smart-a229b233-a3a8-4235-b205-de5fdbfdd9f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010982019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1010982019
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.845585773
Short name T322
Test name
Test status
Simulation time 1811092683 ps
CPU time 16.1 seconds
Started Sep 27 01:12:06 PM PDT 23
Finished Sep 27 01:12:23 PM PDT 23
Peak memory 211064 kb
Host smart-860b821d-1f3f-46c1-873e-de65e4edc997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845585773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.845585773
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1741112872
Short name T157
Test name
Test status
Simulation time 3603029630 ps
CPU time 15.99 seconds
Started Sep 27 01:12:16 PM PDT 23
Finished Sep 27 01:12:32 PM PDT 23
Peak memory 211100 kb
Host smart-c49f9373-5e65-4a0a-84b2-74b154327acb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741112872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1741112872
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.956808411
Short name T335
Test name
Test status
Simulation time 958549381 ps
CPU time 10.32 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:03 PM PDT 23
Peak memory 212824 kb
Host smart-c72df6aa-e3e8-4276-aa93-72d7ed82bbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956808411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.956808411
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2922906683
Short name T415
Test name
Test status
Simulation time 134915233 ps
CPU time 6.65 seconds
Started Sep 27 01:11:58 PM PDT 23
Finished Sep 27 01:12:05 PM PDT 23
Peak memory 210980 kb
Host smart-5f42e2eb-e57b-44bb-84ea-16f135acb8c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922906683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2922906683
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3765643256
Short name T15
Test name
Test status
Simulation time 24358300441 ps
CPU time 1444.08 seconds
Started Sep 27 01:11:55 PM PDT 23
Finished Sep 27 01:35:59 PM PDT 23
Peak memory 235492 kb
Host smart-8750caf3-ecd8-4476-abad-f29df32a8c4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765643256 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3765643256
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3807206787
Short name T246
Test name
Test status
Simulation time 1005099359 ps
CPU time 10.56 seconds
Started Sep 27 01:12:05 PM PDT 23
Finished Sep 27 01:12:16 PM PDT 23
Peak memory 211088 kb
Host smart-06ccf685-9c3b-476a-b866-446c3752e8ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807206787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3807206787
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1235046553
Short name T388
Test name
Test status
Simulation time 237727465103 ps
CPU time 439.6 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:19:13 PM PDT 23
Peak memory 224412 kb
Host smart-ab195ade-4463-46fa-85e7-c80af9a99171
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235046553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1235046553
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2160323837
Short name T365
Test name
Test status
Simulation time 1509887797 ps
CPU time 18.87 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:12:12 PM PDT 23
Peak memory 211196 kb
Host smart-19da12ff-3f6f-4cb1-9aef-fbf17dd38899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160323837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2160323837
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.207064007
Short name T18
Test name
Test status
Simulation time 3998534259 ps
CPU time 17.04 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:09 PM PDT 23
Peak memory 211076 kb
Host smart-e0e78bc5-edaf-43ec-93d2-3f8a927b2a19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=207064007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.207064007
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3650344504
Short name T425
Test name
Test status
Simulation time 3842329305 ps
CPU time 32.52 seconds
Started Sep 27 01:11:59 PM PDT 23
Finished Sep 27 01:12:32 PM PDT 23
Peak memory 212960 kb
Host smart-bbf94d52-6cfc-4615-ac48-a70433e7350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650344504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3650344504
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3899094255
Short name T394
Test name
Test status
Simulation time 5861122011 ps
CPU time 66.51 seconds
Started Sep 27 01:12:08 PM PDT 23
Finished Sep 27 01:13:14 PM PDT 23
Peak memory 216416 kb
Host smart-13ef1384-c33c-4ee5-8c8f-36a00228a37a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899094255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3899094255
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3588336517
Short name T51
Test name
Test status
Simulation time 8582631920 ps
CPU time 16.56 seconds
Started Sep 27 01:12:14 PM PDT 23
Finished Sep 27 01:12:30 PM PDT 23
Peak memory 211120 kb
Host smart-f37c0310-cd84-439d-9506-d5a8093a14ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588336517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3588336517
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.550345402
Short name T59
Test name
Test status
Simulation time 20465738949 ps
CPU time 207.03 seconds
Started Sep 27 01:12:06 PM PDT 23
Finished Sep 27 01:15:33 PM PDT 23
Peak memory 236708 kb
Host smart-b7c91dd6-8ed9-4cdc-a727-e96095994f82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550345402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.550345402
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1134281219
Short name T174
Test name
Test status
Simulation time 13735272049 ps
CPU time 30.21 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:23 PM PDT 23
Peak memory 215544 kb
Host smart-4f711895-7b40-46bd-baab-a3c13ca2a29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134281219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1134281219
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1956359841
Short name T240
Test name
Test status
Simulation time 9044429206 ps
CPU time 13.56 seconds
Started Sep 27 01:11:50 PM PDT 23
Finished Sep 27 01:12:04 PM PDT 23
Peak memory 211036 kb
Host smart-d0195483-7f00-4512-804c-f89598db7f62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956359841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1956359841
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.894480776
Short name T317
Test name
Test status
Simulation time 28755430039 ps
CPU time 32.87 seconds
Started Sep 27 01:12:06 PM PDT 23
Finished Sep 27 01:12:39 PM PDT 23
Peak memory 214016 kb
Host smart-60b4e5fc-659a-417e-9c1e-872ac3d3e527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894480776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.894480776
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.110930137
Short name T374
Test name
Test status
Simulation time 16729447248 ps
CPU time 50.33 seconds
Started Sep 27 01:11:54 PM PDT 23
Finished Sep 27 01:12:44 PM PDT 23
Peak memory 217172 kb
Host smart-936ef84d-4fe3-4bd4-85cb-2190a84b0fb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110930137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.110930137
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.933889590
Short name T11
Test name
Test status
Simulation time 67647924127 ps
CPU time 1369.9 seconds
Started Sep 27 01:11:48 PM PDT 23
Finished Sep 27 01:34:38 PM PDT 23
Peak memory 238128 kb
Host smart-15f04b89-1842-42bc-b484-d13f48749b9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933889590 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.933889590
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3687804687
Short name T228
Test name
Test status
Simulation time 4769142510 ps
CPU time 8.17 seconds
Started Sep 27 01:11:55 PM PDT 23
Finished Sep 27 01:12:04 PM PDT 23
Peak memory 211084 kb
Host smart-50888783-06e4-4835-a010-7a7e4abdc899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687804687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3687804687
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1818897386
Short name T60
Test name
Test status
Simulation time 189385378826 ps
CPU time 351.39 seconds
Started Sep 27 01:11:58 PM PDT 23
Finished Sep 27 01:17:49 PM PDT 23
Peak memory 224488 kb
Host smart-66fd04f7-41d9-4b50-9c13-626d4741ff0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818897386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1818897386
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2650491004
Short name T33
Test name
Test status
Simulation time 177327151 ps
CPU time 9.59 seconds
Started Sep 27 01:11:51 PM PDT 23
Finished Sep 27 01:12:00 PM PDT 23
Peak memory 211240 kb
Host smart-e8945709-3bf6-43ba-ad62-9455dfd7dcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650491004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2650491004
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1886843014
Short name T225
Test name
Test status
Simulation time 95826621 ps
CPU time 5.42 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:11:59 PM PDT 23
Peak memory 210952 kb
Host smart-19977f54-7d77-4543-a9c9-a2a8204ba5d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886843014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1886843014
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.341639642
Short name T402
Test name
Test status
Simulation time 18729687648 ps
CPU time 26.6 seconds
Started Sep 27 01:11:50 PM PDT 23
Finished Sep 27 01:12:17 PM PDT 23
Peak memory 213644 kb
Host smart-87e1112c-99d0-4a44-a4cd-19f122e3e354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341639642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.341639642
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2699991748
Short name T344
Test name
Test status
Simulation time 1091290432 ps
CPU time 12.01 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:05 PM PDT 23
Peak memory 211092 kb
Host smart-5a300e8c-ba5e-4e7b-a3e5-69a70364d0e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699991748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2699991748
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2456867223
Short name T416
Test name
Test status
Simulation time 1064445347 ps
CPU time 10.41 seconds
Started Sep 27 01:11:58 PM PDT 23
Finished Sep 27 01:12:08 PM PDT 23
Peak memory 210976 kb
Host smart-da2c16dc-129e-460a-8d08-c494ebaf5585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456867223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2456867223
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4245644124
Short name T324
Test name
Test status
Simulation time 1250423778 ps
CPU time 71.55 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:13:04 PM PDT 23
Peak memory 227836 kb
Host smart-e4e9cea0-e6e0-43e9-8053-7f7f669b43a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245644124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.4245644124
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2112302951
Short name T291
Test name
Test status
Simulation time 3621975697 ps
CPU time 30.55 seconds
Started Sep 27 01:12:08 PM PDT 23
Finished Sep 27 01:12:39 PM PDT 23
Peak memory 211176 kb
Host smart-32700aba-71f7-4efb-9450-0f8196ec4118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112302951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2112302951
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.839720534
Short name T304
Test name
Test status
Simulation time 1858418211 ps
CPU time 11.34 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:04 PM PDT 23
Peak memory 210944 kb
Host smart-ed261994-252c-492f-a82e-37b56342c1ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839720534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.839720534
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3611670821
Short name T206
Test name
Test status
Simulation time 182704621 ps
CPU time 10.06 seconds
Started Sep 27 01:12:05 PM PDT 23
Finished Sep 27 01:12:15 PM PDT 23
Peak memory 212416 kb
Host smart-1dd0a9ad-6ec3-42c0-8b8f-56daa4fa69e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611670821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3611670821
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.341491670
Short name T372
Test name
Test status
Simulation time 19386481620 ps
CPU time 38.84 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:31 PM PDT 23
Peak memory 216540 kb
Host smart-87e4e424-60eb-4f8c-a4f4-4db4bbbe1248
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341491670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.341491670
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2220099248
Short name T310
Test name
Test status
Simulation time 4983629160 ps
CPU time 11.37 seconds
Started Sep 27 01:12:15 PM PDT 23
Finished Sep 27 01:12:26 PM PDT 23
Peak memory 211132 kb
Host smart-938e5968-b0f3-4aaa-b976-60fa40c3d448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220099248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2220099248
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3273241762
Short name T270
Test name
Test status
Simulation time 120197283157 ps
CPU time 185.86 seconds
Started Sep 27 01:12:16 PM PDT 23
Finished Sep 27 01:15:22 PM PDT 23
Peak memory 237784 kb
Host smart-e9feec79-139e-4e28-8755-36b552357040
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273241762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3273241762
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3000395902
Short name T32
Test name
Test status
Simulation time 922763208 ps
CPU time 9.75 seconds
Started Sep 27 01:11:56 PM PDT 23
Finished Sep 27 01:12:06 PM PDT 23
Peak memory 211048 kb
Host smart-ad0c2381-1aa0-4a53-a94f-d500cad7956d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000395902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3000395902
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1778804434
Short name T423
Test name
Test status
Simulation time 1137131760 ps
CPU time 5.53 seconds
Started Sep 27 01:12:13 PM PDT 23
Finished Sep 27 01:12:19 PM PDT 23
Peak memory 211020 kb
Host smart-acd274fa-d422-428f-8222-8a76798a1569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1778804434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1778804434
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3061277566
Short name T222
Test name
Test status
Simulation time 3199575075 ps
CPU time 19.15 seconds
Started Sep 27 01:12:09 PM PDT 23
Finished Sep 27 01:12:28 PM PDT 23
Peak memory 212596 kb
Host smart-41111b03-9cd8-4d78-8c3e-38bfc6d58987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061277566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3061277566
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1584918676
Short name T183
Test name
Test status
Simulation time 3790475976 ps
CPU time 35.73 seconds
Started Sep 27 01:12:15 PM PDT 23
Finished Sep 27 01:12:51 PM PDT 23
Peak memory 212808 kb
Host smart-14ac1367-108d-46fe-9e83-01b1d3bd9eca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584918676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1584918676
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3680020237
Short name T155
Test name
Test status
Simulation time 90097349 ps
CPU time 4.39 seconds
Started Sep 27 01:12:14 PM PDT 23
Finished Sep 27 01:12:19 PM PDT 23
Peak memory 211060 kb
Host smart-016052c8-9655-427d-9ae2-9749747a3c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680020237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3680020237
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2504176705
Short name T397
Test name
Test status
Simulation time 246475553644 ps
CPU time 215.88 seconds
Started Sep 27 01:12:11 PM PDT 23
Finished Sep 27 01:15:48 PM PDT 23
Peak memory 237432 kb
Host smart-c8fc0b00-cd93-4b17-be34-d116954c17fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504176705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2504176705
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.692320536
Short name T184
Test name
Test status
Simulation time 17058127420 ps
CPU time 33.85 seconds
Started Sep 27 01:11:54 PM PDT 23
Finished Sep 27 01:12:28 PM PDT 23
Peak memory 211384 kb
Host smart-8f45ee57-998f-4ee6-9fae-c396f1bf29cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692320536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.692320536
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1406453356
Short name T244
Test name
Test status
Simulation time 635940754 ps
CPU time 5.39 seconds
Started Sep 27 01:11:58 PM PDT 23
Finished Sep 27 01:12:03 PM PDT 23
Peak memory 210980 kb
Host smart-095a6e12-f32f-470c-8811-fe6bcd4d5fdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406453356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1406453356
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2121374551
Short name T381
Test name
Test status
Simulation time 9919708944 ps
CPU time 26.13 seconds
Started Sep 27 01:12:15 PM PDT 23
Finished Sep 27 01:12:41 PM PDT 23
Peak memory 213080 kb
Host smart-dc00c843-ea79-4ea1-994b-eaa42dc63bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121374551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2121374551
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3860905796
Short name T280
Test name
Test status
Simulation time 5880116201 ps
CPU time 32.98 seconds
Started Sep 27 01:12:12 PM PDT 23
Finished Sep 27 01:12:45 PM PDT 23
Peak memory 213880 kb
Host smart-28fc0447-9df9-4b2f-a4e1-eca00fcc8da3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860905796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3860905796
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2102657335
Short name T391
Test name
Test status
Simulation time 354316543202 ps
CPU time 3697.04 seconds
Started Sep 27 01:11:50 PM PDT 23
Finished Sep 27 02:13:28 PM PDT 23
Peak memory 248940 kb
Host smart-68b91df9-6a47-4fe3-808b-b28f073875c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102657335 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2102657335
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1509334879
Short name T10
Test name
Test status
Simulation time 26482176391 ps
CPU time 17.61 seconds
Started Sep 27 01:12:12 PM PDT 23
Finished Sep 27 01:12:30 PM PDT 23
Peak memory 211084 kb
Host smart-1a510eff-8a8a-4536-8def-2b56844869c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509334879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1509334879
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3805454023
Short name T57
Test name
Test status
Simulation time 20913403772 ps
CPU time 211.28 seconds
Started Sep 27 01:11:57 PM PDT 23
Finished Sep 27 01:15:29 PM PDT 23
Peak memory 234612 kb
Host smart-b595834a-ee68-457f-a8c8-02e5d0f79a55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805454023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3805454023
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3395096818
Short name T201
Test name
Test status
Simulation time 6792572165 ps
CPU time 19.35 seconds
Started Sep 27 01:12:15 PM PDT 23
Finished Sep 27 01:12:34 PM PDT 23
Peak memory 213384 kb
Host smart-e4763d37-bb1a-4328-afa5-47f704040b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395096818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3395096818
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.377014172
Short name T343
Test name
Test status
Simulation time 190433861 ps
CPU time 5.45 seconds
Started Sep 27 01:12:15 PM PDT 23
Finished Sep 27 01:12:21 PM PDT 23
Peak memory 211176 kb
Host smart-81e41425-8033-4917-9902-3a9c6ee6bb7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377014172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.377014172
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3673197668
Short name T107
Test name
Test status
Simulation time 5968700362 ps
CPU time 29.01 seconds
Started Sep 27 01:12:16 PM PDT 23
Finished Sep 27 01:12:45 PM PDT 23
Peak memory 213564 kb
Host smart-0bec0797-599d-40b8-9287-be97bf38deb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673197668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3673197668
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1332694693
Short name T261
Test name
Test status
Simulation time 36676041416 ps
CPU time 42.52 seconds
Started Sep 27 01:12:12 PM PDT 23
Finished Sep 27 01:12:54 PM PDT 23
Peak memory 213692 kb
Host smart-019ff2a9-b8e8-467f-a9b9-477716daec2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332694693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1332694693
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1464620549
Short name T164
Test name
Test status
Simulation time 1362008421 ps
CPU time 6.59 seconds
Started Sep 27 01:12:00 PM PDT 23
Finished Sep 27 01:12:07 PM PDT 23
Peak memory 210976 kb
Host smart-a5402351-654b-48d7-8f1b-7355ac2ea434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464620549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1464620549
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4009171639
Short name T233
Test name
Test status
Simulation time 23044239569 ps
CPU time 261.36 seconds
Started Sep 27 01:11:55 PM PDT 23
Finished Sep 27 01:16:17 PM PDT 23
Peak memory 234752 kb
Host smart-8c6e26d0-0804-4649-b078-f7e70d3ca315
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009171639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.4009171639
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.318540898
Short name T248
Test name
Test status
Simulation time 692404328 ps
CPU time 9.65 seconds
Started Sep 27 01:12:13 PM PDT 23
Finished Sep 27 01:12:23 PM PDT 23
Peak memory 211192 kb
Host smart-90837ddf-4fe2-42f2-8355-5f5294381873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318540898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.318540898
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2197075931
Short name T328
Test name
Test status
Simulation time 1888018051 ps
CPU time 16.47 seconds
Started Sep 27 01:12:15 PM PDT 23
Finished Sep 27 01:12:31 PM PDT 23
Peak memory 211016 kb
Host smart-d7dde94d-0c4d-4e55-98c1-aaf85a08732f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2197075931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2197075931
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1359225774
Short name T172
Test name
Test status
Simulation time 618956415 ps
CPU time 14.47 seconds
Started Sep 27 01:11:59 PM PDT 23
Finished Sep 27 01:12:14 PM PDT 23
Peak memory 213076 kb
Host smart-7aec653e-0213-4d3c-a21d-23d360255444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359225774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1359225774
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4176915197
Short name T339
Test name
Test status
Simulation time 28313598699 ps
CPU time 60.61 seconds
Started Sep 27 01:11:59 PM PDT 23
Finished Sep 27 01:13:00 PM PDT 23
Peak memory 219288 kb
Host smart-64e7cf71-f9c7-44b1-95c5-cd12072dc3e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176915197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4176915197
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.637494563
Short name T321
Test name
Test status
Simulation time 17984318803 ps
CPU time 2178.59 seconds
Started Sep 27 01:11:55 PM PDT 23
Finished Sep 27 01:48:14 PM PDT 23
Peak memory 232232 kb
Host smart-3e3bac9e-771e-482f-bf55-f5ab9287c1d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637494563 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.637494563
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.236990659
Short name T313
Test name
Test status
Simulation time 6318218436 ps
CPU time 13.39 seconds
Started Sep 27 01:12:28 PM PDT 23
Finished Sep 27 01:12:42 PM PDT 23
Peak memory 211148 kb
Host smart-6311db31-c2ab-4110-8bb4-fb7a3dc5b14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236990659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.236990659
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.383255426
Short name T275
Test name
Test status
Simulation time 3590705602 ps
CPU time 127.23 seconds
Started Sep 27 01:12:01 PM PDT 23
Finished Sep 27 01:14:09 PM PDT 23
Peak memory 236816 kb
Host smart-1141590b-c549-4322-a2c4-51f051dd3828
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383255426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.383255426
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2679478489
Short name T223
Test name
Test status
Simulation time 7825090394 ps
CPU time 21.27 seconds
Started Sep 27 01:11:56 PM PDT 23
Finished Sep 27 01:12:18 PM PDT 23
Peak memory 211396 kb
Host smart-9ef93329-4757-467c-87c8-2df4bd434a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679478489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2679478489
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1730849212
Short name T331
Test name
Test status
Simulation time 6900623095 ps
CPU time 14.56 seconds
Started Sep 27 01:12:06 PM PDT 23
Finished Sep 27 01:12:20 PM PDT 23
Peak memory 211056 kb
Host smart-9d91a831-41b1-4214-aa29-a6199bcb9d61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730849212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1730849212
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2036332363
Short name T262
Test name
Test status
Simulation time 15142849449 ps
CPU time 31.34 seconds
Started Sep 27 01:12:12 PM PDT 23
Finished Sep 27 01:12:43 PM PDT 23
Peak memory 213696 kb
Host smart-d9430767-809d-4760-9d20-d3e889807f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036332363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2036332363
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.34694401
Short name T357
Test name
Test status
Simulation time 1575064488 ps
CPU time 23.71 seconds
Started Sep 27 01:12:01 PM PDT 23
Finished Sep 27 01:12:25 PM PDT 23
Peak memory 215512 kb
Host smart-a483a505-7c5a-419c-b0b4-fe2a4ddb8bfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34694401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 49.rom_ctrl_stress_all.34694401
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1824617664
Short name T112
Test name
Test status
Simulation time 65286316222 ps
CPU time 2495.01 seconds
Started Sep 27 01:12:36 PM PDT 23
Finished Sep 27 01:54:11 PM PDT 23
Peak memory 244000 kb
Host smart-825e7c0e-cf86-46ea-a311-ac022488ed74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824617664 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1824617664
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1083994984
Short name T226
Test name
Test status
Simulation time 377931725 ps
CPU time 4.48 seconds
Started Sep 27 01:11:17 PM PDT 23
Finished Sep 27 01:11:22 PM PDT 23
Peak memory 211012 kb
Host smart-c072774c-87c9-4efd-9368-c438038965a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083994984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1083994984
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1739256209
Short name T277
Test name
Test status
Simulation time 328299767823 ps
CPU time 246.61 seconds
Started Sep 27 01:11:21 PM PDT 23
Finished Sep 27 01:15:28 PM PDT 23
Peak memory 237788 kb
Host smart-4a6ef7fd-080c-4a08-8bf3-8d6eecb9214c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739256209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1739256209
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1270724191
Short name T377
Test name
Test status
Simulation time 940480625 ps
CPU time 15.93 seconds
Started Sep 27 01:11:21 PM PDT 23
Finished Sep 27 01:11:37 PM PDT 23
Peak memory 211196 kb
Host smart-655ac7cd-e647-401d-9e4e-0a66d3c294a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270724191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1270724191
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1759025999
Short name T220
Test name
Test status
Simulation time 1844511644 ps
CPU time 15.47 seconds
Started Sep 27 01:11:19 PM PDT 23
Finished Sep 27 01:11:35 PM PDT 23
Peak memory 211080 kb
Host smart-300423c2-f5f6-4f71-b3fa-fb471fb642bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1759025999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1759025999
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.23912298
Short name T349
Test name
Test status
Simulation time 16401956448 ps
CPU time 29.31 seconds
Started Sep 27 01:12:01 PM PDT 23
Finished Sep 27 01:12:31 PM PDT 23
Peak memory 212988 kb
Host smart-f89d6f12-02c2-4f24-98ac-849596da4074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23912298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.23912298
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3720084862
Short name T375
Test name
Test status
Simulation time 40359239958 ps
CPU time 82.16 seconds
Started Sep 27 01:12:16 PM PDT 23
Finished Sep 27 01:13:39 PM PDT 23
Peak memory 219312 kb
Host smart-5d4b91d4-594b-4a59-926c-bf390175a05f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720084862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3720084862
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.4219609057
Short name T13
Test name
Test status
Simulation time 135327789515 ps
CPU time 1182.47 seconds
Started Sep 27 01:12:18 PM PDT 23
Finished Sep 27 01:32:01 PM PDT 23
Peak memory 235752 kb
Host smart-9a0109c8-3d4d-46d2-9920-6df4a7b3e879
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219609057 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.4219609057
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1165979015
Short name T229
Test name
Test status
Simulation time 3596730700 ps
CPU time 9.63 seconds
Started Sep 27 01:11:15 PM PDT 23
Finished Sep 27 01:11:25 PM PDT 23
Peak memory 211164 kb
Host smart-c0194adf-1a62-492d-b7c8-fb72890ee50a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165979015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1165979015
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3318976755
Short name T50
Test name
Test status
Simulation time 187983697199 ps
CPU time 231.4 seconds
Started Sep 27 01:11:17 PM PDT 23
Finished Sep 27 01:15:09 PM PDT 23
Peak memory 237772 kb
Host smart-d3e813aa-f8b8-4863-ac0b-320b0bc71f33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318976755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3318976755
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.16335597
Short name T211
Test name
Test status
Simulation time 363966905 ps
CPU time 9.53 seconds
Started Sep 27 01:31:13 PM PDT 23
Finished Sep 27 01:31:23 PM PDT 23
Peak memory 211400 kb
Host smart-7aa673c8-b0c1-43f7-aea1-26e5fa054896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16335597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.16335597
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4100687831
Short name T191
Test name
Test status
Simulation time 8394439568 ps
CPU time 14.65 seconds
Started Sep 27 01:11:49 PM PDT 23
Finished Sep 27 01:12:04 PM PDT 23
Peak memory 211076 kb
Host smart-43a54738-b4b2-4b9c-bddf-1130652ffaf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4100687831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4100687831
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.90264911
Short name T282
Test name
Test status
Simulation time 7876928558 ps
CPU time 21.65 seconds
Started Sep 27 01:11:52 PM PDT 23
Finished Sep 27 01:12:15 PM PDT 23
Peak memory 212080 kb
Host smart-5844dee0-4051-4f41-8319-54353c24fe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90264911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.90264911
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2045111876
Short name T254
Test name
Test status
Simulation time 474507139 ps
CPU time 30.78 seconds
Started Sep 27 01:11:53 PM PDT 23
Finished Sep 27 01:12:24 PM PDT 23
Peak memory 215132 kb
Host smart-627cb655-790d-49d7-b5bc-ed184e358160
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045111876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2045111876
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2053128747
Short name T383
Test name
Test status
Simulation time 132750506305 ps
CPU time 2568.56 seconds
Started Sep 27 01:11:17 PM PDT 23
Finished Sep 27 01:54:06 PM PDT 23
Peak memory 235772 kb
Host smart-2d395113-1732-4aba-af17-2e37e3003828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053128747 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2053128747
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1637197031
Short name T154
Test name
Test status
Simulation time 347447374 ps
CPU time 4.15 seconds
Started Sep 27 01:11:15 PM PDT 23
Finished Sep 27 01:11:19 PM PDT 23
Peak memory 211020 kb
Host smart-9415b1de-21ad-4f27-9804-5ec51d7d1d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637197031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1637197031
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.922795414
Short name T300
Test name
Test status
Simulation time 146682055678 ps
CPU time 315.01 seconds
Started Sep 27 01:17:38 PM PDT 23
Finished Sep 27 01:22:53 PM PDT 23
Peak memory 212360 kb
Host smart-c817a862-c4bf-46ea-9c16-515d22f926e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922795414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.922795414
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3828641334
Short name T56
Test name
Test status
Simulation time 10626581575 ps
CPU time 26.13 seconds
Started Sep 27 01:11:15 PM PDT 23
Finished Sep 27 01:11:41 PM PDT 23
Peak memory 211480 kb
Host smart-e39da034-dd38-4267-9c58-91a7ab271b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828641334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3828641334
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.503413509
Short name T353
Test name
Test status
Simulation time 6439884399 ps
CPU time 15.11 seconds
Started Sep 27 01:11:19 PM PDT 23
Finished Sep 27 01:11:34 PM PDT 23
Peak memory 211176 kb
Host smart-447c3a0f-6a2a-490f-a9d1-93732f22ae5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503413509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.503413509
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2843396885
Short name T186
Test name
Test status
Simulation time 373501464 ps
CPU time 10.39 seconds
Started Sep 27 01:11:17 PM PDT 23
Finished Sep 27 01:11:27 PM PDT 23
Peak memory 212276 kb
Host smart-61061617-1d7d-428b-b3ea-6b70cd96fc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843396885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2843396885
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4201948543
Short name T274
Test name
Test status
Simulation time 3357900938 ps
CPU time 10.91 seconds
Started Sep 27 01:19:40 PM PDT 23
Finished Sep 27 01:19:51 PM PDT 23
Peak memory 211808 kb
Host smart-88bc40b5-5928-423e-a191-f24d39386d00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201948543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4201948543
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3808743422
Short name T49
Test name
Test status
Simulation time 168649741 ps
CPU time 4.33 seconds
Started Sep 27 01:21:12 PM PDT 23
Finished Sep 27 01:21:17 PM PDT 23
Peak memory 210936 kb
Host smart-78586dbe-d3ee-49c5-be9b-8f33966a1fbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808743422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3808743422
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.860408014
Short name T61
Test name
Test status
Simulation time 26945751599 ps
CPU time 292.29 seconds
Started Sep 27 01:18:27 PM PDT 23
Finished Sep 27 01:23:20 PM PDT 23
Peak memory 233872 kb
Host smart-93397cf6-0396-49a8-99af-e63fdd2e5ef7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860408014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.860408014
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.350474389
Short name T309
Test name
Test status
Simulation time 15101404329 ps
CPU time 26.87 seconds
Started Sep 27 01:12:03 PM PDT 23
Finished Sep 27 01:12:30 PM PDT 23
Peak memory 211616 kb
Host smart-3adbca2a-d5bf-4452-a76d-1da208e39634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350474389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.350474389
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.172137842
Short name T242
Test name
Test status
Simulation time 1990759591 ps
CPU time 11.69 seconds
Started Sep 27 01:13:05 PM PDT 23
Finished Sep 27 01:13:17 PM PDT 23
Peak memory 210984 kb
Host smart-6fb77941-11f9-49c7-bcb4-21938020f6e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172137842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.172137842
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.144931528
Short name T418
Test name
Test status
Simulation time 1686018448 ps
CPU time 13.13 seconds
Started Sep 27 01:20:40 PM PDT 23
Finished Sep 27 01:20:53 PM PDT 23
Peak memory 212756 kb
Host smart-286cc2f0-4491-4f1b-b31f-4dc703c12d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144931528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.144931528
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1916328373
Short name T178
Test name
Test status
Simulation time 12395639572 ps
CPU time 42.33 seconds
Started Sep 27 01:19:56 PM PDT 23
Finished Sep 27 01:20:39 PM PDT 23
Peak memory 214028 kb
Host smart-252b6501-7998-459f-a7c0-336aea1cddef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916328373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1916328373
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.133625189
Short name T194
Test name
Test status
Simulation time 74478823795 ps
CPU time 9305.93 seconds
Started Sep 27 01:11:15 PM PDT 23
Finished Sep 27 03:46:22 PM PDT 23
Peak memory 243132 kb
Host smart-d4217c8f-b829-4bd2-8c48-45245557a77c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133625189 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.133625189
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3766480958
Short name T263
Test name
Test status
Simulation time 1429965828 ps
CPU time 9.04 seconds
Started Sep 27 01:14:07 PM PDT 23
Finished Sep 27 01:14:17 PM PDT 23
Peak memory 211076 kb
Host smart-1c8f926a-117d-410b-9618-4cbd188457e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766480958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3766480958
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4126313375
Short name T251
Test name
Test status
Simulation time 136625825892 ps
CPU time 191.22 seconds
Started Sep 27 01:11:15 PM PDT 23
Finished Sep 27 01:14:26 PM PDT 23
Peak memory 212372 kb
Host smart-6485ca75-f45a-4b5f-90f8-75217bd8c073
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126313375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4126313375
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2028863385
Short name T359
Test name
Test status
Simulation time 2480279224 ps
CPU time 13.05 seconds
Started Sep 27 01:12:16 PM PDT 23
Finished Sep 27 01:12:30 PM PDT 23
Peak memory 211288 kb
Host smart-d226a4e9-de60-4394-b78c-178b87889f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028863385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2028863385
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1869064902
Short name T185
Test name
Test status
Simulation time 7712645527 ps
CPU time 16.07 seconds
Started Sep 27 01:19:47 PM PDT 23
Finished Sep 27 01:20:03 PM PDT 23
Peak memory 211168 kb
Host smart-c28915e1-3037-4072-811e-42b42d01d17d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1869064902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1869064902
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3181013732
Short name T180
Test name
Test status
Simulation time 14788162252 ps
CPU time 30.32 seconds
Started Sep 27 01:11:21 PM PDT 23
Finished Sep 27 01:11:51 PM PDT 23
Peak memory 213372 kb
Host smart-15660edf-8f17-49f2-b885-3f82d45c50c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181013732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3181013732
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2692556687
Short name T247
Test name
Test status
Simulation time 300080724 ps
CPU time 17.24 seconds
Started Sep 27 01:19:53 PM PDT 23
Finished Sep 27 01:20:11 PM PDT 23
Peak memory 215588 kb
Host smart-df497298-b5fc-49c5-8664-64a7b12c8f0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692556687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2692556687
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2381645858
Short name T224
Test name
Test status
Simulation time 35954656191 ps
CPU time 354.64 seconds
Started Sep 27 01:11:17 PM PDT 23
Finished Sep 27 01:17:12 PM PDT 23
Peak memory 231060 kb
Host smart-c8178a85-df24-4e57-adf5-8f93062c7d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381645858 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2381645858
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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