ROM_CTRL Simulation Results

Wednesday September 27 2023 19:02:42 UTC

GitHub Revision: `38769a5e7`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2962962794

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	36.830s	8.173ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	12.930s	1.179ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.920s	2.123ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	17.700s	2.215ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.870s	8.815ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.720s	8.915ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.920s	2.123ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.870s	8.815ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.500s	9.958ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.660s	2.026ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.370s	2.159ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.999m	46.348ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.610s	18.287ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	17.610s	26.482ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.800s	2.070ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.800s	2.070ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	12.930s	1.179ms	5	5	100.00
		rom_ctrl_csr_rw	16.920s	2.123ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.870s	8.815ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	19.150s	2.235ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	12.930s	1.179ms	5	5	100.00
		rom_ctrl_csr_rw	16.920s	2.123ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.870s	8.815ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	19.150s	2.235ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.825m	283.120ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	6.318m	37.941ms	18	20	90.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.045m	2.328ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.481m	4.377ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.045m	2.328ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.825m	283.120ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.825m	283.120ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.825m	283.120ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.825m	283.120ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.825m	283.120ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.045m	2.328ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.045m	2.328ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	36.830s	8.173ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	36.830s	8.173ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	36.830s	8.173ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.481m	4.377ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.825m	283.120ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.610s	18.287ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.825m	283.120ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.825m	283.120ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.825m	283.120ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	6.318m	37.941ms	18	20	90.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.045m	2.328ms	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.870h	241.858ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			480	500	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.68	97.11	93.27	97.88	100.00	99.02	97.89	98.61

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 13 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.923879338
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:6f70b56b-a69e-4b5b-8eb6-c3f30aba4546
```
  - 2.rom_ctrl_stress_all_with_rand_reset.3256769033
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:95a09e3c-bb5b-48f3-a3a2-1acf66d596f3
```
  - ... and 11 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 5 failures:

Test rom_ctrl_stress_all_with_rand_reset has 3 failures.

0.rom_ctrl_stress_all_with_rand_reset.3370449938
Line 216, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 14900209225 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x570428db
  UVM_INFO @ 14900209225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.rom_ctrl_stress_all_with_rand_reset.2016507023
Line 211, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 11063381426 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x7cfeffe9
  UVM_INFO @ 11063381426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rom_ctrl_passthru_mem_tl_intg_err has 2 failures.

15.rom_ctrl_passthru_mem_tl_intg_err.791323287
Line 207, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @ 10019049642 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x30a8004
  UVM_INFO @ 10019049642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.rom_ctrl_passthru_mem_tl_intg_err.1600754619
Line 207, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @ 10015143452 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x4e7a000c
  UVM_INFO @ 10015143452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 37.rom_ctrl_kmac_err_chk.2712294754
    Line 206, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/37.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 3313724566 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3313724566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 45.rom_ctrl_stress_all_with_rand_reset.3176337745
    Line 328, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 158481095830 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 158481095830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```