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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.67 97.11 93.12 97.88 100.00 98.69 98.04 98.84


Total test records in report: 484
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T276 /workspace/coverage/default/38.rom_ctrl_alert_test.248524423 Oct 01 12:31:39 PM PDT 23 Oct 01 12:31:44 PM PDT 23 334195558 ps
T277 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.237744748 Oct 01 12:20:22 PM PDT 23 Oct 01 12:21:59 PM PDT 23 7752656723 ps
T278 /workspace/coverage/default/4.rom_ctrl_stress_all.399982273 Oct 01 12:18:40 PM PDT 23 Oct 01 12:18:52 PM PDT 23 4729035014 ps
T279 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2723318841 Oct 01 12:31:46 PM PDT 23 Oct 01 12:43:41 PM PDT 23 68627195696 ps
T280 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3577669711 Oct 01 12:31:31 PM PDT 23 Oct 01 12:31:44 PM PDT 23 1632274996 ps
T281 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3799605336 Oct 01 12:30:53 PM PDT 23 Oct 01 01:58:12 PM PDT 23 436518593370 ps
T38 /workspace/coverage/default/1.rom_ctrl_sec_cm.2199609672 Oct 01 12:15:03 PM PDT 23 Oct 01 12:16:07 PM PDT 23 4519926163 ps
T282 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3950402434 Oct 01 12:31:07 PM PDT 23 Oct 01 01:41:12 PM PDT 23 162670597810 ps
T283 /workspace/coverage/default/6.rom_ctrl_stress_all.1394842439 Oct 01 12:22:51 PM PDT 23 Oct 01 12:23:16 PM PDT 23 3360473326 ps
T284 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3445745715 Oct 01 12:15:19 PM PDT 23 Oct 01 12:17:27 PM PDT 23 41536880753 ps
T285 /workspace/coverage/default/44.rom_ctrl_alert_test.1766620933 Oct 01 12:31:39 PM PDT 23 Oct 01 12:31:53 PM PDT 23 1600882547 ps
T286 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.734995706 Oct 01 12:31:11 PM PDT 23 Oct 01 12:31:28 PM PDT 23 13040419706 ps
T287 /workspace/coverage/default/8.rom_ctrl_stress_all.160517403 Oct 01 12:31:05 PM PDT 23 Oct 01 12:31:59 PM PDT 23 6409144619 ps
T288 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3849691308 Oct 01 12:17:29 PM PDT 23 Oct 01 12:18:32 PM PDT 23 2846237475 ps
T289 /workspace/coverage/default/39.rom_ctrl_smoke.2382407597 Oct 01 12:31:13 PM PDT 23 Oct 01 12:31:28 PM PDT 23 3014167994 ps
T290 /workspace/coverage/default/24.rom_ctrl_smoke.1501592186 Oct 01 12:31:03 PM PDT 23 Oct 01 12:31:34 PM PDT 23 3213021973 ps
T291 /workspace/coverage/default/27.rom_ctrl_stress_all.2744560614 Oct 01 12:31:11 PM PDT 23 Oct 01 12:32:54 PM PDT 23 79166457925 ps
T292 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2674098803 Oct 01 12:31:51 PM PDT 23 Oct 01 12:32:09 PM PDT 23 4522744350 ps
T293 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2366739858 Oct 01 12:31:34 PM PDT 23 Oct 01 12:33:27 PM PDT 23 4543005496 ps
T294 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3906195892 Oct 01 12:18:25 PM PDT 23 Oct 01 12:18:49 PM PDT 23 4758028436 ps
T295 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2213655893 Oct 01 12:30:47 PM PDT 23 Oct 01 12:31:18 PM PDT 23 7338359957 ps
T296 /workspace/coverage/default/43.rom_ctrl_smoke.2751789162 Oct 01 12:31:19 PM PDT 23 Oct 01 12:31:44 PM PDT 23 4135972992 ps
T297 /workspace/coverage/default/42.rom_ctrl_stress_all.2357721744 Oct 01 12:31:31 PM PDT 23 Oct 01 12:32:15 PM PDT 23 16437954600 ps
T298 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2700248901 Oct 01 12:31:33 PM PDT 23 Oct 01 12:58:34 PM PDT 23 186961704736 ps
T299 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.593932999 Oct 01 12:30:43 PM PDT 23 Oct 01 12:38:30 PM PDT 23 151926364789 ps
T300 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3354719785 Oct 01 12:31:43 PM PDT 23 Oct 01 12:32:17 PM PDT 23 14895959690 ps
T301 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.300364325 Oct 01 12:32:13 PM PDT 23 Oct 01 12:32:45 PM PDT 23 7382262818 ps
T302 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1002754523 Oct 01 12:31:57 PM PDT 23 Oct 01 12:34:16 PM PDT 23 28515807926 ps
T303 /workspace/coverage/default/33.rom_ctrl_alert_test.4058908908 Oct 01 12:31:27 PM PDT 23 Oct 01 12:31:43 PM PDT 23 1995529298 ps
T304 /workspace/coverage/default/15.rom_ctrl_smoke.107493952 Oct 01 12:31:18 PM PDT 23 Oct 01 12:31:53 PM PDT 23 8563470820 ps
T305 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3351944272 Oct 01 12:30:46 PM PDT 23 Oct 01 12:54:31 PM PDT 23 25149676449 ps
T306 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2462801071 Oct 01 12:31:11 PM PDT 23 Oct 01 12:31:26 PM PDT 23 3195515970 ps
T307 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2579987075 Oct 01 12:31:08 PM PDT 23 Oct 01 12:39:01 PM PDT 23 49939472084 ps
T308 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1498773485 Oct 01 12:31:25 PM PDT 23 Oct 01 12:34:29 PM PDT 23 11212013486 ps
T309 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.144468328 Oct 01 12:31:07 PM PDT 23 Oct 01 12:35:00 PM PDT 23 42593486573 ps
T310 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1282815658 Oct 01 12:31:02 PM PDT 23 Oct 01 12:38:17 PM PDT 23 167551354509 ps
T311 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3515776419 Oct 01 12:31:44 PM PDT 23 Oct 01 12:32:11 PM PDT 23 26182780962 ps
T312 /workspace/coverage/default/1.rom_ctrl_smoke.2042294824 Oct 01 12:16:10 PM PDT 23 Oct 01 12:16:28 PM PDT 23 2208559905 ps
T313 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2101132676 Oct 01 12:30:57 PM PDT 23 Oct 01 12:31:30 PM PDT 23 11278633125 ps
T314 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1584346183 Oct 01 12:31:32 PM PDT 23 Oct 01 12:31:47 PM PDT 23 3091915627 ps
T315 /workspace/coverage/default/35.rom_ctrl_alert_test.3652535066 Oct 01 12:31:23 PM PDT 23 Oct 01 12:31:32 PM PDT 23 1335200430 ps
T316 /workspace/coverage/default/29.rom_ctrl_alert_test.2235835226 Oct 01 12:30:58 PM PDT 23 Oct 01 12:31:02 PM PDT 23 1655092075 ps
T317 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4193127640 Oct 01 12:30:59 PM PDT 23 Oct 01 12:31:24 PM PDT 23 2226224179 ps
T318 /workspace/coverage/default/23.rom_ctrl_alert_test.64977044 Oct 01 12:30:58 PM PDT 23 Oct 01 12:31:05 PM PDT 23 558919762 ps
T319 /workspace/coverage/default/1.rom_ctrl_stress_all.3680648309 Oct 01 12:18:25 PM PDT 23 Oct 01 12:18:46 PM PDT 23 7900802619 ps
T320 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.764426639 Oct 01 12:23:04 PM PDT 23 Oct 01 12:29:43 PM PDT 23 46096791484 ps
T321 /workspace/coverage/default/13.rom_ctrl_stress_all.3224575177 Oct 01 12:31:01 PM PDT 23 Oct 01 12:31:16 PM PDT 23 1686415900 ps
T322 /workspace/coverage/default/6.rom_ctrl_alert_test.795212227 Oct 01 12:30:53 PM PDT 23 Oct 01 12:30:58 PM PDT 23 1550391285 ps
T323 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.485924351 Oct 01 12:31:06 PM PDT 23 Oct 01 12:35:10 PM PDT 23 19112564490 ps
T324 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.568064529 Oct 01 12:30:46 PM PDT 23 Oct 01 12:35:07 PM PDT 23 22180804878 ps
T325 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1051958062 Oct 01 12:31:48 PM PDT 23 Oct 01 12:31:56 PM PDT 23 3278045979 ps
T326 /workspace/coverage/default/5.rom_ctrl_smoke.3043237965 Oct 01 12:19:36 PM PDT 23 Oct 01 12:20:09 PM PDT 23 12261572564 ps
T327 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3297686341 Oct 01 12:18:25 PM PDT 23 Oct 01 12:18:40 PM PDT 23 1593907384 ps
T328 /workspace/coverage/default/5.rom_ctrl_alert_test.2358665752 Oct 01 12:21:20 PM PDT 23 Oct 01 12:21:35 PM PDT 23 6604549230 ps
T23 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1961471050 Oct 01 12:31:05 PM PDT 23 Oct 01 01:47:50 PM PDT 23 151477822724 ps
T329 /workspace/coverage/default/45.rom_ctrl_alert_test.3793101358 Oct 01 12:31:30 PM PDT 23 Oct 01 12:31:43 PM PDT 23 8714016381 ps
T330 /workspace/coverage/default/17.rom_ctrl_stress_all.1893575162 Oct 01 12:30:57 PM PDT 23 Oct 01 12:32:08 PM PDT 23 70456966087 ps
T331 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1238696600 Oct 01 12:30:43 PM PDT 23 Oct 01 12:52:07 PM PDT 23 139712027100 ps
T332 /workspace/coverage/default/41.rom_ctrl_alert_test.1006415531 Oct 01 12:31:17 PM PDT 23 Oct 01 12:31:30 PM PDT 23 1641378413 ps
T333 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4170173815 Oct 01 12:30:53 PM PDT 23 Oct 01 12:31:03 PM PDT 23 1276249673 ps
T334 /workspace/coverage/default/21.rom_ctrl_alert_test.11848076 Oct 01 12:30:42 PM PDT 23 Oct 01 12:30:55 PM PDT 23 5760905916 ps
T335 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.952376034 Oct 01 12:31:24 PM PDT 23 Oct 01 12:36:21 PM PDT 23 171621127599 ps
T336 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3907536849 Oct 01 12:31:30 PM PDT 23 Oct 01 12:52:31 PM PDT 23 33363070266 ps
T337 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4231295390 Oct 01 12:18:57 PM PDT 23 Oct 01 12:19:09 PM PDT 23 1324784220 ps
T338 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1208906252 Oct 01 12:30:46 PM PDT 23 Oct 01 12:30:52 PM PDT 23 352735428 ps
T339 /workspace/coverage/default/31.rom_ctrl_alert_test.4202726518 Oct 01 12:31:09 PM PDT 23 Oct 01 12:31:14 PM PDT 23 346421449 ps
T46 /workspace/coverage/default/2.rom_ctrl_sec_cm.2946489367 Oct 01 12:21:03 PM PDT 23 Oct 01 12:22:12 PM PDT 23 9087682349 ps
T340 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.104892050 Oct 01 12:30:25 PM PDT 23 Oct 01 12:30:42 PM PDT 23 7706581029 ps
T341 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4224896689 Oct 01 12:30:49 PM PDT 23 Oct 01 12:30:55 PM PDT 23 100518702 ps
T342 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2473410803 Oct 01 12:20:32 PM PDT 23 Oct 01 12:20:48 PM PDT 23 4433788010 ps
T343 /workspace/coverage/default/12.rom_ctrl_alert_test.1666383322 Oct 01 12:30:43 PM PDT 23 Oct 01 12:30:53 PM PDT 23 8566334792 ps
T344 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.92608475 Oct 01 12:31:05 PM PDT 23 Oct 01 12:31:39 PM PDT 23 23243081785 ps
T345 /workspace/coverage/default/3.rom_ctrl_alert_test.2447328866 Oct 01 12:20:29 PM PDT 23 Oct 01 12:20:34 PM PDT 23 93580437 ps
T346 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1524769532 Oct 01 12:31:07 PM PDT 23 Oct 01 12:31:17 PM PDT 23 333587825 ps
T347 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3907728131 Oct 01 12:30:46 PM PDT 23 Oct 01 12:34:30 PM PDT 23 22598019766 ps
T348 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.494013958 Oct 01 12:31:29 PM PDT 23 Oct 01 12:31:36 PM PDT 23 196305444 ps
T349 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1912845579 Oct 01 12:31:15 PM PDT 23 Oct 01 12:31:30 PM PDT 23 8650740344 ps
T350 /workspace/coverage/default/38.rom_ctrl_stress_all.2680701603 Oct 01 12:31:42 PM PDT 23 Oct 01 12:31:51 PM PDT 23 123355724 ps
T351 /workspace/coverage/default/5.rom_ctrl_stress_all.1316752961 Oct 01 12:19:41 PM PDT 23 Oct 01 12:21:53 PM PDT 23 13250566375 ps
T352 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.967862730 Oct 01 12:31:11 PM PDT 23 Oct 01 12:31:23 PM PDT 23 4919445827 ps
T353 /workspace/coverage/default/26.rom_ctrl_alert_test.2849369096 Oct 01 12:31:30 PM PDT 23 Oct 01 12:31:35 PM PDT 23 923955695 ps
T354 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1726571952 Oct 01 12:31:15 PM PDT 23 Oct 01 12:36:45 PM PDT 23 165881281030 ps
T355 /workspace/coverage/default/17.rom_ctrl_smoke.1663978031 Oct 01 12:30:47 PM PDT 23 Oct 01 12:31:11 PM PDT 23 6346090161 ps
T356 /workspace/coverage/default/11.rom_ctrl_alert_test.1521852816 Oct 01 12:30:57 PM PDT 23 Oct 01 12:31:01 PM PDT 23 1657467166 ps
T357 /workspace/coverage/default/25.rom_ctrl_stress_all.1955809188 Oct 01 12:31:25 PM PDT 23 Oct 01 12:31:33 PM PDT 23 121284703 ps
T358 /workspace/coverage/default/37.rom_ctrl_stress_all.1055274807 Oct 01 12:31:37 PM PDT 23 Oct 01 12:32:52 PM PDT 23 20126903660 ps
T359 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1175413643 Oct 01 12:20:53 PM PDT 23 Oct 01 12:23:45 PM PDT 23 119332501372 ps
T360 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1834039314 Oct 01 12:30:58 PM PDT 23 Oct 01 12:31:17 PM PDT 23 1785616084 ps
T361 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3467002725 Oct 01 12:30:47 PM PDT 23 Oct 01 01:13:27 PM PDT 23 70992909521 ps
T362 /workspace/coverage/default/18.rom_ctrl_alert_test.3334784729 Oct 01 12:31:23 PM PDT 23 Oct 01 12:31:27 PM PDT 23 346942940 ps
T363 /workspace/coverage/default/3.rom_ctrl_smoke.732824471 Oct 01 12:17:13 PM PDT 23 Oct 01 12:17:24 PM PDT 23 1020580908 ps
T364 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4098013057 Oct 01 12:31:27 PM PDT 23 Oct 01 12:31:56 PM PDT 23 19327391234 ps
T365 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.574554263 Oct 01 12:20:49 PM PDT 23 Oct 01 12:20:54 PM PDT 23 99753845 ps
T366 /workspace/coverage/default/19.rom_ctrl_alert_test.2938300209 Oct 01 12:30:47 PM PDT 23 Oct 01 12:31:04 PM PDT 23 2091551009 ps
T367 /workspace/coverage/default/44.rom_ctrl_smoke.4202446058 Oct 01 12:30:45 PM PDT 23 Oct 01 12:31:11 PM PDT 23 5064944596 ps
T368 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.285901251 Oct 01 12:30:53 PM PDT 23 Oct 01 12:35:54 PM PDT 23 315517956094 ps
T369 /workspace/coverage/default/21.rom_ctrl_smoke.2663406953 Oct 01 12:30:57 PM PDT 23 Oct 01 12:31:14 PM PDT 23 946807097 ps
T370 /workspace/coverage/default/15.rom_ctrl_alert_test.3533910495 Oct 01 12:30:55 PM PDT 23 Oct 01 12:31:11 PM PDT 23 8185585705 ps
T371 /workspace/coverage/default/44.rom_ctrl_stress_all.131437843 Oct 01 12:31:31 PM PDT 23 Oct 01 12:31:47 PM PDT 23 2249303537 ps
T372 /workspace/coverage/default/42.rom_ctrl_alert_test.645330260 Oct 01 12:31:20 PM PDT 23 Oct 01 12:31:25 PM PDT 23 346932321 ps
T373 /workspace/coverage/default/14.rom_ctrl_stress_all.1678558001 Oct 01 12:31:33 PM PDT 23 Oct 01 12:32:58 PM PDT 23 70273104526 ps
T374 /workspace/coverage/default/20.rom_ctrl_alert_test.2450022061 Oct 01 12:30:53 PM PDT 23 Oct 01 12:30:59 PM PDT 23 294269909 ps
T375 /workspace/coverage/default/1.rom_ctrl_alert_test.510637905 Oct 01 12:19:38 PM PDT 23 Oct 01 12:19:52 PM PDT 23 3591606402 ps
T376 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1459335040 Oct 01 12:30:58 PM PDT 23 Oct 01 12:31:03 PM PDT 23 371239043 ps
T377 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1811975701 Oct 01 12:31:32 PM PDT 23 Oct 01 12:32:06 PM PDT 23 4444851276 ps
T378 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.874563681 Oct 01 12:31:22 PM PDT 23 Oct 01 12:31:31 PM PDT 23 471846773 ps
T379 /workspace/coverage/default/19.rom_ctrl_smoke.3178488130 Oct 01 12:31:19 PM PDT 23 Oct 01 12:31:55 PM PDT 23 13833775464 ps
T380 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1323728103 Oct 01 12:22:48 PM PDT 23 Oct 01 12:22:59 PM PDT 23 175373368 ps
T381 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2738828805 Oct 01 12:31:28 PM PDT 23 Oct 01 12:34:43 PM PDT 23 21728556795 ps
T382 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4045722082 Oct 01 12:31:03 PM PDT 23 Oct 01 12:31:36 PM PDT 23 3882545026 ps
T383 /workspace/coverage/default/32.rom_ctrl_smoke.3778300201 Oct 01 12:30:47 PM PDT 23 Oct 01 12:31:20 PM PDT 23 3083030831 ps
T384 /workspace/coverage/default/9.rom_ctrl_stress_all.1791719301 Oct 01 12:30:45 PM PDT 23 Oct 01 12:31:51 PM PDT 23 4981423872 ps
T385 /workspace/coverage/default/25.rom_ctrl_smoke.3358067603 Oct 01 12:31:15 PM PDT 23 Oct 01 12:31:49 PM PDT 23 6890801459 ps
T386 /workspace/coverage/default/29.rom_ctrl_stress_all.2082151982 Oct 01 12:31:04 PM PDT 23 Oct 01 12:31:19 PM PDT 23 3023764788 ps
T387 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.9259825 Oct 01 12:31:26 PM PDT 23 Oct 01 12:36:23 PM PDT 23 62225461056 ps
T388 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.587254989 Oct 01 12:31:41 PM PDT 23 Oct 01 12:31:55 PM PDT 23 5802898387 ps
T389 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.231541061 Oct 01 12:31:26 PM PDT 23 Oct 01 12:31:44 PM PDT 23 5472362275 ps
T390 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2958236262 Oct 01 12:30:47 PM PDT 23 Oct 01 12:31:18 PM PDT 23 15004082014 ps
T391 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2268273494 Oct 01 12:18:40 PM PDT 23 Oct 01 12:19:13 PM PDT 23 16416375812 ps
T392 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1426203531 Oct 01 12:31:08 PM PDT 23 Oct 01 12:31:22 PM PDT 23 1586598730 ps
T393 /workspace/coverage/default/22.rom_ctrl_alert_test.602116674 Oct 01 12:31:10 PM PDT 23 Oct 01 12:31:16 PM PDT 23 403458508 ps
T394 /workspace/coverage/default/42.rom_ctrl_smoke.3225787054 Oct 01 12:31:17 PM PDT 23 Oct 01 12:31:44 PM PDT 23 38382733125 ps
T395 /workspace/coverage/default/41.rom_ctrl_stress_all.2888800231 Oct 01 12:31:36 PM PDT 23 Oct 01 12:32:28 PM PDT 23 19542237253 ps
T396 /workspace/coverage/default/11.rom_ctrl_stress_all.3430490085 Oct 01 12:30:49 PM PDT 23 Oct 01 12:31:55 PM PDT 23 20894396733 ps
T397 /workspace/coverage/default/8.rom_ctrl_alert_test.3973481465 Oct 01 12:30:55 PM PDT 23 Oct 01 12:31:04 PM PDT 23 690198685 ps
T398 /workspace/coverage/default/40.rom_ctrl_stress_all.1507900327 Oct 01 12:31:48 PM PDT 23 Oct 01 12:32:04 PM PDT 23 768664874 ps
T399 /workspace/coverage/default/36.rom_ctrl_smoke.4086798960 Oct 01 12:31:38 PM PDT 23 Oct 01 12:32:04 PM PDT 23 2725595622 ps
T400 /workspace/coverage/default/39.rom_ctrl_stress_all.1649733902 Oct 01 12:31:14 PM PDT 23 Oct 01 12:31:52 PM PDT 23 5119720917 ps
T401 /workspace/coverage/default/48.rom_ctrl_stress_all.723397220 Oct 01 12:31:31 PM PDT 23 Oct 01 12:32:06 PM PDT 23 8106551393 ps
T402 /workspace/coverage/default/18.rom_ctrl_stress_all.1718430948 Oct 01 12:30:53 PM PDT 23 Oct 01 12:31:08 PM PDT 23 2662092545 ps
T403 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3137331277 Oct 01 12:31:35 PM PDT 23 Oct 01 12:31:44 PM PDT 23 357815455 ps
T47 /workspace/coverage/default/0.rom_ctrl_sec_cm.229735684 Oct 01 12:15:48 PM PDT 23 Oct 01 12:16:57 PM PDT 23 2165510753 ps
T404 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.539060488 Oct 01 12:31:18 PM PDT 23 Oct 01 12:31:31 PM PDT 23 986024143 ps
T405 /workspace/coverage/default/24.rom_ctrl_stress_all.1960871018 Oct 01 12:30:49 PM PDT 23 Oct 01 12:31:38 PM PDT 23 10283561480 ps
T89 /workspace/coverage/default/2.rom_ctrl_smoke.2324759039 Oct 01 12:14:49 PM PDT 23 Oct 01 12:15:14 PM PDT 23 2966091584 ps
T90 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.61243231 Oct 01 12:31:05 PM PDT 23 Oct 01 12:31:29 PM PDT 23 5429134687 ps
T91 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1427392067 Oct 01 12:31:40 PM PDT 23 Oct 01 12:31:51 PM PDT 23 664665347 ps
T92 /workspace/coverage/default/16.rom_ctrl_smoke.2358443791 Oct 01 12:31:08 PM PDT 23 Oct 01 12:31:24 PM PDT 23 3479223158 ps
T93 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.192477522 Oct 01 12:31:22 PM PDT 23 Oct 01 12:31:32 PM PDT 23 4139106117 ps
T94 /workspace/coverage/default/21.rom_ctrl_stress_all.633328642 Oct 01 12:30:53 PM PDT 23 Oct 01 12:31:02 PM PDT 23 533476880 ps
T95 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2443752675 Oct 01 12:23:42 PM PDT 23 Oct 01 12:28:21 PM PDT 23 91685670388 ps
T96 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2599380244 Oct 01 12:31:23 PM PDT 23 Oct 01 12:35:45 PM PDT 23 47937472288 ps
T97 /workspace/coverage/default/35.rom_ctrl_smoke.918126544 Oct 01 12:31:12 PM PDT 23 Oct 01 12:31:29 PM PDT 23 1668539703 ps
T98 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2874165629 Oct 01 12:15:07 PM PDT 23 Oct 01 02:33:50 PM PDT 23 224601640224 ps
T406 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.728970974 Oct 01 12:31:26 PM PDT 23 Oct 01 12:38:07 PM PDT 23 256684563802 ps
T407 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3138659368 Oct 01 12:31:08 PM PDT 23 Oct 01 01:59:45 PM PDT 23 65323115090 ps
T408 /workspace/coverage/default/47.rom_ctrl_smoke.1102938302 Oct 01 12:31:26 PM PDT 23 Oct 01 12:31:37 PM PDT 23 1639227873 ps
T409 /workspace/coverage/default/38.rom_ctrl_smoke.380750235 Oct 01 12:31:04 PM PDT 23 Oct 01 12:31:32 PM PDT 23 2407473828 ps
T410 /workspace/coverage/default/6.rom_ctrl_smoke.2731330426 Oct 01 12:20:51 PM PDT 23 Oct 01 12:21:24 PM PDT 23 3389187693 ps
T411 /workspace/coverage/default/2.rom_ctrl_stress_all.292525772 Oct 01 12:19:31 PM PDT 23 Oct 01 12:20:05 PM PDT 23 5001145056 ps
T412 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2154800237 Oct 01 12:22:57 PM PDT 23 Oct 01 12:23:06 PM PDT 23 693582347 ps
T413 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2144299265 Oct 01 12:31:13 PM PDT 23 Oct 01 12:34:16 PM PDT 23 4757688409 ps
T414 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.4249173501 Oct 01 12:30:55 PM PDT 23 Oct 01 01:37:35 PM PDT 23 40076239066 ps
T415 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3676498917 Oct 01 12:31:28 PM PDT 23 Oct 01 12:31:34 PM PDT 23 400814943 ps
T416 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4033229072 Oct 01 12:30:47 PM PDT 23 Oct 01 12:30:57 PM PDT 23 761785559 ps
T417 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2081723388 Oct 01 12:31:08 PM PDT 23 Oct 01 12:31:14 PM PDT 23 463054871 ps
T418 /workspace/coverage/default/4.rom_ctrl_alert_test.3767328510 Oct 01 12:19:59 PM PDT 23 Oct 01 12:20:04 PM PDT 23 333186744 ps
T419 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.725347736 Oct 01 12:31:06 PM PDT 23 Oct 01 12:31:19 PM PDT 23 1389941847 ps
T420 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3431091690 Oct 01 12:31:24 PM PDT 23 Oct 01 12:31:30 PM PDT 23 99457698 ps
T421 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1845351403 Oct 01 12:31:01 PM PDT 23 Oct 01 12:33:38 PM PDT 23 154339218860 ps
T422 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1466727160 Oct 01 12:21:07 PM PDT 23 Oct 01 01:09:33 PM PDT 23 201118503082 ps
T423 /workspace/coverage/default/23.rom_ctrl_smoke.2067285232 Oct 01 12:31:18 PM PDT 23 Oct 01 12:31:39 PM PDT 23 3703703791 ps
T424 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2436467449 Oct 01 12:30:50 PM PDT 23 Oct 01 12:39:46 PM PDT 23 12074289051 ps
T425 /workspace/coverage/default/3.rom_ctrl_stress_all.4105998723 Oct 01 12:22:29 PM PDT 23 Oct 01 12:24:00 PM PDT 23 20483931820 ps
T426 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1323769642 Oct 01 12:30:52 PM PDT 23 Oct 01 12:35:43 PM PDT 23 20198242602 ps
T427 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1445079327 Oct 01 12:31:26 PM PDT 23 Oct 01 02:15:51 PM PDT 23 50516451233 ps
T428 /workspace/coverage/default/45.rom_ctrl_smoke.663239522 Oct 01 12:31:08 PM PDT 23 Oct 01 12:31:19 PM PDT 23 242099025 ps
T429 /workspace/coverage/default/8.rom_ctrl_smoke.1319832843 Oct 01 12:30:45 PM PDT 23 Oct 01 12:31:02 PM PDT 23 1907197986 ps
T430 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1878307567 Oct 01 12:31:26 PM PDT 23 Oct 01 12:38:21 PM PDT 23 79089581476 ps
T431 /workspace/coverage/default/48.rom_ctrl_alert_test.2574019066 Oct 01 12:31:37 PM PDT 23 Oct 01 12:31:42 PM PDT 23 592672543 ps
T432 /workspace/coverage/default/9.rom_ctrl_alert_test.1836366528 Oct 01 12:30:53 PM PDT 23 Oct 01 12:31:08 PM PDT 23 1751979550 ps
T433 /workspace/coverage/default/12.rom_ctrl_stress_all.448978653 Oct 01 12:31:15 PM PDT 23 Oct 01 12:32:34 PM PDT 23 9462580394 ps
T24 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.4248647082 Oct 01 12:21:20 PM PDT 23 Oct 01 01:00:57 PM PDT 23 63056799727 ps
T88 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4204514640 Oct 01 12:31:51 PM PDT 23 Oct 01 12:34:38 PM PDT 23 9884833956 ps
T434 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1513646206 Oct 01 12:31:58 PM PDT 23 Oct 01 12:32:08 PM PDT 23 974668693 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1124565275 Oct 01 12:32:04 PM PDT 23 Oct 01 12:32:11 PM PDT 23 662628780 ps
T436 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.303878645 Oct 01 12:31:45 PM PDT 23 Oct 01 12:31:55 PM PDT 23 4391266166 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.451169197 Oct 01 12:19:47 PM PDT 23 Oct 01 12:19:52 PM PDT 23 170191649 ps
T438 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.660021333 Oct 01 12:31:39 PM PDT 23 Oct 01 12:31:52 PM PDT 23 1417689401 ps
T439 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2731721950 Oct 01 12:31:38 PM PDT 23 Oct 01 12:31:58 PM PDT 23 1859548169 ps
T440 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.209051779 Oct 01 12:31:34 PM PDT 23 Oct 01 12:31:47 PM PDT 23 4447326632 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4169890296 Oct 01 12:21:19 PM PDT 23 Oct 01 12:21:32 PM PDT 23 15529587445 ps
T441 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.36849652 Oct 01 12:31:36 PM PDT 23 Oct 01 12:36:02 PM PDT 23 86597919763 ps
T114 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1557114488 Oct 01 12:31:45 PM PDT 23 Oct 01 12:32:34 PM PDT 23 7534438131 ps
T81 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3793699138 Oct 01 12:19:30 PM PDT 23 Oct 01 12:21:07 PM PDT 23 10942428264 ps
T442 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2547486320 Oct 01 12:32:01 PM PDT 23 Oct 01 12:32:22 PM PDT 23 2042781886 ps
T108 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1317068957 Oct 01 12:32:37 PM PDT 23 Oct 01 12:33:55 PM PDT 23 2819088634 ps
T443 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3618016608 Oct 01 12:31:42 PM PDT 23 Oct 01 12:31:54 PM PDT 23 6824315057 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1792153952 Oct 01 12:18:45 PM PDT 23 Oct 01 12:18:56 PM PDT 23 1036828986 ps
T109 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4246003090 Oct 01 12:31:57 PM PDT 23 Oct 01 12:32:46 PM PDT 23 1971960182 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1386684890 Oct 01 12:20:48 PM PDT 23 Oct 01 12:20:58 PM PDT 23 2414786794 ps
T446 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1831137504 Oct 01 12:31:59 PM PDT 23 Oct 01 12:32:16 PM PDT 23 3591882224 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3411424799 Oct 01 12:17:46 PM PDT 23 Oct 01 12:17:51 PM PDT 23 392392915 ps
T448 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1511373683 Oct 01 12:32:03 PM PDT 23 Oct 01 12:32:22 PM PDT 23 1693286852 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3069921598 Oct 01 12:21:06 PM PDT 23 Oct 01 12:21:12 PM PDT 23 164900308 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2839999317 Oct 01 12:15:24 PM PDT 23 Oct 01 12:15:28 PM PDT 23 89080795 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1137195719 Oct 01 12:17:45 PM PDT 23 Oct 01 12:17:54 PM PDT 23 2284855296 ps
T83 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4047899170 Oct 01 12:31:41 PM PDT 23 Oct 01 12:33:43 PM PDT 23 87299346561 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2455442221 Oct 01 12:18:37 PM PDT 23 Oct 01 12:18:43 PM PDT 23 259297619 ps
T452 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3397570587 Oct 01 12:31:36 PM PDT 23 Oct 01 12:32:26 PM PDT 23 2062190905 ps
T453 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2740897718 Oct 01 12:31:40 PM PDT 23 Oct 01 12:31:51 PM PDT 23 214226043 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4008177387 Oct 01 12:20:34 PM PDT 23 Oct 01 12:21:26 PM PDT 23 1309224213 ps
T455 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.404571367 Oct 01 12:31:41 PM PDT 23 Oct 01 12:31:55 PM PDT 23 1751035157 ps
T456 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1006483791 Oct 01 12:32:10 PM PDT 23 Oct 01 12:33:01 PM PDT 23 988398301 ps
T457 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3399487894 Oct 01 12:31:25 PM PDT 23 Oct 01 12:31:42 PM PDT 23 34680263928 ps
T458 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1566647015 Oct 01 12:31:48 PM PDT 23 Oct 01 12:32:03 PM PDT 23 3040797824 ps
T459 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2298390552 Oct 01 12:31:35 PM PDT 23 Oct 01 12:31:50 PM PDT 23 1696926281 ps
T460 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3425652005 Oct 01 12:32:30 PM PDT 23 Oct 01 12:32:36 PM PDT 23 137504234 ps
T461 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3244107548 Oct 01 12:22:27 PM PDT 23 Oct 01 12:22:39 PM PDT 23 1513470868 ps
T462 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2286283998 Oct 01 12:31:44 PM PDT 23 Oct 01 12:32:01 PM PDT 23 2072466586 ps
T463 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1500244557 Oct 01 12:31:42 PM PDT 23 Oct 01 12:32:00 PM PDT 23 4108313469 ps
T464 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3662223086 Oct 01 12:19:22 PM PDT 23 Oct 01 12:22:05 PM PDT 23 37658016689 ps
T465 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4207614004 Oct 01 12:19:40 PM PDT 23 Oct 01 12:19:49 PM PDT 23 867899341 ps
T466 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.668016494 Oct 01 12:32:14 PM PDT 23 Oct 01 12:32:19 PM PDT 23 333975760 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3573039907 Oct 01 12:18:40 PM PDT 23 Oct 01 12:18:48 PM PDT 23 594409839 ps
T467 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.383093802 Oct 01 12:20:50 PM PDT 23 Oct 01 12:23:26 PM PDT 23 8220382246 ps
T468 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2884761125 Oct 01 12:21:42 PM PDT 23 Oct 01 12:21:56 PM PDT 23 1282672465 ps
T469 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2680698913 Oct 01 12:15:33 PM PDT 23 Oct 01 12:15:46 PM PDT 23 1414898049 ps
T470 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2662892124 Oct 01 12:31:32 PM PDT 23 Oct 01 12:31:41 PM PDT 23 1111079182 ps
T471 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3636556211 Oct 01 12:19:50 PM PDT 23 Oct 01 12:20:03 PM PDT 23 11741819445 ps
T472 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1277775060 Oct 01 12:19:56 PM PDT 23 Oct 01 12:20:02 PM PDT 23 209105302 ps
T473 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.429867265 Oct 01 12:19:28 PM PDT 23 Oct 01 12:19:35 PM PDT 23 857948292 ps
T474 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4269596476 Oct 01 12:32:13 PM PDT 23 Oct 01 12:32:25 PM PDT 23 2194035824 ps
T475 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.220115376 Oct 01 12:20:35 PM PDT 23 Oct 01 12:20:46 PM PDT 23 5085907588 ps
T476 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1810801111 Oct 01 12:20:44 PM PDT 23 Oct 01 12:20:54 PM PDT 23 1665475905 ps
T477 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1525894496 Oct 01 12:20:55 PM PDT 23 Oct 01 12:21:46 PM PDT 23 5622835253 ps
T116 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1006773505 Oct 01 12:21:17 PM PDT 23 Oct 01 12:22:07 PM PDT 23 2308999574 ps
T478 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1996330821 Oct 01 12:15:56 PM PDT 23 Oct 01 12:16:12 PM PDT 23 1983501949 ps
T479 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.192231779 Oct 01 12:31:47 PM PDT 23 Oct 01 12:31:59 PM PDT 23 217090620 ps
T480 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4264467391 Oct 01 12:32:03 PM PDT 23 Oct 01 12:32:18 PM PDT 23 2046297896 ps
T481 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1230504179 Oct 01 12:31:22 PM PDT 23 Oct 01 12:31:36 PM PDT 23 1557899843 ps
T482 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1122402189 Oct 01 12:31:45 PM PDT 23 Oct 01 12:36:23 PM PDT 23 25812399203 ps
T483 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.107926464 Oct 01 12:31:56 PM PDT 23 Oct 01 12:32:06 PM PDT 23 1868875572 ps
T484 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3079603905 Oct 01 12:31:37 PM PDT 23 Oct 01 12:31:53 PM PDT 23 2128596593 ps

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2451526527
Short name T20
Test name
Test status
Simulation time 3337811067 ps
CPU time 15.56 seconds
Started Oct 01 12:20:40 PM PDT 23
Finished Oct 01 12:20:56 PM PDT 23
Peak memory 218916 kb
Host smart-b02c3b06-7316-4abe-8746-d50ce4d47975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451526527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2451526527
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1412746461
Short name T8
Test name
Test status
Simulation time 60105682401 ps
CPU time 9768.41 seconds
Started Oct 01 12:31:31 PM PDT 23
Finished Oct 01 03:14:20 PM PDT 23
Peak memory 236436 kb
Host smart-7390b852-45f4-4f36-bb8f-4f98a573f454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412746461 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1412746461
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3646384486
Short name T28
Test name
Test status
Simulation time 7491822215 ps
CPU time 99.69 seconds
Started Oct 01 12:31:54 PM PDT 23
Finished Oct 01 12:33:34 PM PDT 23
Peak memory 218784 kb
Host smart-b4c3044b-4cb5-4b48-8f4e-3b1e5b430f23
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646384486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3646384486
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.345899608
Short name T32
Test name
Test status
Simulation time 4315406252 ps
CPU time 13.79 seconds
Started Oct 01 12:14:50 PM PDT 23
Finished Oct 01 12:15:04 PM PDT 23
Peak memory 215028 kb
Host smart-391b0749-ad6b-4019-b152-136ae1f7dd9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345899608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.345899608
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1273434073
Short name T57
Test name
Test status
Simulation time 5565810220 ps
CPU time 45.9 seconds
Started Oct 01 12:21:31 PM PDT 23
Finished Oct 01 12:22:22 PM PDT 23
Peak memory 212152 kb
Host smart-85df869d-b216-42d2-88a4-3710d878df02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273434073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1273434073
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4132737053
Short name T7
Test name
Test status
Simulation time 31318920045 ps
CPU time 350.42 seconds
Started Oct 01 12:31:30 PM PDT 23
Finished Oct 01 12:37:26 PM PDT 23
Peak memory 237724 kb
Host smart-b11753d1-d1c6-4675-b0f4-d32b2b799365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132737053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4132737053
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.487776203
Short name T56
Test name
Test status
Simulation time 182735613 ps
CPU time 10.51 seconds
Started Oct 01 12:31:21 PM PDT 23
Finished Oct 01 12:31:32 PM PDT 23
Peak memory 213072 kb
Host smart-97e62ff9-40d3-4018-8c84-163d0884913f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487776203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.487776203
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1557114488
Short name T114
Test name
Test status
Simulation time 7534438131 ps
CPU time 49.07 seconds
Started Oct 01 12:31:45 PM PDT 23
Finished Oct 01 12:32:34 PM PDT 23
Peak memory 212144 kb
Host smart-9ea78026-e42d-4d91-85a6-6f300fef08d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557114488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1557114488
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2372452173
Short name T2
Test name
Test status
Simulation time 23640219572 ps
CPU time 117.25 seconds
Started Oct 01 12:19:24 PM PDT 23
Finished Oct 01 12:21:22 PM PDT 23
Peak memory 235812 kb
Host smart-e1ce8d1a-f9f1-447c-866f-dbfcb83cfaf4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372452173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2372452173
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.4248647082
Short name T24
Test name
Test status
Simulation time 63056799727 ps
CPU time 2377.18 seconds
Started Oct 01 12:21:20 PM PDT 23
Finished Oct 01 01:00:57 PM PDT 23
Peak memory 235432 kb
Host smart-09d1551f-e0b9-40f6-a698-b108f63ffd69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248647082 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.4248647082
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.207766918
Short name T112
Test name
Test status
Simulation time 1180797388 ps
CPU time 77.3 seconds
Started Oct 01 12:31:36 PM PDT 23
Finished Oct 01 12:32:54 PM PDT 23
Peak memory 211128 kb
Host smart-27babb51-7de9-4c91-a0b2-620ca5ade217
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207766918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.207766918
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1566515959
Short name T167
Test name
Test status
Simulation time 3431232547 ps
CPU time 62.83 seconds
Started Oct 01 12:30:42 PM PDT 23
Finished Oct 01 12:31:45 PM PDT 23
Peak memory 212356 kb
Host smart-58bc7dd6-6553-4a7d-a5d4-7569fa7ee0cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566515959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1566515959
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4246003090
Short name T109
Test name
Test status
Simulation time 1971960182 ps
CPU time 48.96 seconds
Started Oct 01 12:31:57 PM PDT 23
Finished Oct 01 12:32:46 PM PDT 23
Peak memory 218820 kb
Host smart-f75830e7-e4c2-4c1f-84b4-d2efeec37a78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246003090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4246003090
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3522189593
Short name T79
Test name
Test status
Simulation time 85585587 ps
CPU time 4.45 seconds
Started Oct 01 12:18:53 PM PDT 23
Finished Oct 01 12:18:58 PM PDT 23
Peak memory 210640 kb
Host smart-3ed1151a-4bb0-41ae-8762-cb126ceb9cd2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522189593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3522189593
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2331748280
Short name T17
Test name
Test status
Simulation time 4074254188 ps
CPU time 20.68 seconds
Started Oct 01 12:30:53 PM PDT 23
Finished Oct 01 12:31:14 PM PDT 23
Peak memory 211264 kb
Host smart-2b982e38-396e-4674-b736-41c211d0f0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331748280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2331748280
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3992343802
Short name T11
Test name
Test status
Simulation time 754963729 ps
CPU time 9.67 seconds
Started Oct 01 12:31:20 PM PDT 23
Finished Oct 01 12:31:30 PM PDT 23
Peak memory 211152 kb
Host smart-667c8a7e-2088-4187-b220-84da90f2ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992343802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3992343802
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2480661864
Short name T1
Test name
Test status
Simulation time 44929569778 ps
CPU time 99.19 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:33:03 PM PDT 23
Peak memory 217512 kb
Host smart-fb8cda63-70f5-4700-9c68-e23ca75129b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480661864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2480661864
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1033076729
Short name T184
Test name
Test status
Simulation time 88888992 ps
CPU time 4.4 seconds
Started Oct 01 12:31:01 PM PDT 23
Finished Oct 01 12:31:05 PM PDT 23
Peak memory 210908 kb
Host smart-f720dae1-fca2-499e-bfe8-080b8c4405fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033076729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1033076729
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1250524210
Short name T70
Test name
Test status
Simulation time 1598754302 ps
CPU time 75.25 seconds
Started Oct 01 12:32:00 PM PDT 23
Finished Oct 01 12:33:16 PM PDT 23
Peak memory 218804 kb
Host smart-977efe7b-ee7b-41c9-8f30-b1bab146a437
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250524210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1250524210
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2324759039
Short name T89
Test name
Test status
Simulation time 2966091584 ps
CPU time 24.48 seconds
Started Oct 01 12:14:49 PM PDT 23
Finished Oct 01 12:15:14 PM PDT 23
Peak memory 214000 kb
Host smart-9ee7fe40-3dc9-4bce-b7ca-e9cfe0449767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324759039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2324759039
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4169890296
Short name T80
Test name
Test status
Simulation time 15529587445 ps
CPU time 12.65 seconds
Started Oct 01 12:21:19 PM PDT 23
Finished Oct 01 12:21:32 PM PDT 23
Peak memory 217588 kb
Host smart-2ce80cb7-fc8b-4b57-8229-a996aef0fa1a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169890296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4169890296
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1251494887
Short name T139
Test name
Test status
Simulation time 396437255 ps
CPU time 4.44 seconds
Started Oct 01 12:20:22 PM PDT 23
Finished Oct 01 12:20:27 PM PDT 23
Peak memory 209796 kb
Host smart-f730d039-fd2a-4947-bb07-6f05d75b03a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251494887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1251494887
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.560119842
Short name T121
Test name
Test status
Simulation time 1202914796 ps
CPU time 7.7 seconds
Started Oct 01 12:19:35 PM PDT 23
Finished Oct 01 12:19:45 PM PDT 23
Peak memory 210356 kb
Host smart-5df68aaa-1ebb-4d6b-8f4a-725d88dd09e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560119842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.560119842
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3411424799
Short name T447
Test name
Test status
Simulation time 392392915 ps
CPU time 4.89 seconds
Started Oct 01 12:17:46 PM PDT 23
Finished Oct 01 12:17:51 PM PDT 23
Peak memory 218648 kb
Host smart-298c9004-16dc-4d29-87b6-ea171608f926
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411424799 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3411424799
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2884761125
Short name T468
Test name
Test status
Simulation time 1282672465 ps
CPU time 11.77 seconds
Started Oct 01 12:21:42 PM PDT 23
Finished Oct 01 12:21:56 PM PDT 23
Peak memory 210624 kb
Host smart-43b0fddb-35b7-46a2-afaf-2c2c6b89c458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884761125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2884761125
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2312059985
Short name T119
Test name
Test status
Simulation time 250918316 ps
CPU time 5.75 seconds
Started Oct 01 12:18:38 PM PDT 23
Finished Oct 01 12:18:44 PM PDT 23
Peak memory 210308 kb
Host smart-dc3a11b0-1793-4313-815e-5a7ac1c46070
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312059985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2312059985
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.864825715
Short name T130
Test name
Test status
Simulation time 1752351673 ps
CPU time 14.48 seconds
Started Oct 01 12:17:15 PM PDT 23
Finished Oct 01 12:17:29 PM PDT 23
Peak memory 210804 kb
Host smart-e0ba67ab-eb3b-48e8-a346-be00d5fffd88
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864825715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
864825715
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4008177387
Short name T454
Test name
Test status
Simulation time 1309224213 ps
CPU time 51.05 seconds
Started Oct 01 12:20:34 PM PDT 23
Finished Oct 01 12:21:26 PM PDT 23
Peak memory 210632 kb
Host smart-cf9fc623-a437-463a-be5e-65aee6cc1db2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008177387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4008177387
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1792153952
Short name T444
Test name
Test status
Simulation time 1036828986 ps
CPU time 10.28 seconds
Started Oct 01 12:18:45 PM PDT 23
Finished Oct 01 12:18:56 PM PDT 23
Peak memory 210616 kb
Host smart-ac03267c-db8f-4f56-8bf6-36a593f198d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792153952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1792153952
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2045779295
Short name T53
Test name
Test status
Simulation time 7298442606 ps
CPU time 17.85 seconds
Started Oct 01 12:20:29 PM PDT 23
Finished Oct 01 12:20:47 PM PDT 23
Peak memory 217904 kb
Host smart-88d813fc-dc71-44eb-b042-f84e52874919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045779295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2045779295
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1603369255
Short name T71
Test name
Test status
Simulation time 44882891100 ps
CPU time 85.02 seconds
Started Oct 01 12:18:58 PM PDT 23
Finished Oct 01 12:20:23 PM PDT 23
Peak memory 218832 kb
Host smart-189b7d4c-be84-4102-947a-c1d8917125ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603369255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1603369255
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2839999317
Short name T82
Test name
Test status
Simulation time 89080795 ps
CPU time 4.47 seconds
Started Oct 01 12:15:24 PM PDT 23
Finished Oct 01 12:15:28 PM PDT 23
Peak memory 210752 kb
Host smart-4a3f088b-dbc9-472b-bf4b-a200723e8e3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839999317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2839999317
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2680698913
Short name T469
Test name
Test status
Simulation time 1414898049 ps
CPU time 12.76 seconds
Started Oct 01 12:15:33 PM PDT 23
Finished Oct 01 12:15:46 PM PDT 23
Peak memory 210784 kb
Host smart-ca1f478f-79f0-4b19-9f6e-983b069a3530
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680698913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2680698913
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.143277128
Short name T62
Test name
Test status
Simulation time 1558322044 ps
CPU time 16.19 seconds
Started Oct 01 12:20:41 PM PDT 23
Finished Oct 01 12:20:57 PM PDT 23
Peak memory 217740 kb
Host smart-0993ac65-6130-44cf-8dec-484f85597b3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143277128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.143277128
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4026903473
Short name T72
Test name
Test status
Simulation time 632041358 ps
CPU time 8.11 seconds
Started Oct 01 12:20:57 PM PDT 23
Finished Oct 01 12:21:05 PM PDT 23
Peak memory 211120 kb
Host smart-b581789f-653b-4d7e-b9ba-97af8b81baa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026903473 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4026903473
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3573039907
Short name T85
Test name
Test status
Simulation time 594409839 ps
CPU time 7.81 seconds
Started Oct 01 12:18:40 PM PDT 23
Finished Oct 01 12:18:48 PM PDT 23
Peak memory 215672 kb
Host smart-19e05469-70ca-4d77-89a8-bd5ddb1c71d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573039907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3573039907
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.359783499
Short name T147
Test name
Test status
Simulation time 41123919936 ps
CPU time 16.97 seconds
Started Oct 01 12:18:42 PM PDT 23
Finished Oct 01 12:19:00 PM PDT 23
Peak memory 210644 kb
Host smart-ca065576-8d03-4092-821b-f5fc26ae9212
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359783499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.359783499
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3692119302
Short name T133
Test name
Test status
Simulation time 1138226425 ps
CPU time 10.99 seconds
Started Oct 01 12:19:31 PM PDT 23
Finished Oct 01 12:19:42 PM PDT 23
Peak memory 210564 kb
Host smart-f3a73f42-a285-4e43-a9a1-b1d90cece004
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692119302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3692119302
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4004512214
Short name T43
Test name
Test status
Simulation time 23346813985 ps
CPU time 175.2 seconds
Started Oct 01 12:19:33 PM PDT 23
Finished Oct 01 12:22:29 PM PDT 23
Peak memory 210488 kb
Host smart-76bd592b-b7c6-457e-b27c-45dcd03d67f1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004512214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4004512214
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1137195719
Short name T450
Test name
Test status
Simulation time 2284855296 ps
CPU time 7.97 seconds
Started Oct 01 12:17:45 PM PDT 23
Finished Oct 01 12:17:54 PM PDT 23
Peak memory 214984 kb
Host smart-c1945bbe-0ef1-45b0-b042-fa1108c142ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137195719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1137195719
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3683924983
Short name T118
Test name
Test status
Simulation time 8630220493 ps
CPU time 12.31 seconds
Started Oct 01 12:16:24 PM PDT 23
Finished Oct 01 12:16:36 PM PDT 23
Peak memory 219044 kb
Host smart-3ac635a0-41fc-47b7-8ad2-bcea183ae0ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683924983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3683924983
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.172272024
Short name T106
Test name
Test status
Simulation time 17859104514 ps
CPU time 48.54 seconds
Started Oct 01 12:20:22 PM PDT 23
Finished Oct 01 12:21:11 PM PDT 23
Peak memory 217952 kb
Host smart-ac9c59b3-7f87-4897-a6ac-04eaa199b76a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172272024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.172272024
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1515337131
Short name T136
Test name
Test status
Simulation time 19738254488 ps
CPU time 11.5 seconds
Started Oct 01 12:31:41 PM PDT 23
Finished Oct 01 12:31:53 PM PDT 23
Peak memory 213544 kb
Host smart-d2a2eb7b-ba7b-4ef5-87df-9e660e497aea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515337131 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1515337131
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4262243416
Short name T125
Test name
Test status
Simulation time 7364516754 ps
CPU time 14.08 seconds
Started Oct 01 12:31:28 PM PDT 23
Finished Oct 01 12:31:42 PM PDT 23
Peak memory 210684 kb
Host smart-b31639d9-137d-4ac3-8a5f-f3239a400edb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262243416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4262243416
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.125672760
Short name T64
Test name
Test status
Simulation time 126158436978 ps
CPU time 304.28 seconds
Started Oct 01 12:31:45 PM PDT 23
Finished Oct 01 12:36:54 PM PDT 23
Peak memory 210928 kb
Host smart-8bcc3e5f-d51c-40aa-8357-27d47d3961b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125672760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.125672760
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.660021333
Short name T438
Test name
Test status
Simulation time 1417689401 ps
CPU time 12.83 seconds
Started Oct 01 12:31:39 PM PDT 23
Finished Oct 01 12:31:52 PM PDT 23
Peak memory 210736 kb
Host smart-2e851344-1aef-4784-84a0-11354495ccd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660021333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.660021333
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1500244557
Short name T463
Test name
Test status
Simulation time 4108313469 ps
CPU time 18.19 seconds
Started Oct 01 12:31:42 PM PDT 23
Finished Oct 01 12:32:00 PM PDT 23
Peak memory 219016 kb
Host smart-a4c5fc38-9eeb-4fec-ad39-31f0c7f36af0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500244557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1500244557
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.209051779
Short name T440
Test name
Test status
Simulation time 4447326632 ps
CPU time 11.43 seconds
Started Oct 01 12:31:34 PM PDT 23
Finished Oct 01 12:31:47 PM PDT 23
Peak memory 218980 kb
Host smart-8be0acc9-9066-479d-aa11-f70e3ac37bf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209051779 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.209051779
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1712929405
Short name T35
Test name
Test status
Simulation time 1998956320 ps
CPU time 15.74 seconds
Started Oct 01 12:31:33 PM PDT 23
Finished Oct 01 12:31:49 PM PDT 23
Peak memory 216984 kb
Host smart-b62af7dd-8446-4898-a417-6165f370f3e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712929405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1712929405
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1122402189
Short name T482
Test name
Test status
Simulation time 25812399203 ps
CPU time 277.79 seconds
Started Oct 01 12:31:45 PM PDT 23
Finished Oct 01 12:36:23 PM PDT 23
Peak memory 210660 kb
Host smart-bbfaa5f6-5037-473c-b58c-74bb7ec31d86
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122402189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1122402189
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3452383117
Short name T60
Test name
Test status
Simulation time 2033136730 ps
CPU time 16.61 seconds
Started Oct 01 12:31:56 PM PDT 23
Finished Oct 01 12:32:13 PM PDT 23
Peak memory 216976 kb
Host smart-8c189e83-f5a7-4afd-9164-079c8efd4214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452383117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3452383117
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3397570587
Short name T452
Test name
Test status
Simulation time 2062190905 ps
CPU time 49.63 seconds
Started Oct 01 12:31:36 PM PDT 23
Finished Oct 01 12:32:26 PM PDT 23
Peak memory 211824 kb
Host smart-44ff38a4-d979-4d10-90fe-af4026e350e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397570587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3397570587
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1124565275
Short name T435
Test name
Test status
Simulation time 662628780 ps
CPU time 6.5 seconds
Started Oct 01 12:32:04 PM PDT 23
Finished Oct 01 12:32:11 PM PDT 23
Peak memory 210716 kb
Host smart-b7837d51-20d9-4e83-af8d-d5a2b46e84b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124565275 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1124565275
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3079603905
Short name T484
Test name
Test status
Simulation time 2128596593 ps
CPU time 16.3 seconds
Started Oct 01 12:31:37 PM PDT 23
Finished Oct 01 12:31:53 PM PDT 23
Peak memory 210628 kb
Host smart-1dce6566-8a57-41d6-a640-7dcf2cf692c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079603905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3079603905
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.36849652
Short name T441
Test name
Test status
Simulation time 86597919763 ps
CPU time 266.27 seconds
Started Oct 01 12:31:36 PM PDT 23
Finished Oct 01 12:36:02 PM PDT 23
Peak memory 210700 kb
Host smart-28e23e22-23d3-4687-8664-28483d983f69
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36849652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pas
sthru_mem_tl_intg_err.36849652
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.107926464
Short name T483
Test name
Test status
Simulation time 1868875572 ps
CPU time 10.63 seconds
Started Oct 01 12:31:56 PM PDT 23
Finished Oct 01 12:32:06 PM PDT 23
Peak memory 218824 kb
Host smart-df3f0c3a-c36f-49c1-a1aa-32e3f2a3e7be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107926464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.107926464
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2731721950
Short name T439
Test name
Test status
Simulation time 1859548169 ps
CPU time 19.86 seconds
Started Oct 01 12:31:38 PM PDT 23
Finished Oct 01 12:31:58 PM PDT 23
Peak memory 219024 kb
Host smart-e2acc870-5495-41e8-b811-e054316e37f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731721950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2731721950
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.303878645
Short name T436
Test name
Test status
Simulation time 4391266166 ps
CPU time 9.5 seconds
Started Oct 01 12:31:45 PM PDT 23
Finished Oct 01 12:31:55 PM PDT 23
Peak memory 212792 kb
Host smart-45197505-5cfd-478a-82fb-331f34a0166a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303878645 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.303878645
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1566647015
Short name T458
Test name
Test status
Simulation time 3040797824 ps
CPU time 15.24 seconds
Started Oct 01 12:31:48 PM PDT 23
Finished Oct 01 12:32:03 PM PDT 23
Peak memory 216960 kb
Host smart-9785a1c8-52c8-4b7f-bc86-ea071c202e45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566647015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1566647015
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1263403623
Short name T67
Test name
Test status
Simulation time 47060811487 ps
CPU time 136.84 seconds
Started Oct 01 12:31:50 PM PDT 23
Finished Oct 01 12:34:07 PM PDT 23
Peak memory 218980 kb
Host smart-330dbf2d-9a11-40df-92c4-3d6b3ac58211
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263403623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1263403623
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4269596476
Short name T474
Test name
Test status
Simulation time 2194035824 ps
CPU time 12.52 seconds
Started Oct 01 12:32:13 PM PDT 23
Finished Oct 01 12:32:25 PM PDT 23
Peak memory 210688 kb
Host smart-9b6bbbce-c69a-492b-8b6d-f6737a5303f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269596476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4269596476
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1231466051
Short name T135
Test name
Test status
Simulation time 1202155338 ps
CPU time 13.22 seconds
Started Oct 01 12:31:59 PM PDT 23
Finished Oct 01 12:32:13 PM PDT 23
Peak memory 218948 kb
Host smart-755a8c7c-a5f7-4943-81d2-9bef1b29c4fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231466051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1231466051
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.273203540
Short name T111
Test name
Test status
Simulation time 5606685014 ps
CPU time 77.28 seconds
Started Oct 01 12:31:34 PM PDT 23
Finished Oct 01 12:32:51 PM PDT 23
Peak memory 211280 kb
Host smart-03ec629f-07eb-4861-88b1-1127988bc645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273203540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.273203540
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.286666890
Short name T117
Test name
Test status
Simulation time 802170820 ps
CPU time 10.58 seconds
Started Oct 01 12:31:29 PM PDT 23
Finished Oct 01 12:31:41 PM PDT 23
Peak memory 218864 kb
Host smart-8ffeb5fe-7b30-4d7b-bd27-972255c1b805
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286666890 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.286666890
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.993368689
Short name T122
Test name
Test status
Simulation time 463279930 ps
CPU time 4.13 seconds
Started Oct 01 12:31:16 PM PDT 23
Finished Oct 01 12:31:26 PM PDT 23
Peak memory 210632 kb
Host smart-152bb108-df32-4d27-b636-7943541a1cd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993368689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.993368689
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2233480342
Short name T65
Test name
Test status
Simulation time 11418021901 ps
CPU time 91.37 seconds
Started Oct 01 12:31:57 PM PDT 23
Finished Oct 01 12:33:29 PM PDT 23
Peak memory 218856 kb
Host smart-9d9c4d9c-5612-48a3-9a35-7a4a78c9c3b6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233480342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2233480342
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3850809399
Short name T140
Test name
Test status
Simulation time 902646658 ps
CPU time 9.8 seconds
Started Oct 01 12:31:39 PM PDT 23
Finished Oct 01 12:31:49 PM PDT 23
Peak memory 217556 kb
Host smart-bab3b8eb-ffb4-4552-9bed-f62307eac974
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850809399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3850809399
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1556536035
Short name T42
Test name
Test status
Simulation time 386679434 ps
CPU time 6.96 seconds
Started Oct 01 12:31:25 PM PDT 23
Finished Oct 01 12:31:32 PM PDT 23
Peak memory 218952 kb
Host smart-ed3a8ed2-5c21-4c6a-9dba-bb9f57c1a333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556536035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1556536035
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2191797395
Short name T44
Test name
Test status
Simulation time 26856632462 ps
CPU time 86.26 seconds
Started Oct 01 12:32:09 PM PDT 23
Finished Oct 01 12:33:35 PM PDT 23
Peak memory 212292 kb
Host smart-105bf1c9-9d0c-430a-a385-eb388d6a2ec4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191797395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2191797395
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.668016494
Short name T466
Test name
Test status
Simulation time 333975760 ps
CPU time 4.7 seconds
Started Oct 01 12:32:14 PM PDT 23
Finished Oct 01 12:32:19 PM PDT 23
Peak memory 213388 kb
Host smart-d249eb3e-0565-47bf-9c01-798fb33c8def
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668016494 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.668016494
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1230504179
Short name T481
Test name
Test status
Simulation time 1557899843 ps
CPU time 13.3 seconds
Started Oct 01 12:31:22 PM PDT 23
Finished Oct 01 12:31:36 PM PDT 23
Peak memory 210604 kb
Host smart-aa4a52f5-7210-46c4-b389-174e347736cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230504179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1230504179
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4047899170
Short name T83
Test name
Test status
Simulation time 87299346561 ps
CPU time 121.33 seconds
Started Oct 01 12:31:41 PM PDT 23
Finished Oct 01 12:33:43 PM PDT 23
Peak memory 218980 kb
Host smart-a187683a-82c9-4214-8a6e-fcdad6b9c9d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047899170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4047899170
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3568477184
Short name T146
Test name
Test status
Simulation time 1683475124 ps
CPU time 14.32 seconds
Started Oct 01 12:31:50 PM PDT 23
Finished Oct 01 12:32:05 PM PDT 23
Peak memory 210740 kb
Host smart-00a7a064-8835-4b7c-bd8d-997c899302a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568477184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3568477184
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.940249418
Short name T59
Test name
Test status
Simulation time 1554300762 ps
CPU time 17.36 seconds
Started Oct 01 12:31:44 PM PDT 23
Finished Oct 01 12:32:02 PM PDT 23
Peak memory 214532 kb
Host smart-ee917ba0-7a19-41e7-aa38-c4984b206b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940249418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.940249418
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3416134294
Short name T105
Test name
Test status
Simulation time 599911622 ps
CPU time 76 seconds
Started Oct 01 12:32:01 PM PDT 23
Finished Oct 01 12:33:18 PM PDT 23
Peak memory 210992 kb
Host smart-6b2ddeff-8c42-4436-85ea-e9f162448451
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416134294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3416134294
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2286283998
Short name T462
Test name
Test status
Simulation time 2072466586 ps
CPU time 16.52 seconds
Started Oct 01 12:31:44 PM PDT 23
Finished Oct 01 12:32:01 PM PDT 23
Peak memory 218968 kb
Host smart-336c1c6b-da42-4ca4-9820-b0a0f69486f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286283998 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2286283998
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1479382881
Short name T30
Test name
Test status
Simulation time 1572420284 ps
CPU time 13.06 seconds
Started Oct 01 12:31:34 PM PDT 23
Finished Oct 01 12:31:47 PM PDT 23
Peak memory 216892 kb
Host smart-3645c394-6bd8-4d86-aa67-5adf73520df4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479382881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1479382881
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.971937787
Short name T63
Test name
Test status
Simulation time 141812896425 ps
CPU time 304.33 seconds
Started Oct 01 12:32:13 PM PDT 23
Finished Oct 01 12:37:18 PM PDT 23
Peak memory 210692 kb
Host smart-ec7ffbac-2dd2-43a2-9bf7-3f7e8b80af72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971937787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.971937787
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2373952094
Short name T141
Test name
Test status
Simulation time 439537054 ps
CPU time 7.56 seconds
Started Oct 01 12:31:37 PM PDT 23
Finished Oct 01 12:31:45 PM PDT 23
Peak memory 210748 kb
Host smart-c3caf020-66c8-47fd-bb31-d24c912f1192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373952094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2373952094
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.666771927
Short name T132
Test name
Test status
Simulation time 295560619 ps
CPU time 9.6 seconds
Started Oct 01 12:31:33 PM PDT 23
Finished Oct 01 12:31:43 PM PDT 23
Peak memory 214656 kb
Host smart-b0fb3243-ea4d-4c24-8333-030364c9bdf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666771927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.666771927
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2298390552
Short name T459
Test name
Test status
Simulation time 1696926281 ps
CPU time 14.28 seconds
Started Oct 01 12:31:35 PM PDT 23
Finished Oct 01 12:31:50 PM PDT 23
Peak memory 218808 kb
Host smart-29b1a45f-79ac-4540-be02-af31effcf97b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298390552 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2298390552
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1351194246
Short name T137
Test name
Test status
Simulation time 1329041639 ps
CPU time 11.58 seconds
Started Oct 01 12:31:34 PM PDT 23
Finished Oct 01 12:31:45 PM PDT 23
Peak memory 210736 kb
Host smart-54d6b0a6-69be-4831-a936-4a786d19c919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351194246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1351194246
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.868140630
Short name T61
Test name
Test status
Simulation time 227329247 ps
CPU time 7.62 seconds
Started Oct 01 12:31:29 PM PDT 23
Finished Oct 01 12:31:38 PM PDT 23
Peak memory 218720 kb
Host smart-1547da79-50d1-492e-b096-dd5a19d3376b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868140630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.868140630
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2547486320
Short name T442
Test name
Test status
Simulation time 2042781886 ps
CPU time 20.45 seconds
Started Oct 01 12:32:01 PM PDT 23
Finished Oct 01 12:32:22 PM PDT 23
Peak memory 218816 kb
Host smart-421667c4-06cf-446c-8f89-73bf8ca4e085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547486320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2547486320
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3425652005
Short name T460
Test name
Test status
Simulation time 137504234 ps
CPU time 5.42 seconds
Started Oct 01 12:32:30 PM PDT 23
Finished Oct 01 12:32:36 PM PDT 23
Peak memory 211808 kb
Host smart-3098e035-e3bd-428f-b882-50abf9cb079e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425652005 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3425652005
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4264467391
Short name T480
Test name
Test status
Simulation time 2046297896 ps
CPU time 15.74 seconds
Started Oct 01 12:32:03 PM PDT 23
Finished Oct 01 12:32:18 PM PDT 23
Peak memory 217236 kb
Host smart-5557e20c-d3b9-4852-a732-091d46d0c2ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264467391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4264467391
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1006483791
Short name T456
Test name
Test status
Simulation time 988398301 ps
CPU time 50.77 seconds
Started Oct 01 12:32:10 PM PDT 23
Finished Oct 01 12:33:01 PM PDT 23
Peak memory 210648 kb
Host smart-31b54ae4-2b48-4256-99ce-21e2d6293b51
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006483791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1006483791
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1064768399
Short name T74
Test name
Test status
Simulation time 865014903 ps
CPU time 9.66 seconds
Started Oct 01 12:32:13 PM PDT 23
Finished Oct 01 12:32:23 PM PDT 23
Peak memory 210732 kb
Host smart-fcd9ac14-5fd0-49ff-ae9e-5eb90f31fb79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064768399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1064768399
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1831137504
Short name T446
Test name
Test status
Simulation time 3591882224 ps
CPU time 17.26 seconds
Started Oct 01 12:31:59 PM PDT 23
Finished Oct 01 12:32:16 PM PDT 23
Peak memory 218984 kb
Host smart-0dca368a-649b-488c-ba1f-63e74b987848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831137504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1831137504
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3025257093
Short name T55
Test name
Test status
Simulation time 1303470687 ps
CPU time 45.54 seconds
Started Oct 01 12:31:41 PM PDT 23
Finished Oct 01 12:32:27 PM PDT 23
Peak memory 217788 kb
Host smart-e37712de-bba3-4fcb-9837-c25a47d693ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025257093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3025257093
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.192231779
Short name T479
Test name
Test status
Simulation time 217090620 ps
CPU time 6.06 seconds
Started Oct 01 12:31:47 PM PDT 23
Finished Oct 01 12:31:59 PM PDT 23
Peak memory 218776 kb
Host smart-5752dda2-95b3-4daf-815b-f84e2ba6b0eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192231779 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.192231779
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3276465329
Short name T126
Test name
Test status
Simulation time 719753132 ps
CPU time 8.69 seconds
Started Oct 01 12:32:15 PM PDT 23
Finished Oct 01 12:32:24 PM PDT 23
Peak memory 210724 kb
Host smart-53138d44-5df9-4cc2-abb6-35422a933702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276465329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3276465329
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1752144576
Short name T36
Test name
Test status
Simulation time 40431947763 ps
CPU time 342.3 seconds
Started Oct 01 12:32:18 PM PDT 23
Finished Oct 01 12:38:00 PM PDT 23
Peak memory 218820 kb
Host smart-4f767dec-e80d-42a4-ac86-9d7409dff611
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752144576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1752144576
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.430938854
Short name T99
Test name
Test status
Simulation time 462594720 ps
CPU time 4.35 seconds
Started Oct 01 12:32:19 PM PDT 23
Finished Oct 01 12:32:24 PM PDT 23
Peak memory 216388 kb
Host smart-abd96249-1938-4a9c-b7e1-c931a9c3422a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430938854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.430938854
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1752700134
Short name T58
Test name
Test status
Simulation time 3769613547 ps
CPU time 13.99 seconds
Started Oct 01 12:31:44 PM PDT 23
Finished Oct 01 12:31:58 PM PDT 23
Peak memory 214516 kb
Host smart-1fc9bc1c-59f2-4eec-bbdc-1cd051ee82c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752700134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1752700134
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1317068957
Short name T108
Test name
Test status
Simulation time 2819088634 ps
CPU time 78.07 seconds
Started Oct 01 12:32:37 PM PDT 23
Finished Oct 01 12:33:55 PM PDT 23
Peak memory 218892 kb
Host smart-6b0c82e2-355c-4adb-a6c3-98f446c174a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317068957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1317068957
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2332236832
Short name T34
Test name
Test status
Simulation time 1093163930 ps
CPU time 7.73 seconds
Started Oct 01 12:19:41 PM PDT 23
Finished Oct 01 12:19:49 PM PDT 23
Peak memory 217120 kb
Host smart-e933a100-026e-441d-b5c9-85349f209d42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332236832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2332236832
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2666271298
Short name T31
Test name
Test status
Simulation time 199456509 ps
CPU time 4.4 seconds
Started Oct 01 12:22:18 PM PDT 23
Finished Oct 01 12:22:22 PM PDT 23
Peak memory 215588 kb
Host smart-8d5c946b-29f0-4954-b349-b5960ffd1aa7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666271298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2666271298
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2360673631
Short name T120
Test name
Test status
Simulation time 3891942898 ps
CPU time 10.4 seconds
Started Oct 01 12:20:56 PM PDT 23
Finished Oct 01 12:21:07 PM PDT 23
Peak memory 210632 kb
Host smart-bfd3f29e-25b4-458b-be0c-515ac46db54e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360673631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2360673631
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3636556211
Short name T471
Test name
Test status
Simulation time 11741819445 ps
CPU time 12.69 seconds
Started Oct 01 12:19:50 PM PDT 23
Finished Oct 01 12:20:03 PM PDT 23
Peak memory 218852 kb
Host smart-5d5dd988-a24f-4105-a579-345209aba471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636556211 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3636556211
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1277775060
Short name T472
Test name
Test status
Simulation time 209105302 ps
CPU time 5.8 seconds
Started Oct 01 12:19:56 PM PDT 23
Finished Oct 01 12:20:02 PM PDT 23
Peak memory 215788 kb
Host smart-81406aac-9709-453b-9d46-6f135c4f79be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277775060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1277775060
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.429867265
Short name T473
Test name
Test status
Simulation time 857948292 ps
CPU time 7.12 seconds
Started Oct 01 12:19:28 PM PDT 23
Finished Oct 01 12:19:35 PM PDT 23
Peak memory 210696 kb
Host smart-e9d1086c-e87e-4877-8345-594e56dc0c62
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429867265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.429867265
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3244107548
Short name T461
Test name
Test status
Simulation time 1513470868 ps
CPU time 11.96 seconds
Started Oct 01 12:22:27 PM PDT 23
Finished Oct 01 12:22:39 PM PDT 23
Peak memory 210648 kb
Host smart-c48a5f50-13f3-4889-9b83-c23dc24f278f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244107548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3244107548
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3662223086
Short name T464
Test name
Test status
Simulation time 37658016689 ps
CPU time 162.35 seconds
Started Oct 01 12:19:22 PM PDT 23
Finished Oct 01 12:22:05 PM PDT 23
Peak memory 210952 kb
Host smart-af229b3f-acd9-4ebf-920d-5c2b53c5cb2f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662223086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3662223086
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1143234845
Short name T100
Test name
Test status
Simulation time 199979409 ps
CPU time 4.37 seconds
Started Oct 01 12:20:28 PM PDT 23
Finished Oct 01 12:20:33 PM PDT 23
Peak memory 216092 kb
Host smart-320c5189-e4e4-4e36-981a-4eef8714c6d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143234845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1143234845
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1525894496
Short name T477
Test name
Test status
Simulation time 5622835253 ps
CPU time 45.45 seconds
Started Oct 01 12:20:55 PM PDT 23
Finished Oct 01 12:21:46 PM PDT 23
Peak memory 218860 kb
Host smart-61c0cae2-19d5-457d-b42f-7c9eac64394d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525894496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1525894496
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3069921598
Short name T449
Test name
Test status
Simulation time 164900308 ps
CPU time 4.62 seconds
Started Oct 01 12:21:06 PM PDT 23
Finished Oct 01 12:21:12 PM PDT 23
Peak memory 214796 kb
Host smart-a09208ab-957f-4e26-9237-71792a147821
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069921598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3069921598
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4207614004
Short name T465
Test name
Test status
Simulation time 867899341 ps
CPU time 7.57 seconds
Started Oct 01 12:19:40 PM PDT 23
Finished Oct 01 12:19:49 PM PDT 23
Peak memory 218280 kb
Host smart-9cfee5b0-5378-46dc-b20d-ae107113307f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207614004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4207614004
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1830538805
Short name T54
Test name
Test status
Simulation time 385983852 ps
CPU time 6.07 seconds
Started Oct 01 12:26:54 PM PDT 23
Finished Oct 01 12:27:01 PM PDT 23
Peak memory 218852 kb
Host smart-e9ee40b3-1b48-4927-bf82-8ff52de36269
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830538805 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1830538805
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.19116443
Short name T123
Test name
Test status
Simulation time 378707633 ps
CPU time 4.41 seconds
Started Oct 01 12:19:23 PM PDT 23
Finished Oct 01 12:19:27 PM PDT 23
Peak memory 215032 kb
Host smart-555d68d8-b07e-4963-9a1f-4356128fd1bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19116443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.19116443
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1810801111
Short name T476
Test name
Test status
Simulation time 1665475905 ps
CPU time 8.66 seconds
Started Oct 01 12:20:44 PM PDT 23
Finished Oct 01 12:20:54 PM PDT 23
Peak memory 210404 kb
Host smart-898e3204-3afb-4258-bb8e-e0b7686ef2c6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810801111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1810801111
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1386684890
Short name T445
Test name
Test status
Simulation time 2414786794 ps
CPU time 9.9 seconds
Started Oct 01 12:20:48 PM PDT 23
Finished Oct 01 12:20:58 PM PDT 23
Peak memory 209976 kb
Host smart-18f2fd14-62b7-4931-8419-ac0a009ff468
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386684890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1386684890
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.383093802
Short name T467
Test name
Test status
Simulation time 8220382246 ps
CPU time 155.79 seconds
Started Oct 01 12:20:50 PM PDT 23
Finished Oct 01 12:23:26 PM PDT 23
Peak memory 209896 kb
Host smart-48667a06-3f5a-4c3b-b37c-9d0f4719778c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383093802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.383093802
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1493660205
Short name T143
Test name
Test status
Simulation time 7999191415 ps
CPU time 17.06 seconds
Started Oct 01 12:21:36 PM PDT 23
Finished Oct 01 12:21:53 PM PDT 23
Peak memory 210664 kb
Host smart-b735a541-0815-4aa5-a4dc-1d38dd4509f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493660205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1493660205
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1183889526
Short name T138
Test name
Test status
Simulation time 87366101 ps
CPU time 6.7 seconds
Started Oct 01 12:20:47 PM PDT 23
Finished Oct 01 12:20:54 PM PDT 23
Peak memory 218116 kb
Host smart-b752c3db-a128-40ad-9ea7-94d0fdbe7922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183889526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1183889526
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1006773505
Short name T116
Test name
Test status
Simulation time 2308999574 ps
CPU time 49.55 seconds
Started Oct 01 12:21:17 PM PDT 23
Finished Oct 01 12:22:07 PM PDT 23
Peak memory 218860 kb
Host smart-6aa5c703-38a1-400f-ab18-6015ae4bcf5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006773505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1006773505
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1996330821
Short name T478
Test name
Test status
Simulation time 1983501949 ps
CPU time 15.78 seconds
Started Oct 01 12:15:56 PM PDT 23
Finished Oct 01 12:16:12 PM PDT 23
Peak memory 210704 kb
Host smart-62a822ee-52b7-46d0-b970-9b4cc3b0a02d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996330821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1996330821
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.220115376
Short name T475
Test name
Test status
Simulation time 5085907588 ps
CPU time 11.29 seconds
Started Oct 01 12:20:35 PM PDT 23
Finished Oct 01 12:20:46 PM PDT 23
Peak memory 216356 kb
Host smart-d61fc527-ca6d-4703-bf85-b2a75b23267e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220115376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.220115376
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1372072004
Short name T75
Test name
Test status
Simulation time 246778896 ps
CPU time 8.04 seconds
Started Oct 01 12:16:50 PM PDT 23
Finished Oct 01 12:16:58 PM PDT 23
Peak memory 210752 kb
Host smart-393beeae-86cd-4c30-a538-996dd00ef033
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372072004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1372072004
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2823419683
Short name T127
Test name
Test status
Simulation time 791012761 ps
CPU time 4.49 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:29 PM PDT 23
Peak memory 212540 kb
Host smart-f7997033-6b95-436d-8b7a-93447277f331
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823419683 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2823419683
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.451169197
Short name T437
Test name
Test status
Simulation time 170191649 ps
CPU time 5.16 seconds
Started Oct 01 12:19:47 PM PDT 23
Finished Oct 01 12:19:52 PM PDT 23
Peak memory 216400 kb
Host smart-c6018b1b-26b5-4595-8ab4-58fe26ada7e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451169197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.451169197
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3043165316
Short name T84
Test name
Test status
Simulation time 1358325637 ps
CPU time 11.6 seconds
Started Oct 01 12:21:04 PM PDT 23
Finished Oct 01 12:21:16 PM PDT 23
Peak memory 209920 kb
Host smart-18e36e6d-9ac5-4e0a-a836-48000fc58012
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043165316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3043165316
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2455442221
Short name T451
Test name
Test status
Simulation time 259297619 ps
CPU time 6.11 seconds
Started Oct 01 12:18:37 PM PDT 23
Finished Oct 01 12:18:43 PM PDT 23
Peak memory 210900 kb
Host smart-da4eceb2-78bb-4554-a889-a6eac94b140e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455442221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2455442221
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3793699138
Short name T81
Test name
Test status
Simulation time 10942428264 ps
CPU time 96.11 seconds
Started Oct 01 12:19:30 PM PDT 23
Finished Oct 01 12:21:07 PM PDT 23
Peak memory 218656 kb
Host smart-ae09acbd-a8b3-4d81-a45d-b341d5948dc5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793699138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3793699138
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1263803062
Short name T86
Test name
Test status
Simulation time 934304984 ps
CPU time 11.19 seconds
Started Oct 01 12:31:45 PM PDT 23
Finished Oct 01 12:31:57 PM PDT 23
Peak memory 210692 kb
Host smart-00b6b464-e6c7-40b8-a701-13d1f1379a95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263803062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1263803062
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1513646206
Short name T434
Test name
Test status
Simulation time 974668693 ps
CPU time 9.81 seconds
Started Oct 01 12:31:58 PM PDT 23
Finished Oct 01 12:32:08 PM PDT 23
Peak memory 218916 kb
Host smart-d25e02b8-c103-4c51-bde8-8ac6b2565a26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513646206 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1513646206
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3519109150
Short name T73
Test name
Test status
Simulation time 1027545529 ps
CPU time 10.34 seconds
Started Oct 01 12:31:37 PM PDT 23
Finished Oct 01 12:31:48 PM PDT 23
Peak memory 217076 kb
Host smart-84584659-5b66-4bdd-93f5-d7a29f8450d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519109150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3519109150
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4204514640
Short name T88
Test name
Test status
Simulation time 9884833956 ps
CPU time 167.26 seconds
Started Oct 01 12:31:51 PM PDT 23
Finished Oct 01 12:34:38 PM PDT 23
Peak memory 219016 kb
Host smart-452d08d6-8008-4f7d-96b0-39dd81cf6460
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204514640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4204514640
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2077673406
Short name T124
Test name
Test status
Simulation time 6933766809 ps
CPU time 15.94 seconds
Started Oct 01 12:31:47 PM PDT 23
Finished Oct 01 12:32:03 PM PDT 23
Peak memory 217084 kb
Host smart-a96fac33-bf0a-4d29-9ec6-97083eda01fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077673406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2077673406
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1530645284
Short name T104
Test name
Test status
Simulation time 694274668 ps
CPU time 10.38 seconds
Started Oct 01 12:32:22 PM PDT 23
Finished Oct 01 12:32:33 PM PDT 23
Peak memory 218964 kb
Host smart-22419151-a8d2-4db8-a382-45e7fff52334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530645284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1530645284
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2379767468
Short name T33
Test name
Test status
Simulation time 669713503 ps
CPU time 41.19 seconds
Started Oct 01 12:32:02 PM PDT 23
Finished Oct 01 12:32:43 PM PDT 23
Peak memory 211932 kb
Host smart-01b4d156-2df0-4fab-b4a6-9c564cffa4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379767468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2379767468
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3618016608
Short name T443
Test name
Test status
Simulation time 6824315057 ps
CPU time 12.25 seconds
Started Oct 01 12:31:42 PM PDT 23
Finished Oct 01 12:31:54 PM PDT 23
Peak memory 212428 kb
Host smart-6ee1d4c4-034b-4fce-8c5a-a0ef4e4a9e8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618016608 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3618016608
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1511373683
Short name T448
Test name
Test status
Simulation time 1693286852 ps
CPU time 13.71 seconds
Started Oct 01 12:32:03 PM PDT 23
Finished Oct 01 12:32:22 PM PDT 23
Peak memory 216868 kb
Host smart-d6180cce-4531-4be3-9b79-0f1ea064003c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511373683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1511373683
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2684052510
Short name T76
Test name
Test status
Simulation time 18985350773 ps
CPU time 175.72 seconds
Started Oct 01 12:31:39 PM PDT 23
Finished Oct 01 12:34:35 PM PDT 23
Peak memory 210800 kb
Host smart-a0965348-ec6f-426c-90f2-82a5f5e19187
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684052510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2684052510
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.404571367
Short name T455
Test name
Test status
Simulation time 1751035157 ps
CPU time 14.09 seconds
Started Oct 01 12:31:41 PM PDT 23
Finished Oct 01 12:31:55 PM PDT 23
Peak memory 210692 kb
Host smart-18d468f6-9ad2-4f4a-92a7-3f09423e97ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404571367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.404571367
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2285220908
Short name T129
Test name
Test status
Simulation time 1153994381 ps
CPU time 10.45 seconds
Started Oct 01 12:32:21 PM PDT 23
Finished Oct 01 12:32:32 PM PDT 23
Peak memory 218936 kb
Host smart-f7b4091e-fe1d-404d-bb30-748c5adcd0c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285220908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2285220908
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3290407899
Short name T110
Test name
Test status
Simulation time 800539161 ps
CPU time 40.17 seconds
Started Oct 01 12:32:28 PM PDT 23
Finished Oct 01 12:33:09 PM PDT 23
Peak memory 218060 kb
Host smart-567f117a-669a-4ad9-8c7e-ae962d201d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290407899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3290407899
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2078151573
Short name T45
Test name
Test status
Simulation time 350375397 ps
CPU time 4.27 seconds
Started Oct 01 12:31:37 PM PDT 23
Finished Oct 01 12:31:41 PM PDT 23
Peak memory 210824 kb
Host smart-7dc76881-ec18-4660-9d79-fe63b5bd98f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078151573 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2078151573
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3562989088
Short name T131
Test name
Test status
Simulation time 12816914178 ps
CPU time 15.84 seconds
Started Oct 01 12:31:36 PM PDT 23
Finished Oct 01 12:31:52 PM PDT 23
Peak memory 210748 kb
Host smart-79dfafac-07d8-4f5e-9e97-d6732317f0cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562989088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3562989088
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.300265132
Short name T68
Test name
Test status
Simulation time 1936882467 ps
CPU time 50.94 seconds
Started Oct 01 12:31:32 PM PDT 23
Finished Oct 01 12:32:24 PM PDT 23
Peak memory 218076 kb
Host smart-512ee70c-6487-4a6d-bfec-5f641f5135f2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300265132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.300265132
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2447883155
Short name T142
Test name
Test status
Simulation time 93982772 ps
CPU time 6.26 seconds
Started Oct 01 12:31:53 PM PDT 23
Finished Oct 01 12:31:59 PM PDT 23
Peak memory 210748 kb
Host smart-5d08667a-aebc-499c-a801-cfe08c8ac9c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447883155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2447883155
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2740897718
Short name T453
Test name
Test status
Simulation time 214226043 ps
CPU time 9.64 seconds
Started Oct 01 12:31:40 PM PDT 23
Finished Oct 01 12:31:51 PM PDT 23
Peak memory 218960 kb
Host smart-b7978aa7-4bcb-4fd6-84d9-409e79703fba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740897718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2740897718
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4080418250
Short name T107
Test name
Test status
Simulation time 237998789 ps
CPU time 75.36 seconds
Started Oct 01 12:31:36 PM PDT 23
Finished Oct 01 12:32:52 PM PDT 23
Peak memory 213000 kb
Host smart-aa2cb976-dda8-4669-9f34-e869b1b4deb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080418250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4080418250
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1701029510
Short name T128
Test name
Test status
Simulation time 1655442559 ps
CPU time 14.15 seconds
Started Oct 01 12:31:57 PM PDT 23
Finished Oct 01 12:32:16 PM PDT 23
Peak memory 215212 kb
Host smart-4f36ce2e-97fa-4451-bcbc-255d6f494435
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701029510 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1701029510
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2662892124
Short name T470
Test name
Test status
Simulation time 1111079182 ps
CPU time 7.84 seconds
Started Oct 01 12:31:32 PM PDT 23
Finished Oct 01 12:31:41 PM PDT 23
Peak memory 216176 kb
Host smart-928458b1-92fe-4633-a83f-38fc1561763c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662892124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2662892124
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2023100063
Short name T66
Test name
Test status
Simulation time 13654460232 ps
CPU time 127.33 seconds
Started Oct 01 12:31:25 PM PDT 23
Finished Oct 01 12:33:33 PM PDT 23
Peak memory 210688 kb
Host smart-f49f7787-ba85-451c-845e-eb8c9adb9ec0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023100063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2023100063
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.838005790
Short name T144
Test name
Test status
Simulation time 1987275576 ps
CPU time 7.73 seconds
Started Oct 01 12:31:53 PM PDT 23
Finished Oct 01 12:32:01 PM PDT 23
Peak memory 210644 kb
Host smart-edb11524-115b-415f-a6a4-b9013289df94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838005790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.838005790
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3204061824
Short name T134
Test name
Test status
Simulation time 10381741175 ps
CPU time 18.09 seconds
Started Oct 01 12:31:17 PM PDT 23
Finished Oct 01 12:31:35 PM PDT 23
Peak memory 218924 kb
Host smart-26e60ffb-a439-4f46-a987-50c9e4ebe743
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204061824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3204061824
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.688172886
Short name T113
Test name
Test status
Simulation time 1179428555 ps
CPU time 77.49 seconds
Started Oct 01 12:31:16 PM PDT 23
Finished Oct 01 12:32:34 PM PDT 23
Peak memory 210880 kb
Host smart-2b7a0192-a6d2-4f0e-9736-efcd258501da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688172886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.688172886
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3704440919
Short name T145
Test name
Test status
Simulation time 4637000419 ps
CPU time 11.33 seconds
Started Oct 01 12:31:46 PM PDT 23
Finished Oct 01 12:31:58 PM PDT 23
Peak memory 213644 kb
Host smart-ad5564af-464b-4b03-85c0-1eb3a1ebdc05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704440919 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3704440919
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.855517073
Short name T29
Test name
Test status
Simulation time 4635423367 ps
CPU time 8.82 seconds
Started Oct 01 12:31:36 PM PDT 23
Finished Oct 01 12:31:45 PM PDT 23
Peak memory 210668 kb
Host smart-ddb37abb-1fb4-4201-b8de-da27fc337e06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855517073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.855517073
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4039988167
Short name T69
Test name
Test status
Simulation time 3123108978 ps
CPU time 50.69 seconds
Started Oct 01 12:31:49 PM PDT 23
Finished Oct 01 12:32:40 PM PDT 23
Peak memory 210700 kb
Host smart-3b0ddb69-4433-45c4-8600-120756a1cbff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039988167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.4039988167
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2274248678
Short name T87
Test name
Test status
Simulation time 11687969508 ps
CPU time 9.81 seconds
Started Oct 01 12:31:33 PM PDT 23
Finished Oct 01 12:31:43 PM PDT 23
Peak memory 210796 kb
Host smart-40ea9bf0-96ff-41ff-b18e-cacaba49d377
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274248678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2274248678
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3399487894
Short name T457
Test name
Test status
Simulation time 34680263928 ps
CPU time 17.34 seconds
Started Oct 01 12:31:25 PM PDT 23
Finished Oct 01 12:31:42 PM PDT 23
Peak memory 219044 kb
Host smart-96996557-9ce4-47cb-8f9c-ee608e91bd8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399487894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3399487894
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2249804757
Short name T115
Test name
Test status
Simulation time 1905617321 ps
CPU time 81.93 seconds
Started Oct 01 12:31:28 PM PDT 23
Finished Oct 01 12:32:50 PM PDT 23
Peak memory 210880 kb
Host smart-d5e876ae-1131-467e-bcd4-3d17523fe426
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249804757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2249804757
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.260726384
Short name T270
Test name
Test status
Simulation time 3269368448 ps
CPU time 9.11 seconds
Started Oct 01 12:20:26 PM PDT 23
Finished Oct 01 12:20:35 PM PDT 23
Peak memory 211052 kb
Host smart-acac206f-a0b7-4d0c-ab67-519f18a30cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260726384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.260726384
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3445745715
Short name T284
Test name
Test status
Simulation time 41536880753 ps
CPU time 128.16 seconds
Started Oct 01 12:15:19 PM PDT 23
Finished Oct 01 12:17:27 PM PDT 23
Peak memory 236752 kb
Host smart-52290b6a-8576-4087-9017-9bae1fbfbdd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445745715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3445745715
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3906195892
Short name T294
Test name
Test status
Simulation time 4758028436 ps
CPU time 23.78 seconds
Started Oct 01 12:18:25 PM PDT 23
Finished Oct 01 12:18:49 PM PDT 23
Peak memory 210016 kb
Host smart-eb41bcb4-9382-4f17-8dfe-74637646d5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906195892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3906195892
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.178929703
Short name T238
Test name
Test status
Simulation time 6866146492 ps
CPU time 16.44 seconds
Started Oct 01 12:15:54 PM PDT 23
Finished Oct 01 12:16:11 PM PDT 23
Peak memory 211116 kb
Host smart-0ddde61b-d72d-4884-8c89-fd29297d137c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=178929703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.178929703
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.229735684
Short name T47
Test name
Test status
Simulation time 2165510753 ps
CPU time 68.44 seconds
Started Oct 01 12:15:48 PM PDT 23
Finished Oct 01 12:16:57 PM PDT 23
Peak memory 235840 kb
Host smart-ec05f63a-29a0-4166-a92b-ea4a34f1a01c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229735684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.229735684
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2488078372
Short name T164
Test name
Test status
Simulation time 16471799323 ps
CPU time 40.56 seconds
Started Oct 01 12:17:12 PM PDT 23
Finished Oct 01 12:17:53 PM PDT 23
Peak memory 213968 kb
Host smart-1e698309-614c-443e-a8c8-7c3d1ed9547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488078372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2488078372
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4276982657
Short name T251
Test name
Test status
Simulation time 57582192812 ps
CPU time 57.53 seconds
Started Oct 01 12:17:33 PM PDT 23
Finished Oct 01 12:18:31 PM PDT 23
Peak memory 215984 kb
Host smart-db3e7997-5b9b-4870-b9b7-ede3903930b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276982657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4276982657
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.354138218
Short name T266
Test name
Test status
Simulation time 404363957012 ps
CPU time 3570.24 seconds
Started Oct 01 12:22:38 PM PDT 23
Finished Oct 01 01:22:09 PM PDT 23
Peak memory 251220 kb
Host smart-01c51df3-4d3c-4b2f-9900-87f87b135005
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354138218 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.354138218
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.510637905
Short name T375
Test name
Test status
Simulation time 3591606402 ps
CPU time 14.15 seconds
Started Oct 01 12:19:38 PM PDT 23
Finished Oct 01 12:19:52 PM PDT 23
Peak memory 210980 kb
Host smart-76edfc23-b638-4726-82f1-a53d1c5f6625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510637905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.510637905
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.237744748
Short name T277
Test name
Test status
Simulation time 7752656723 ps
CPU time 95.97 seconds
Started Oct 01 12:20:22 PM PDT 23
Finished Oct 01 12:21:59 PM PDT 23
Peak memory 212252 kb
Host smart-88c74b80-0793-452a-b0a0-86ff78f9c2b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237744748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.237744748
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2268273494
Short name T391
Test name
Test status
Simulation time 16416375812 ps
CPU time 33.04 seconds
Started Oct 01 12:18:40 PM PDT 23
Finished Oct 01 12:19:13 PM PDT 23
Peak memory 211196 kb
Host smart-68d9a038-3b16-4206-9b1b-7dfe79b82345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268273494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2268273494
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2127131351
Short name T27
Test name
Test status
Simulation time 197184542 ps
CPU time 5.54 seconds
Started Oct 01 12:19:33 PM PDT 23
Finished Oct 01 12:19:39 PM PDT 23
Peak memory 210636 kb
Host smart-0a596758-f308-49f6-ab37-e4023df39ce1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127131351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2127131351
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2199609672
Short name T38
Test name
Test status
Simulation time 4519926163 ps
CPU time 64.7 seconds
Started Oct 01 12:15:03 PM PDT 23
Finished Oct 01 12:16:07 PM PDT 23
Peak memory 237676 kb
Host smart-b816ea94-7f67-4ef5-a7e2-27f0f661762e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199609672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2199609672
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2042294824
Short name T312
Test name
Test status
Simulation time 2208559905 ps
CPU time 17.29 seconds
Started Oct 01 12:16:10 PM PDT 23
Finished Oct 01 12:16:28 PM PDT 23
Peak memory 212692 kb
Host smart-4b42ffca-2a74-48ea-bdce-6278da4c4afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042294824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2042294824
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3680648309
Short name T319
Test name
Test status
Simulation time 7900802619 ps
CPU time 20.45 seconds
Started Oct 01 12:18:25 PM PDT 23
Finished Oct 01 12:18:46 PM PDT 23
Peak memory 213052 kb
Host smart-d74f62a9-5352-4bf3-9e1b-2d4aa94ddad9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680648309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3680648309
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2874165629
Short name T98
Test name
Test status
Simulation time 224601640224 ps
CPU time 8321.22 seconds
Started Oct 01 12:15:07 PM PDT 23
Finished Oct 01 02:33:50 PM PDT 23
Peak memory 236124 kb
Host smart-2fc93250-ff42-41ca-8806-f82aecc6b905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874165629 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2874165629
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2579987075
Short name T307
Test name
Test status
Simulation time 49939472084 ps
CPU time 472.62 seconds
Started Oct 01 12:31:08 PM PDT 23
Finished Oct 01 12:39:01 PM PDT 23
Peak memory 237484 kb
Host smart-f1710b17-816f-475d-bb1b-98d63329c9c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579987075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2579987075
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3875919273
Short name T221
Test name
Test status
Simulation time 19345973981 ps
CPU time 35.03 seconds
Started Oct 01 12:30:43 PM PDT 23
Finished Oct 01 12:31:18 PM PDT 23
Peak memory 211512 kb
Host smart-31dad4b6-2040-49f4-9878-dc906b9d4bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875919273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3875919273
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.967862730
Short name T352
Test name
Test status
Simulation time 4919445827 ps
CPU time 12.4 seconds
Started Oct 01 12:31:11 PM PDT 23
Finished Oct 01 12:31:23 PM PDT 23
Peak memory 211048 kb
Host smart-6a487cbb-1723-415b-a201-3260aeaaa6b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967862730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.967862730
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.15955777
Short name T241
Test name
Test status
Simulation time 6160188752 ps
CPU time 18.75 seconds
Started Oct 01 12:30:52 PM PDT 23
Finished Oct 01 12:31:11 PM PDT 23
Peak memory 213676 kb
Host smart-96035b04-ee8c-4580-960f-bb6d9c234654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15955777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.15955777
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1165036449
Short name T235
Test name
Test status
Simulation time 8133202271 ps
CPU time 48.82 seconds
Started Oct 01 12:30:58 PM PDT 23
Finished Oct 01 12:31:47 PM PDT 23
Peak memory 219256 kb
Host smart-075fd9ba-cc05-49ce-9d2d-9af7439b5981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165036449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1165036449
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4050708738
Short name T230
Test name
Test status
Simulation time 24751770832 ps
CPU time 1095.69 seconds
Started Oct 01 12:31:03 PM PDT 23
Finished Oct 01 12:49:20 PM PDT 23
Peak memory 235616 kb
Host smart-ea6cf130-76d6-481e-ae7b-ce52be56eb67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050708738 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.4050708738
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1521852816
Short name T356
Test name
Test status
Simulation time 1657467166 ps
CPU time 4.42 seconds
Started Oct 01 12:30:57 PM PDT 23
Finished Oct 01 12:31:01 PM PDT 23
Peak memory 211060 kb
Host smart-83d8ed46-33cc-4643-87bb-2afb900c7a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521852816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1521852816
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1845351403
Short name T421
Test name
Test status
Simulation time 154339218860 ps
CPU time 156.84 seconds
Started Oct 01 12:31:01 PM PDT 23
Finished Oct 01 12:33:38 PM PDT 23
Peak memory 237520 kb
Host smart-0799d6bf-3c72-4f7c-88ea-12e308ca2eb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845351403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1845351403
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1834039314
Short name T360
Test name
Test status
Simulation time 1785616084 ps
CPU time 18.19 seconds
Started Oct 01 12:30:58 PM PDT 23
Finished Oct 01 12:31:17 PM PDT 23
Peak memory 211948 kb
Host smart-e86743aa-b5d1-4191-8f79-b7412af40da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834039314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1834039314
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2687277510
Short name T9
Test name
Test status
Simulation time 3948660815 ps
CPU time 11.32 seconds
Started Oct 01 12:30:58 PM PDT 23
Finished Oct 01 12:31:09 PM PDT 23
Peak memory 211156 kb
Host smart-5567fe64-182e-46b3-83d4-6d0b0b9f6a83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2687277510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2687277510
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.793788672
Short name T243
Test name
Test status
Simulation time 870695677 ps
CPU time 17.88 seconds
Started Oct 01 12:30:58 PM PDT 23
Finished Oct 01 12:31:16 PM PDT 23
Peak memory 212944 kb
Host smart-fdcb4237-7241-4e04-b356-7e43c9b04576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793788672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.793788672
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3430490085
Short name T396
Test name
Test status
Simulation time 20894396733 ps
CPU time 65.3 seconds
Started Oct 01 12:30:49 PM PDT 23
Finished Oct 01 12:31:55 PM PDT 23
Peak memory 215976 kb
Host smart-efa6e3a3-2b3d-42f9-ad17-7597e23ff9ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430490085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3430490085
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1666383322
Short name T343
Test name
Test status
Simulation time 8566334792 ps
CPU time 10.15 seconds
Started Oct 01 12:30:43 PM PDT 23
Finished Oct 01 12:30:53 PM PDT 23
Peak memory 211056 kb
Host smart-da39f1d7-0088-4998-a204-5268ba6c0b99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666383322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1666383322
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.593932999
Short name T299
Test name
Test status
Simulation time 151926364789 ps
CPU time 467.11 seconds
Started Oct 01 12:30:43 PM PDT 23
Finished Oct 01 12:38:30 PM PDT 23
Peak memory 233564 kb
Host smart-2d668264-44ed-4f6b-a4b4-e5620bb4665c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593932999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.593932999
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2081723388
Short name T417
Test name
Test status
Simulation time 463054871 ps
CPU time 5.55 seconds
Started Oct 01 12:31:08 PM PDT 23
Finished Oct 01 12:31:14 PM PDT 23
Peak memory 211124 kb
Host smart-892551da-507a-4be6-b125-b9d948d3977e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081723388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2081723388
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2927237646
Short name T152
Test name
Test status
Simulation time 5167897232 ps
CPU time 25.6 seconds
Started Oct 01 12:30:48 PM PDT 23
Finished Oct 01 12:31:18 PM PDT 23
Peak memory 212784 kb
Host smart-0f689c03-2c5b-40a9-803b-fa7f7434c7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927237646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2927237646
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.448978653
Short name T433
Test name
Test status
Simulation time 9462580394 ps
CPU time 78.91 seconds
Started Oct 01 12:31:15 PM PDT 23
Finished Oct 01 12:32:34 PM PDT 23
Peak memory 215748 kb
Host smart-6603db71-8b95-4ce2-931e-52c6dd5e2913
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448978653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.448978653
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3799605336
Short name T281
Test name
Test status
Simulation time 436518593370 ps
CPU time 5238.46 seconds
Started Oct 01 12:30:53 PM PDT 23
Finished Oct 01 01:58:12 PM PDT 23
Peak memory 262388 kb
Host smart-e76b2509-7ebf-41fe-8588-ba109dee8e4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799605336 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3799605336
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.966408879
Short name T264
Test name
Test status
Simulation time 523074510 ps
CPU time 5.06 seconds
Started Oct 01 12:31:02 PM PDT 23
Finished Oct 01 12:31:07 PM PDT 23
Peak memory 211036 kb
Host smart-fb5e3ef2-e03d-4ce3-8def-703f0c5273ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966408879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.966408879
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3112749714
Short name T179
Test name
Test status
Simulation time 32343101599 ps
CPU time 318.21 seconds
Started Oct 01 12:31:00 PM PDT 23
Finished Oct 01 12:36:19 PM PDT 23
Peak memory 228116 kb
Host smart-2117c005-f81b-4a72-b585-0ed6b3643912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112749714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3112749714
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2625628444
Short name T262
Test name
Test status
Simulation time 2682733001 ps
CPU time 18.24 seconds
Started Oct 01 12:31:01 PM PDT 23
Finished Oct 01 12:31:19 PM PDT 23
Peak memory 211208 kb
Host smart-f3bbbc34-5f85-47e9-b678-4889592c76cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625628444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2625628444
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.104876115
Short name T173
Test name
Test status
Simulation time 1661843761 ps
CPU time 14.39 seconds
Started Oct 01 12:30:54 PM PDT 23
Finished Oct 01 12:31:09 PM PDT 23
Peak memory 210936 kb
Host smart-91f838e8-f134-4bf3-af26-645e8fcc60b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104876115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.104876115
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3975676124
Short name T150
Test name
Test status
Simulation time 186581019 ps
CPU time 9.92 seconds
Started Oct 01 12:30:58 PM PDT 23
Finished Oct 01 12:31:12 PM PDT 23
Peak memory 212376 kb
Host smart-c13dc6db-68a4-4ccc-af67-19fcb8812a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975676124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3975676124
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3224575177
Short name T321
Test name
Test status
Simulation time 1686415900 ps
CPU time 14.7 seconds
Started Oct 01 12:31:01 PM PDT 23
Finished Oct 01 12:31:16 PM PDT 23
Peak memory 210816 kb
Host smart-f1ea8446-e575-47f2-a918-93ba7123b44f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224575177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3224575177
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.415929360
Short name T156
Test name
Test status
Simulation time 93416908552 ps
CPU time 844.46 seconds
Started Oct 01 12:31:02 PM PDT 23
Finished Oct 01 12:45:07 PM PDT 23
Peak memory 231584 kb
Host smart-9e901e3b-5287-4cbb-b9bb-fb3074475659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415929360 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.415929360
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3828224708
Short name T255
Test name
Test status
Simulation time 6329497050 ps
CPU time 10.95 seconds
Started Oct 01 12:30:47 PM PDT 23
Finished Oct 01 12:30:58 PM PDT 23
Peak memory 211092 kb
Host smart-21d5cec9-7485-4065-97ef-ff4d16c5a339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828224708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3828224708
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1610096541
Short name T189
Test name
Test status
Simulation time 22617470330 ps
CPU time 237.7 seconds
Started Oct 01 12:30:57 PM PDT 23
Finished Oct 01 12:34:55 PM PDT 23
Peak memory 232720 kb
Host smart-3ac0e2f0-ffcc-42d6-9870-10413a7f46de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610096541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1610096541
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4193127640
Short name T317
Test name
Test status
Simulation time 2226224179 ps
CPU time 22.7 seconds
Started Oct 01 12:30:59 PM PDT 23
Finished Oct 01 12:31:24 PM PDT 23
Peak memory 211208 kb
Host smart-11f3b884-57e5-4d32-8496-39dc04e35551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193127640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4193127640
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4033229072
Short name T416
Test name
Test status
Simulation time 761785559 ps
CPU time 10.24 seconds
Started Oct 01 12:30:47 PM PDT 23
Finished Oct 01 12:30:57 PM PDT 23
Peak memory 211044 kb
Host smart-f0966fe0-3e2c-4d1e-b77e-38857a9d4657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4033229072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4033229072
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4280468252
Short name T274
Test name
Test status
Simulation time 865586128 ps
CPU time 13.54 seconds
Started Oct 01 12:31:11 PM PDT 23
Finished Oct 01 12:31:25 PM PDT 23
Peak memory 212760 kb
Host smart-b1cb31ed-3b06-4f40-aaac-dbadac4ccbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280468252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4280468252
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1678558001
Short name T373
Test name
Test status
Simulation time 70273104526 ps
CPU time 84.45 seconds
Started Oct 01 12:31:33 PM PDT 23
Finished Oct 01 12:32:58 PM PDT 23
Peak memory 216312 kb
Host smart-ea56cdc2-a22b-412c-8e76-6b0355e675e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678558001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1678558001
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3533910495
Short name T370
Test name
Test status
Simulation time 8185585705 ps
CPU time 15.14 seconds
Started Oct 01 12:30:55 PM PDT 23
Finished Oct 01 12:31:11 PM PDT 23
Peak memory 211156 kb
Host smart-cce53893-5a38-48a9-813d-c2d72e15cb0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533910495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3533910495
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1599067488
Short name T246
Test name
Test status
Simulation time 33992693487 ps
CPU time 424.3 seconds
Started Oct 01 12:30:54 PM PDT 23
Finished Oct 01 12:37:58 PM PDT 23
Peak memory 236252 kb
Host smart-e0fdaf86-ffae-45b9-adea-36d02db97697
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599067488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1599067488
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2871774585
Short name T161
Test name
Test status
Simulation time 14991609906 ps
CPU time 30.9 seconds
Started Oct 01 12:30:52 PM PDT 23
Finished Oct 01 12:31:23 PM PDT 23
Peak memory 211928 kb
Host smart-4e25bfb0-e448-4848-8b08-c4542ab687ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871774585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2871774585
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2896486507
Short name T268
Test name
Test status
Simulation time 1022818693 ps
CPU time 7.21 seconds
Started Oct 01 12:31:07 PM PDT 23
Finished Oct 01 12:31:15 PM PDT 23
Peak memory 210972 kb
Host smart-b8e1e2ec-fed1-4cd4-838f-c658edd4b80e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2896486507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2896486507
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.107493952
Short name T304
Test name
Test status
Simulation time 8563470820 ps
CPU time 34.02 seconds
Started Oct 01 12:31:18 PM PDT 23
Finished Oct 01 12:31:53 PM PDT 23
Peak memory 213292 kb
Host smart-792beca7-84a4-4661-aa1d-05f023dca3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107493952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.107493952
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1821633406
Short name T252
Test name
Test status
Simulation time 31407575908 ps
CPU time 74.21 seconds
Started Oct 01 12:30:45 PM PDT 23
Finished Oct 01 12:31:59 PM PDT 23
Peak memory 216308 kb
Host smart-72d6d47f-8d7b-4562-a3c2-ccf681a2ec23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821633406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1821633406
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2012798654
Short name T244
Test name
Test status
Simulation time 223455914174 ps
CPU time 1638.8 seconds
Started Oct 01 12:31:32 PM PDT 23
Finished Oct 01 12:58:51 PM PDT 23
Peak memory 236524 kb
Host smart-85211d05-d6fb-4fa9-9e94-4d3c135ad2be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012798654 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2012798654
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.668571772
Short name T259
Test name
Test status
Simulation time 7866064724 ps
CPU time 14.97 seconds
Started Oct 01 12:30:52 PM PDT 23
Finished Oct 01 12:31:07 PM PDT 23
Peak memory 211084 kb
Host smart-bc3bac89-fc46-46c8-b7c2-ede16d918bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668571772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.668571772
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4045722082
Short name T382
Test name
Test status
Simulation time 3882545026 ps
CPU time 32.31 seconds
Started Oct 01 12:31:03 PM PDT 23
Finished Oct 01 12:31:36 PM PDT 23
Peak memory 211236 kb
Host smart-cbb7ce9d-571f-4606-990b-3d721181a2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045722082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4045722082
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1497591303
Short name T226
Test name
Test status
Simulation time 16205438067 ps
CPU time 15.8 seconds
Started Oct 01 12:30:53 PM PDT 23
Finished Oct 01 12:31:14 PM PDT 23
Peak memory 210980 kb
Host smart-075238e3-1d90-4c8c-9304-307d50456b48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497591303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1497591303
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2358443791
Short name T92
Test name
Test status
Simulation time 3479223158 ps
CPU time 15.26 seconds
Started Oct 01 12:31:08 PM PDT 23
Finished Oct 01 12:31:24 PM PDT 23
Peak memory 212980 kb
Host smart-f67c5f1d-37c8-490b-8d7d-12a35c3e1199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358443791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2358443791
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.861762844
Short name T25
Test name
Test status
Simulation time 1625596635 ps
CPU time 9.6 seconds
Started Oct 01 12:30:55 PM PDT 23
Finished Oct 01 12:31:05 PM PDT 23
Peak memory 211448 kb
Host smart-a519717f-d896-4cc3-a8ae-d773760bc388
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861762844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.861762844
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.4249173501
Short name T414
Test name
Test status
Simulation time 40076239066 ps
CPU time 3999.14 seconds
Started Oct 01 12:30:55 PM PDT 23
Finished Oct 01 01:37:35 PM PDT 23
Peak memory 230884 kb
Host smart-20fde927-1e16-4c49-bb8d-20d25556b756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249173501 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.4249173501
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2181393535
Short name T159
Test name
Test status
Simulation time 1965100092 ps
CPU time 15.11 seconds
Started Oct 01 12:30:44 PM PDT 23
Finished Oct 01 12:30:59 PM PDT 23
Peak memory 210964 kb
Host smart-18858430-ee43-4dca-84bd-d49832786511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181393535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2181393535
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3309183790
Short name T195
Test name
Test status
Simulation time 136474376932 ps
CPU time 247.64 seconds
Started Oct 01 12:30:45 PM PDT 23
Finished Oct 01 12:34:53 PM PDT 23
Peak memory 232648 kb
Host smart-e5ef63ce-c4d0-4129-9c63-1198a24134ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309183790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3309183790
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3891803787
Short name T185
Test name
Test status
Simulation time 1643856406 ps
CPU time 19.79 seconds
Started Oct 01 12:31:11 PM PDT 23
Finished Oct 01 12:31:31 PM PDT 23
Peak memory 210964 kb
Host smart-38dc5c59-1714-46d9-8a06-28d1532916af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891803787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3891803787
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.494013958
Short name T348
Test name
Test status
Simulation time 196305444 ps
CPU time 5.67 seconds
Started Oct 01 12:31:29 PM PDT 23
Finished Oct 01 12:31:36 PM PDT 23
Peak memory 211032 kb
Host smart-5384be4c-14a2-4627-9faa-10c1a6e1c137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494013958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.494013958
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1663978031
Short name T355
Test name
Test status
Simulation time 6346090161 ps
CPU time 23.5 seconds
Started Oct 01 12:30:47 PM PDT 23
Finished Oct 01 12:31:11 PM PDT 23
Peak memory 213712 kb
Host smart-2b9ab5fe-52ca-44d9-acaa-46c95c31d65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663978031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1663978031
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1893575162
Short name T330
Test name
Test status
Simulation time 70456966087 ps
CPU time 70.79 seconds
Started Oct 01 12:30:57 PM PDT 23
Finished Oct 01 12:32:08 PM PDT 23
Peak memory 219316 kb
Host smart-2df6d7a4-1e90-45ca-bfd0-bebaf2ecc256
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893575162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1893575162
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3467002725
Short name T361
Test name
Test status
Simulation time 70992909521 ps
CPU time 2559.72 seconds
Started Oct 01 12:30:47 PM PDT 23
Finished Oct 01 01:13:27 PM PDT 23
Peak memory 244452 kb
Host smart-ded357e4-7230-4d2d-8175-953bc27dd99f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467002725 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3467002725
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3334784729
Short name T362
Test name
Test status
Simulation time 346942940 ps
CPU time 4.24 seconds
Started Oct 01 12:31:23 PM PDT 23
Finished Oct 01 12:31:27 PM PDT 23
Peak memory 210968 kb
Host smart-b7e76caf-ad07-41e8-8be9-520a00a78e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334784729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3334784729
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.390535114
Short name T183
Test name
Test status
Simulation time 142365496393 ps
CPU time 369.45 seconds
Started Oct 01 12:31:15 PM PDT 23
Finished Oct 01 12:37:24 PM PDT 23
Peak memory 236368 kb
Host smart-9dbce398-bf1e-4aa1-91bf-e92d29c14ab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390535114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.390535114
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1309956999
Short name T162
Test name
Test status
Simulation time 1413531923 ps
CPU time 18.42 seconds
Started Oct 01 12:31:04 PM PDT 23
Finished Oct 01 12:31:22 PM PDT 23
Peak memory 211060 kb
Host smart-fce6a906-4297-457b-beeb-2144fe092ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309956999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1309956999
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2462801071
Short name T306
Test name
Test status
Simulation time 3195515970 ps
CPU time 14.78 seconds
Started Oct 01 12:31:11 PM PDT 23
Finished Oct 01 12:31:26 PM PDT 23
Peak memory 211020 kb
Host smart-8de68aaa-d66c-4b65-a7ba-5035f2a4cf3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2462801071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2462801071
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3028047703
Short name T188
Test name
Test status
Simulation time 758847598 ps
CPU time 9.84 seconds
Started Oct 01 12:30:50 PM PDT 23
Finished Oct 01 12:31:00 PM PDT 23
Peak memory 212876 kb
Host smart-340187bd-be85-4d46-a563-877370757346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028047703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3028047703
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1718430948
Short name T402
Test name
Test status
Simulation time 2662092545 ps
CPU time 14.36 seconds
Started Oct 01 12:30:53 PM PDT 23
Finished Oct 01 12:31:08 PM PDT 23
Peak memory 213884 kb
Host smart-62f720e2-b1fe-42d7-a5dd-224612257231
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718430948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1718430948
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2938300209
Short name T366
Test name
Test status
Simulation time 2091551009 ps
CPU time 15.92 seconds
Started Oct 01 12:30:47 PM PDT 23
Finished Oct 01 12:31:04 PM PDT 23
Peak memory 211048 kb
Host smart-6f1dbe50-6392-4ac3-824f-a6c723bf9bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938300209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2938300209
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2833064829
Short name T50
Test name
Test status
Simulation time 118245608141 ps
CPU time 276.8 seconds
Started Oct 01 12:30:50 PM PDT 23
Finished Oct 01 12:35:27 PM PDT 23
Peak memory 212288 kb
Host smart-1e1f22cb-d89b-4e62-8659-1f2ee6a6523c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833064829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2833064829
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.734995706
Short name T286
Test name
Test status
Simulation time 13040419706 ps
CPU time 16.83 seconds
Started Oct 01 12:31:11 PM PDT 23
Finished Oct 01 12:31:28 PM PDT 23
Peak memory 211092 kb
Host smart-4ad204cf-abeb-4e28-be9d-113f5ebef3e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734995706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.734995706
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3178488130
Short name T379
Test name
Test status
Simulation time 13833775464 ps
CPU time 35.2 seconds
Started Oct 01 12:31:19 PM PDT 23
Finished Oct 01 12:31:55 PM PDT 23
Peak memory 213532 kb
Host smart-44e26ae1-0759-4374-a4d4-0abf24d4df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178488130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3178488130
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3709846747
Short name T201
Test name
Test status
Simulation time 289992635 ps
CPU time 12.04 seconds
Started Oct 01 12:30:59 PM PDT 23
Finished Oct 01 12:31:14 PM PDT 23
Peak memory 213468 kb
Host smart-6f188dd1-ccfd-4f61-9241-8e664a8108ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709846747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3709846747
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1238696600
Short name T331
Test name
Test status
Simulation time 139712027100 ps
CPU time 1284.02 seconds
Started Oct 01 12:30:43 PM PDT 23
Finished Oct 01 12:52:07 PM PDT 23
Peak memory 235804 kb
Host smart-5f19d764-48c6-48d0-9587-dbd45bea47dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238696600 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1238696600
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1365886203
Short name T187
Test name
Test status
Simulation time 4086853943 ps
CPU time 15.31 seconds
Started Oct 01 12:20:16 PM PDT 23
Finished Oct 01 12:20:32 PM PDT 23
Peak memory 211056 kb
Host smart-90c3a9ea-1be6-4d77-b8fa-fc6a2d41d015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365886203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1365886203
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.698252477
Short name T177
Test name
Test status
Simulation time 107245156242 ps
CPU time 458.18 seconds
Started Oct 01 12:20:39 PM PDT 23
Finished Oct 01 12:28:18 PM PDT 23
Peak memory 228348 kb
Host smart-efb79f15-86b2-454d-b7b6-31ae256c066d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698252477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.698252477
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1323728103
Short name T380
Test name
Test status
Simulation time 175373368 ps
CPU time 9.2 seconds
Started Oct 01 12:22:48 PM PDT 23
Finished Oct 01 12:22:59 PM PDT 23
Peak memory 211116 kb
Host smart-4f2b2aa8-0906-45e2-999d-528446d6ac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323728103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1323728103
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1516805119
Short name T166
Test name
Test status
Simulation time 97058969 ps
CPU time 5.58 seconds
Started Oct 01 12:19:23 PM PDT 23
Finished Oct 01 12:19:29 PM PDT 23
Peak memory 210124 kb
Host smart-67cc3306-3bab-4156-8b37-d175a37d7f3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516805119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1516805119
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2946489367
Short name T46
Test name
Test status
Simulation time 9087682349 ps
CPU time 68.84 seconds
Started Oct 01 12:21:03 PM PDT 23
Finished Oct 01 12:22:12 PM PDT 23
Peak memory 236628 kb
Host smart-f196f431-3db8-4816-8f5b-ae58bdabdded
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946489367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2946489367
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.292525772
Short name T411
Test name
Test status
Simulation time 5001145056 ps
CPU time 32.5 seconds
Started Oct 01 12:19:31 PM PDT 23
Finished Oct 01 12:20:05 PM PDT 23
Peak memory 215888 kb
Host smart-f0d0de26-29e0-443f-ad58-8de43225fbbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292525772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.292525772
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2942059785
Short name T190
Test name
Test status
Simulation time 24194164113 ps
CPU time 1111.2 seconds
Started Oct 01 12:21:26 PM PDT 23
Finished Oct 01 12:39:57 PM PDT 23
Peak memory 232300 kb
Host smart-92a0dc83-f9de-4c9a-b85d-ba392acb0b3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942059785 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2942059785
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2450022061
Short name T374
Test name
Test status
Simulation time 294269909 ps
CPU time 6.25 seconds
Started Oct 01 12:30:53 PM PDT 23
Finished Oct 01 12:30:59 PM PDT 23
Peak memory 211040 kb
Host smart-c03a24da-94d7-4231-b61b-f2e5094cc53c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450022061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2450022061
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3044212379
Short name T275
Test name
Test status
Simulation time 81757116356 ps
CPU time 200.75 seconds
Started Oct 01 12:31:30 PM PDT 23
Finished Oct 01 12:34:51 PM PDT 23
Peak memory 236732 kb
Host smart-2d5314d0-a1bb-4835-bfac-bf724e3c2fda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044212379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3044212379
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3199954697
Short name T13
Test name
Test status
Simulation time 692462777 ps
CPU time 9.53 seconds
Started Oct 01 12:31:05 PM PDT 23
Finished Oct 01 12:31:15 PM PDT 23
Peak memory 211188 kb
Host smart-fdb59f97-9f88-4d49-9e0b-4a7ebf885c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199954697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3199954697
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3055415990
Short name T103
Test name
Test status
Simulation time 3086159151 ps
CPU time 10.13 seconds
Started Oct 01 12:30:55 PM PDT 23
Finished Oct 01 12:31:05 PM PDT 23
Peak memory 211096 kb
Host smart-dd97c9ff-00be-47e7-8383-49fe3cc3d5a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055415990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3055415990
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3027830404
Short name T198
Test name
Test status
Simulation time 949019203 ps
CPU time 17.3 seconds
Started Oct 01 12:31:03 PM PDT 23
Finished Oct 01 12:31:21 PM PDT 23
Peak memory 211960 kb
Host smart-70a87c9b-4e37-43a4-99c8-1d53485c742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027830404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3027830404
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.676441696
Short name T78
Test name
Test status
Simulation time 51491497202 ps
CPU time 115.85 seconds
Started Oct 01 12:31:23 PM PDT 23
Finished Oct 01 12:33:19 PM PDT 23
Peak memory 217556 kb
Host smart-2f5b718c-d88d-4180-91fb-59c8507ddf96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676441696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.676441696
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.11848076
Short name T334
Test name
Test status
Simulation time 5760905916 ps
CPU time 12.51 seconds
Started Oct 01 12:30:42 PM PDT 23
Finished Oct 01 12:30:55 PM PDT 23
Peak memory 211120 kb
Host smart-79cc7205-060b-4ee7-b9a3-99fd0a2611a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11848076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.11848076
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.852134345
Short name T272
Test name
Test status
Simulation time 36079646260 ps
CPU time 340.54 seconds
Started Oct 01 12:31:06 PM PDT 23
Finished Oct 01 12:36:47 PM PDT 23
Peak memory 211500 kb
Host smart-71dede2a-c344-4144-883d-4c25e8634e0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852134345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.852134345
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4234922115
Short name T260
Test name
Test status
Simulation time 3899768725 ps
CPU time 32.31 seconds
Started Oct 01 12:30:45 PM PDT 23
Finished Oct 01 12:31:18 PM PDT 23
Peak memory 211300 kb
Host smart-3aab71aa-84f8-43ad-aa5a-671d0a62f2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234922115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4234922115
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1459335040
Short name T376
Test name
Test status
Simulation time 371239043 ps
CPU time 5.55 seconds
Started Oct 01 12:30:58 PM PDT 23
Finished Oct 01 12:31:03 PM PDT 23
Peak memory 211000 kb
Host smart-0c095ff6-f7bd-4acf-a416-f32e7d89d418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459335040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1459335040
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2663406953
Short name T369
Test name
Test status
Simulation time 946807097 ps
CPU time 17.2 seconds
Started Oct 01 12:30:57 PM PDT 23
Finished Oct 01 12:31:14 PM PDT 23
Peak memory 212636 kb
Host smart-7d76720c-efea-409d-85e7-f753a4828112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663406953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2663406953
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.633328642
Short name T94
Test name
Test status
Simulation time 533476880 ps
CPU time 8.67 seconds
Started Oct 01 12:30:53 PM PDT 23
Finished Oct 01 12:31:02 PM PDT 23
Peak memory 211028 kb
Host smart-49b93952-0d8b-4b29-a59f-467c7a5d6584
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633328642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.633328642
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1571743528
Short name T247
Test name
Test status
Simulation time 33402306636 ps
CPU time 1225.14 seconds
Started Oct 01 12:30:59 PM PDT 23
Finished Oct 01 12:51:24 PM PDT 23
Peak memory 229556 kb
Host smart-3801baae-d193-4627-ab47-a93c16235479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571743528 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1571743528
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.602116674
Short name T393
Test name
Test status
Simulation time 403458508 ps
CPU time 5.16 seconds
Started Oct 01 12:31:10 PM PDT 23
Finished Oct 01 12:31:16 PM PDT 23
Peak memory 210872 kb
Host smart-8548ffbf-7c17-4514-82e5-2ab74c8bec20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602116674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.602116674
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2599380244
Short name T96
Test name
Test status
Simulation time 47937472288 ps
CPU time 261.44 seconds
Started Oct 01 12:31:23 PM PDT 23
Finished Oct 01 12:35:45 PM PDT 23
Peak memory 237700 kb
Host smart-ac62544f-89ad-4c63-acf9-1950ce8bd0d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599380244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2599380244
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3494181028
Short name T193
Test name
Test status
Simulation time 10523430595 ps
CPU time 24.91 seconds
Started Oct 01 12:30:59 PM PDT 23
Finished Oct 01 12:31:24 PM PDT 23
Peak memory 211432 kb
Host smart-e99ff324-f33f-428f-bcae-e10e39989e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494181028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3494181028
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1426203531
Short name T392
Test name
Test status
Simulation time 1586598730 ps
CPU time 13.73 seconds
Started Oct 01 12:31:08 PM PDT 23
Finished Oct 01 12:31:22 PM PDT 23
Peak memory 211028 kb
Host smart-90b9a4bf-99c4-42e2-97a4-bf92e182656c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426203531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1426203531
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.350016635
Short name T212
Test name
Test status
Simulation time 4733479895 ps
CPU time 28.55 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:53 PM PDT 23
Peak memory 213260 kb
Host smart-b17b1b93-816c-4551-b3f6-4a6b5cc12682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350016635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.350016635
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2196674468
Short name T171
Test name
Test status
Simulation time 3558988909 ps
CPU time 18.48 seconds
Started Oct 01 12:30:59 PM PDT 23
Finished Oct 01 12:31:18 PM PDT 23
Peak memory 212824 kb
Host smart-26fb893a-e09b-41d6-8ff4-4969c621ff6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196674468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2196674468
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.64977044
Short name T318
Test name
Test status
Simulation time 558919762 ps
CPU time 6.53 seconds
Started Oct 01 12:30:58 PM PDT 23
Finished Oct 01 12:31:05 PM PDT 23
Peak memory 211036 kb
Host smart-12a21ee0-5365-4d61-bae8-ac01110f91ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64977044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.64977044
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1282815658
Short name T310
Test name
Test status
Simulation time 167551354509 ps
CPU time 434.56 seconds
Started Oct 01 12:31:02 PM PDT 23
Finished Oct 01 12:38:17 PM PDT 23
Peak memory 227860 kb
Host smart-8d14d832-8d89-44c3-8aa2-56309575448e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282815658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1282815658
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2101132676
Short name T313
Test name
Test status
Simulation time 11278633125 ps
CPU time 32.65 seconds
Started Oct 01 12:30:57 PM PDT 23
Finished Oct 01 12:31:30 PM PDT 23
Peak memory 211496 kb
Host smart-b6651831-f380-4106-9844-b705b6de307d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101132676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2101132676
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1208906252
Short name T338
Test name
Test status
Simulation time 352735428 ps
CPU time 5.28 seconds
Started Oct 01 12:30:46 PM PDT 23
Finished Oct 01 12:30:52 PM PDT 23
Peak memory 211048 kb
Host smart-d973297d-4da7-4567-90b9-d3d35417a0ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208906252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1208906252
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2067285232
Short name T423
Test name
Test status
Simulation time 3703703791 ps
CPU time 20.78 seconds
Started Oct 01 12:31:18 PM PDT 23
Finished Oct 01 12:31:39 PM PDT 23
Peak memory 212780 kb
Host smart-27f1722b-26e8-4f52-88ce-597bed83d195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067285232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2067285232
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.296971156
Short name T168
Test name
Test status
Simulation time 12332251572 ps
CPU time 55.08 seconds
Started Oct 01 12:31:22 PM PDT 23
Finished Oct 01 12:32:17 PM PDT 23
Peak memory 216092 kb
Host smart-822cf7a5-bba8-48a9-950e-7c4379124634
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296971156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.296971156
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.670367436
Short name T170
Test name
Test status
Simulation time 1226273049 ps
CPU time 7.08 seconds
Started Oct 01 12:30:54 PM PDT 23
Finished Oct 01 12:31:02 PM PDT 23
Peak memory 211012 kb
Host smart-a582f067-d94a-46c9-8f13-4557617f628e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670367436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.670367436
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.440327352
Short name T14
Test name
Test status
Simulation time 67506258516 ps
CPU time 212.71 seconds
Started Oct 01 12:31:07 PM PDT 23
Finished Oct 01 12:34:39 PM PDT 23
Peak memory 236860 kb
Host smart-47b75b51-2276-46e2-9a8b-29db79bfa641
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440327352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.440327352
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2604702569
Short name T12
Test name
Test status
Simulation time 347780675 ps
CPU time 9.35 seconds
Started Oct 01 12:31:04 PM PDT 23
Finished Oct 01 12:31:13 PM PDT 23
Peak memory 211044 kb
Host smart-f722398e-2561-4efe-ab93-66fad9220b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604702569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2604702569
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3946793191
Short name T155
Test name
Test status
Simulation time 1638255368 ps
CPU time 14.89 seconds
Started Oct 01 12:31:19 PM PDT 23
Finished Oct 01 12:31:34 PM PDT 23
Peak memory 211056 kb
Host smart-f266ac49-4659-4001-9583-44d33dd9493d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946793191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3946793191
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1501592186
Short name T290
Test name
Test status
Simulation time 3213021973 ps
CPU time 30.38 seconds
Started Oct 01 12:31:03 PM PDT 23
Finished Oct 01 12:31:34 PM PDT 23
Peak memory 212444 kb
Host smart-c52a925d-494f-480f-a90f-8deab837a493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501592186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1501592186
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1960871018
Short name T405
Test name
Test status
Simulation time 10283561480 ps
CPU time 48.24 seconds
Started Oct 01 12:30:49 PM PDT 23
Finished Oct 01 12:31:38 PM PDT 23
Peak memory 213436 kb
Host smart-fb75d205-f074-4b06-91fd-ef0816c02b70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960871018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1960871018
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.655709190
Short name T223
Test name
Test status
Simulation time 58248279687 ps
CPU time 459.73 seconds
Started Oct 01 12:30:57 PM PDT 23
Finished Oct 01 12:38:37 PM PDT 23
Peak memory 227528 kb
Host smart-b5376730-7280-49f4-bbf5-e660e0f2856f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655709190 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.655709190
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3673052902
Short name T265
Test name
Test status
Simulation time 3181818141 ps
CPU time 12.88 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:37 PM PDT 23
Peak memory 211136 kb
Host smart-7e282c5a-de63-4be7-9984-224c95a19648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673052902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3673052902
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3046056752
Short name T256
Test name
Test status
Simulation time 32963969993 ps
CPU time 135.94 seconds
Started Oct 01 12:31:05 PM PDT 23
Finished Oct 01 12:33:26 PM PDT 23
Peak memory 228112 kb
Host smart-0464fb29-2cc5-4437-9621-3592d581e14d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046056752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3046056752
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2958236262
Short name T390
Test name
Test status
Simulation time 15004082014 ps
CPU time 29.95 seconds
Started Oct 01 12:30:47 PM PDT 23
Finished Oct 01 12:31:18 PM PDT 23
Peak memory 211404 kb
Host smart-90e7223e-e20a-4098-bc86-e8aedcbc303b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958236262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2958236262
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1495239181
Short name T180
Test name
Test status
Simulation time 4278965113 ps
CPU time 11.48 seconds
Started Oct 01 12:31:42 PM PDT 23
Finished Oct 01 12:31:54 PM PDT 23
Peak memory 211060 kb
Host smart-43123fe2-c9a2-44fa-a9c3-43881b023e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1495239181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1495239181
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3358067603
Short name T385
Test name
Test status
Simulation time 6890801459 ps
CPU time 33.57 seconds
Started Oct 01 12:31:15 PM PDT 23
Finished Oct 01 12:31:49 PM PDT 23
Peak memory 213788 kb
Host smart-600fdad1-05e0-4823-a42f-8ee589165b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358067603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3358067603
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1955809188
Short name T357
Test name
Test status
Simulation time 121284703 ps
CPU time 7.82 seconds
Started Oct 01 12:31:25 PM PDT 23
Finished Oct 01 12:31:33 PM PDT 23
Peak memory 211300 kb
Host smart-82166aa8-b39f-4c3c-bf1f-ae72406b168c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955809188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1955809188
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1834932686
Short name T6
Test name
Test status
Simulation time 183656100620 ps
CPU time 1876.19 seconds
Started Oct 01 12:30:50 PM PDT 23
Finished Oct 01 01:02:07 PM PDT 23
Peak memory 244048 kb
Host smart-1ffa7173-34b0-48ee-b183-b5823db2384f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834932686 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1834932686
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2849369096
Short name T353
Test name
Test status
Simulation time 923955695 ps
CPU time 4.37 seconds
Started Oct 01 12:31:30 PM PDT 23
Finished Oct 01 12:31:35 PM PDT 23
Peak memory 210884 kb
Host smart-c1dae3b5-8049-408c-a07b-2d9fce687189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849369096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2849369096
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3907728131
Short name T347
Test name
Test status
Simulation time 22598019766 ps
CPU time 223.82 seconds
Started Oct 01 12:30:46 PM PDT 23
Finished Oct 01 12:34:30 PM PDT 23
Peak memory 236688 kb
Host smart-69349f28-fee9-4930-871b-a3affbe60123
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907728131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3907728131
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4098013057
Short name T364
Test name
Test status
Simulation time 19327391234 ps
CPU time 28.76 seconds
Started Oct 01 12:31:27 PM PDT 23
Finished Oct 01 12:31:56 PM PDT 23
Peak memory 211496 kb
Host smart-34a0b799-e996-4eac-82c1-6eef33034afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098013057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4098013057
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3676498917
Short name T415
Test name
Test status
Simulation time 400814943 ps
CPU time 6.01 seconds
Started Oct 01 12:31:28 PM PDT 23
Finished Oct 01 12:31:34 PM PDT 23
Peak memory 210948 kb
Host smart-92125303-8506-46da-9ffa-137800cf8b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676498917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3676498917
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.729904342
Short name T211
Test name
Test status
Simulation time 6120108568 ps
CPU time 15.81 seconds
Started Oct 01 12:31:26 PM PDT 23
Finished Oct 01 12:31:42 PM PDT 23
Peak memory 214268 kb
Host smart-0985efe1-a243-4e5a-90e2-728945679100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729904342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.729904342
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1422793177
Short name T196
Test name
Test status
Simulation time 75748440531 ps
CPU time 55.28 seconds
Started Oct 01 12:31:22 PM PDT 23
Finished Oct 01 12:32:18 PM PDT 23
Peak memory 216468 kb
Host smart-f250c402-d347-4f09-b889-a96224aec755
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422793177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1422793177
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.492651779
Short name T158
Test name
Test status
Simulation time 93905210906 ps
CPU time 1534.19 seconds
Started Oct 01 12:30:44 PM PDT 23
Finished Oct 01 12:56:19 PM PDT 23
Peak memory 235692 kb
Host smart-26560a4f-639c-4da0-86e6-62148eb76061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492651779 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.492651779
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.427309759
Short name T41
Test name
Test status
Simulation time 4312909062 ps
CPU time 10.77 seconds
Started Oct 01 12:31:15 PM PDT 23
Finished Oct 01 12:31:26 PM PDT 23
Peak memory 211164 kb
Host smart-d59c810e-0be6-4b67-aefb-ab4b9461f415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427309759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.427309759
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.9259825
Short name T387
Test name
Test status
Simulation time 62225461056 ps
CPU time 296.47 seconds
Started Oct 01 12:31:26 PM PDT 23
Finished Oct 01 12:36:23 PM PDT 23
Peak memory 234748 kb
Host smart-2fd6f92b-df0b-42f0-88ff-60613f349a35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9259825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_cor
rupt_sig_fatal_chk.9259825
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.983295214
Short name T217
Test name
Test status
Simulation time 10184955234 ps
CPU time 24.34 seconds
Started Oct 01 12:31:08 PM PDT 23
Finished Oct 01 12:31:33 PM PDT 23
Peak memory 211628 kb
Host smart-0f6321c5-38f9-4b8e-be76-4cc577d75c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983295214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.983295214
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3431091690
Short name T420
Test name
Test status
Simulation time 99457698 ps
CPU time 5.55 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:30 PM PDT 23
Peak memory 210924 kb
Host smart-dc87de53-2d5d-4024-9a1c-2c0e3d30cf11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3431091690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3431091690
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3176766938
Short name T218
Test name
Test status
Simulation time 47024419207 ps
CPU time 30.2 seconds
Started Oct 01 12:31:10 PM PDT 23
Finished Oct 01 12:31:40 PM PDT 23
Peak memory 213488 kb
Host smart-2de92401-30e3-4861-8bf9-adab30a01b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176766938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3176766938
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2744560614
Short name T291
Test name
Test status
Simulation time 79166457925 ps
CPU time 103.52 seconds
Started Oct 01 12:31:11 PM PDT 23
Finished Oct 01 12:32:54 PM PDT 23
Peak memory 219272 kb
Host smart-8e3a8738-7caf-42d3-9f9a-4dd7530acf6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744560614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2744560614
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2436467449
Short name T424
Test name
Test status
Simulation time 12074289051 ps
CPU time 535.7 seconds
Started Oct 01 12:30:50 PM PDT 23
Finished Oct 01 12:39:46 PM PDT 23
Peak memory 221460 kb
Host smart-2585383c-2aeb-420b-974f-b29487a54328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436467449 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2436467449
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1232428187
Short name T39
Test name
Test status
Simulation time 1119423507 ps
CPU time 11.39 seconds
Started Oct 01 12:31:22 PM PDT 23
Finished Oct 01 12:31:33 PM PDT 23
Peak memory 211028 kb
Host smart-f04eaa36-262a-4e8c-b174-6726b0db7b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232428187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1232428187
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.485924351
Short name T323
Test name
Test status
Simulation time 19112564490 ps
CPU time 243.56 seconds
Started Oct 01 12:31:06 PM PDT 23
Finished Oct 01 12:35:10 PM PDT 23
Peak memory 224448 kb
Host smart-c7a5c7c4-634c-448f-abc3-8f9803d26407
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485924351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.485924351
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.409589712
Short name T249
Test name
Test status
Simulation time 168974614 ps
CPU time 9.57 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:34 PM PDT 23
Peak memory 211592 kb
Host smart-dd992da9-e65a-4477-ac55-ac0d4d07da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409589712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.409589712
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.792126419
Short name T101
Test name
Test status
Simulation time 2104670627 ps
CPU time 17.67 seconds
Started Oct 01 12:31:26 PM PDT 23
Finished Oct 01 12:31:44 PM PDT 23
Peak memory 210968 kb
Host smart-02065eb1-bff6-4073-a215-60f74f6335f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792126419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.792126419
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.761637714
Short name T169
Test name
Test status
Simulation time 1363527544 ps
CPU time 14.05 seconds
Started Oct 01 12:31:31 PM PDT 23
Finished Oct 01 12:31:46 PM PDT 23
Peak memory 211556 kb
Host smart-f6912c3c-cc34-494b-a019-be4fe53c3431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761637714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.761637714
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2665633961
Short name T149
Test name
Test status
Simulation time 90289964 ps
CPU time 6.97 seconds
Started Oct 01 12:31:15 PM PDT 23
Finished Oct 01 12:31:22 PM PDT 23
Peak memory 210848 kb
Host smart-b5f01ba3-e77b-417f-9e75-1288b02cf259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665633961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2665633961
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2235835226
Short name T316
Test name
Test status
Simulation time 1655092075 ps
CPU time 4.44 seconds
Started Oct 01 12:30:58 PM PDT 23
Finished Oct 01 12:31:02 PM PDT 23
Peak memory 211048 kb
Host smart-dfb988da-963a-4a4c-a8cf-e4af7e2f16d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235835226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2235835226
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.285901251
Short name T368
Test name
Test status
Simulation time 315517956094 ps
CPU time 300.59 seconds
Started Oct 01 12:30:53 PM PDT 23
Finished Oct 01 12:35:54 PM PDT 23
Peak memory 236884 kb
Host smart-fefa6292-0783-44cd-be85-72eb5af1fbdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285901251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.285901251
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2803237054
Short name T242
Test name
Test status
Simulation time 836418143 ps
CPU time 14.86 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:39 PM PDT 23
Peak memory 211220 kb
Host smart-2100982a-3ce0-4120-9f83-80069a5f2020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803237054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2803237054
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2175797118
Short name T165
Test name
Test status
Simulation time 1747690907 ps
CPU time 15.23 seconds
Started Oct 01 12:31:37 PM PDT 23
Finished Oct 01 12:31:52 PM PDT 23
Peak memory 210972 kb
Host smart-f3881fd5-9faa-4000-b042-ca2a999027d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2175797118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2175797118
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1170177196
Short name T26
Test name
Test status
Simulation time 3016555533 ps
CPU time 34.11 seconds
Started Oct 01 12:31:27 PM PDT 23
Finished Oct 01 12:32:01 PM PDT 23
Peak memory 212812 kb
Host smart-84db456b-4860-4a81-8e65-39160272ddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170177196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1170177196
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2082151982
Short name T386
Test name
Test status
Simulation time 3023764788 ps
CPU time 14.87 seconds
Started Oct 01 12:31:04 PM PDT 23
Finished Oct 01 12:31:19 PM PDT 23
Peak memory 211292 kb
Host smart-c7d7f489-5704-49aa-be81-766a296cf213
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082151982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2082151982
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3138659368
Short name T407
Test name
Test status
Simulation time 65323115090 ps
CPU time 5316.31 seconds
Started Oct 01 12:31:08 PM PDT 23
Finished Oct 01 01:59:45 PM PDT 23
Peak memory 235788 kb
Host smart-e0e8f4c4-aab5-4780-94d5-86b29b87575e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138659368 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3138659368
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2447328866
Short name T345
Test name
Test status
Simulation time 93580437 ps
CPU time 4.25 seconds
Started Oct 01 12:20:29 PM PDT 23
Finished Oct 01 12:20:34 PM PDT 23
Peak memory 210952 kb
Host smart-40562718-21db-462a-996c-09be7abf9ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447328866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2447328866
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3849691308
Short name T288
Test name
Test status
Simulation time 2846237475 ps
CPU time 63.4 seconds
Started Oct 01 12:17:29 PM PDT 23
Finished Oct 01 12:18:32 PM PDT 23
Peak memory 228296 kb
Host smart-437c52a4-d563-428f-bf70-0eced54b2edb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849691308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3849691308
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4231295390
Short name T337
Test name
Test status
Simulation time 1324784220 ps
CPU time 11.87 seconds
Started Oct 01 12:18:57 PM PDT 23
Finished Oct 01 12:19:09 PM PDT 23
Peak memory 211072 kb
Host smart-25194ab9-9170-4ed2-b80d-e4bde92e2112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231295390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4231295390
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3297686341
Short name T327
Test name
Test status
Simulation time 1593907384 ps
CPU time 14.1 seconds
Started Oct 01 12:18:25 PM PDT 23
Finished Oct 01 12:18:40 PM PDT 23
Peak memory 209436 kb
Host smart-e10d23c3-e173-4fbf-9978-12f75523aa4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297686341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3297686341
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.732824471
Short name T363
Test name
Test status
Simulation time 1020580908 ps
CPU time 10.24 seconds
Started Oct 01 12:17:13 PM PDT 23
Finished Oct 01 12:17:24 PM PDT 23
Peak memory 213040 kb
Host smart-bfc89c00-66c6-4f12-959c-1b40cb15d190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732824471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.732824471
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4105998723
Short name T425
Test name
Test status
Simulation time 20483931820 ps
CPU time 90.42 seconds
Started Oct 01 12:22:29 PM PDT 23
Finished Oct 01 12:24:00 PM PDT 23
Peak memory 218644 kb
Host smart-a5259c6f-a7f7-4e13-9c58-98c4eee219e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105998723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4105998723
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1466727160
Short name T422
Test name
Test status
Simulation time 201118503082 ps
CPU time 2905.21 seconds
Started Oct 01 12:21:07 PM PDT 23
Finished Oct 01 01:09:33 PM PDT 23
Peak memory 235708 kb
Host smart-1fbe3923-d9e8-47f9-973a-6b93b383be70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466727160 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1466727160
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.4073722089
Short name T229
Test name
Test status
Simulation time 335305477 ps
CPU time 5.97 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:30 PM PDT 23
Peak memory 210996 kb
Host smart-0e07005f-3053-41fb-b263-b2e798e5693e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073722089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4073722089
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1726571952
Short name T354
Test name
Test status
Simulation time 165881281030 ps
CPU time 330.25 seconds
Started Oct 01 12:31:15 PM PDT 23
Finished Oct 01 12:36:45 PM PDT 23
Peak memory 237500 kb
Host smart-b113d351-fb54-464b-866a-770a35ac4ac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726571952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1726571952
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1524769532
Short name T346
Test name
Test status
Simulation time 333587825 ps
CPU time 9.5 seconds
Started Oct 01 12:31:07 PM PDT 23
Finished Oct 01 12:31:17 PM PDT 23
Peak memory 211128 kb
Host smart-47ed3895-8607-43c3-bc45-3965194a1800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524769532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1524769532
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1048149496
Short name T172
Test name
Test status
Simulation time 3842783548 ps
CPU time 15.71 seconds
Started Oct 01 12:31:00 PM PDT 23
Finished Oct 01 12:31:16 PM PDT 23
Peak memory 211144 kb
Host smart-b65d68e3-ca3e-4cea-b0f1-2c87feae7bc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048149496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1048149496
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3264169283
Short name T186
Test name
Test status
Simulation time 513564399 ps
CPU time 14.19 seconds
Started Oct 01 12:31:17 PM PDT 23
Finished Oct 01 12:31:31 PM PDT 23
Peak memory 212508 kb
Host smart-4e213e11-b043-4bcd-aa7d-954812be12e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264169283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3264169283
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.176133694
Short name T228
Test name
Test status
Simulation time 572179824 ps
CPU time 7.38 seconds
Started Oct 01 12:31:08 PM PDT 23
Finished Oct 01 12:31:15 PM PDT 23
Peak memory 210792 kb
Host smart-9dd000b2-12e1-431c-aefc-4d0661dac9cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176133694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.176133694
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3970570790
Short name T22
Test name
Test status
Simulation time 135082041591 ps
CPU time 510.32 seconds
Started Oct 01 12:31:41 PM PDT 23
Finished Oct 01 12:40:12 PM PDT 23
Peak memory 235768 kb
Host smart-fb22c5bc-0959-4f02-8360-69c565e1c81a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970570790 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3970570790
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4202726518
Short name T339
Test name
Test status
Simulation time 346421449 ps
CPU time 4.28 seconds
Started Oct 01 12:31:09 PM PDT 23
Finished Oct 01 12:31:14 PM PDT 23
Peak memory 210936 kb
Host smart-12644d9d-89c7-4524-bd04-247a67f2543b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202726518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4202726518
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2661008942
Short name T225
Test name
Test status
Simulation time 32906751028 ps
CPU time 299.28 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:36:23 PM PDT 23
Peak memory 239688 kb
Host smart-ce4c5cac-7b28-4f0f-8a1e-1149e6c89b4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661008942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2661008942
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2213655893
Short name T295
Test name
Test status
Simulation time 7338359957 ps
CPU time 30.4 seconds
Started Oct 01 12:30:47 PM PDT 23
Finished Oct 01 12:31:18 PM PDT 23
Peak memory 211624 kb
Host smart-693ee137-2f51-46b3-ba14-acb9d20d6060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213655893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2213655893
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4224896689
Short name T341
Test name
Test status
Simulation time 100518702 ps
CPU time 5.65 seconds
Started Oct 01 12:30:49 PM PDT 23
Finished Oct 01 12:30:55 PM PDT 23
Peak memory 210940 kb
Host smart-e37022a3-49a3-44de-871a-7c0580429bf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4224896689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4224896689
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.65950621
Short name T181
Test name
Test status
Simulation time 296182196 ps
CPU time 10.47 seconds
Started Oct 01 12:31:35 PM PDT 23
Finished Oct 01 12:31:47 PM PDT 23
Peak memory 212368 kb
Host smart-37ca1a03-dd0f-454b-b69c-94e53089e79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65950621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.65950621
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3832411743
Short name T216
Test name
Test status
Simulation time 5900232013 ps
CPU time 26.99 seconds
Started Oct 01 12:31:09 PM PDT 23
Finished Oct 01 12:31:36 PM PDT 23
Peak memory 214896 kb
Host smart-4b05a0ed-3db0-41ed-ae7a-0d8fa326e9c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832411743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3832411743
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2444319926
Short name T3
Test name
Test status
Simulation time 32168095326 ps
CPU time 1421.9 seconds
Started Oct 01 12:31:32 PM PDT 23
Finished Oct 01 12:55:15 PM PDT 23
Peak memory 233144 kb
Host smart-eb8725ab-5a2e-4c71-a656-638458c433bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444319926 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2444319926
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.987157775
Short name T220
Test name
Test status
Simulation time 1920305007 ps
CPU time 13.78 seconds
Started Oct 01 12:31:23 PM PDT 23
Finished Oct 01 12:31:37 PM PDT 23
Peak memory 210992 kb
Host smart-86864418-5394-4415-8c02-95e642eecceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987157775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.987157775
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3595559285
Short name T19
Test name
Test status
Simulation time 8927209561 ps
CPU time 134.27 seconds
Started Oct 01 12:31:16 PM PDT 23
Finished Oct 01 12:33:30 PM PDT 23
Peak memory 224448 kb
Host smart-c31b89aa-0536-42ec-b182-244170f28032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595559285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3595559285
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.539060488
Short name T404
Test name
Test status
Simulation time 986024143 ps
CPU time 13.09 seconds
Started Oct 01 12:31:18 PM PDT 23
Finished Oct 01 12:31:31 PM PDT 23
Peak memory 211220 kb
Host smart-f578bb6a-42b0-44b6-8196-67c36a9b661d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539060488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.539060488
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.482910519
Short name T269
Test name
Test status
Simulation time 7766560168 ps
CPU time 16.56 seconds
Started Oct 01 12:30:48 PM PDT 23
Finished Oct 01 12:31:05 PM PDT 23
Peak memory 211120 kb
Host smart-add69070-df9b-40c5-b75b-883d9b7331e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482910519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.482910519
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3778300201
Short name T383
Test name
Test status
Simulation time 3083030831 ps
CPU time 33.18 seconds
Started Oct 01 12:30:47 PM PDT 23
Finished Oct 01 12:31:20 PM PDT 23
Peak memory 213016 kb
Host smart-c9361e6b-3f45-402a-b575-ce6422e03c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778300201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3778300201
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1619276874
Short name T77
Test name
Test status
Simulation time 834254403 ps
CPU time 12.73 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:37 PM PDT 23
Peak memory 212664 kb
Host smart-d3b450ea-1163-483b-b5c9-1e6e0c93c11f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619276874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1619276874
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4058908908
Short name T303
Test name
Test status
Simulation time 1995529298 ps
CPU time 16.01 seconds
Started Oct 01 12:31:27 PM PDT 23
Finished Oct 01 12:31:43 PM PDT 23
Peak memory 211072 kb
Host smart-829b845e-89e0-4f7e-95db-31642a42414a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058908908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4058908908
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2366739858
Short name T293
Test name
Test status
Simulation time 4543005496 ps
CPU time 108.35 seconds
Started Oct 01 12:31:34 PM PDT 23
Finished Oct 01 12:33:27 PM PDT 23
Peak memory 237824 kb
Host smart-569af8b5-0087-437c-ac4e-6ab9f097893d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366739858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2366739858
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.231541061
Short name T389
Test name
Test status
Simulation time 5472362275 ps
CPU time 18.09 seconds
Started Oct 01 12:31:26 PM PDT 23
Finished Oct 01 12:31:44 PM PDT 23
Peak memory 211688 kb
Host smart-3bc0773d-f006-49d5-acc9-056590dbb1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231541061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.231541061
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.874563681
Short name T378
Test name
Test status
Simulation time 471846773 ps
CPU time 8.36 seconds
Started Oct 01 12:31:22 PM PDT 23
Finished Oct 01 12:31:31 PM PDT 23
Peak memory 211064 kb
Host smart-3e556221-a65c-4016-b8df-648a3e9e0b54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874563681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.874563681
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2799447022
Short name T15
Test name
Test status
Simulation time 2557622641 ps
CPU time 28.51 seconds
Started Oct 01 12:31:36 PM PDT 23
Finished Oct 01 12:32:05 PM PDT 23
Peak memory 212820 kb
Host smart-105a82f5-438b-41f7-b19f-faca04bcb0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799447022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2799447022
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2178964420
Short name T240
Test name
Test status
Simulation time 1012906279 ps
CPU time 10.4 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:34 PM PDT 23
Peak memory 210948 kb
Host smart-2777c8cf-ca88-40c9-afbb-b4813de3c647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178964420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2178964420
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.546438725
Short name T5
Test name
Test status
Simulation time 100199963118 ps
CPU time 329.35 seconds
Started Oct 01 12:31:09 PM PDT 23
Finished Oct 01 12:36:38 PM PDT 23
Peak memory 237728 kb
Host smart-2ed247e6-20bc-4452-9864-77a33062ec5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546438725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.546438725
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1386590542
Short name T267
Test name
Test status
Simulation time 8235216320 ps
CPU time 14.84 seconds
Started Oct 01 12:30:57 PM PDT 23
Finished Oct 01 12:31:12 PM PDT 23
Peak memory 211896 kb
Host smart-b5777269-d71a-4d62-a117-426dee9156b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386590542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1386590542
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3845604889
Short name T160
Test name
Test status
Simulation time 3441233710 ps
CPU time 10.89 seconds
Started Oct 01 12:31:25 PM PDT 23
Finished Oct 01 12:31:36 PM PDT 23
Peak memory 211156 kb
Host smart-66d6bae2-7037-4f6a-9527-290660f42a4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845604889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3845604889
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2153568040
Short name T151
Test name
Test status
Simulation time 31945510641 ps
CPU time 34.95 seconds
Started Oct 01 12:31:17 PM PDT 23
Finished Oct 01 12:31:52 PM PDT 23
Peak memory 213488 kb
Host smart-3dcc46e5-101b-4291-baf7-9a1b7327458b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153568040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2153568040
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3847320331
Short name T175
Test name
Test status
Simulation time 284826642 ps
CPU time 17.82 seconds
Started Oct 01 12:31:07 PM PDT 23
Finished Oct 01 12:31:26 PM PDT 23
Peak memory 212752 kb
Host smart-4fb0c8c5-c6af-4430-b03f-9c53f25acbbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847320331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3847320331
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3652535066
Short name T315
Test name
Test status
Simulation time 1335200430 ps
CPU time 8.18 seconds
Started Oct 01 12:31:23 PM PDT 23
Finished Oct 01 12:31:32 PM PDT 23
Peak memory 211012 kb
Host smart-8bd808f1-9398-4b0b-bdc5-eab5c8a1fe83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652535066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3652535066
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1878307567
Short name T430
Test name
Test status
Simulation time 79089581476 ps
CPU time 414.54 seconds
Started Oct 01 12:31:26 PM PDT 23
Finished Oct 01 12:38:21 PM PDT 23
Peak memory 234708 kb
Host smart-2cd3652b-b6b6-4458-83f4-1e9d2f4944a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878307567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1878307567
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.61243231
Short name T90
Test name
Test status
Simulation time 5429134687 ps
CPU time 24.43 seconds
Started Oct 01 12:31:05 PM PDT 23
Finished Oct 01 12:31:29 PM PDT 23
Peak memory 211876 kb
Host smart-928502eb-3244-43d7-a3bc-59c0ad65c558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61243231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.61243231
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4294350874
Short name T200
Test name
Test status
Simulation time 101094710 ps
CPU time 5.66 seconds
Started Oct 01 12:31:22 PM PDT 23
Finished Oct 01 12:31:27 PM PDT 23
Peak memory 210936 kb
Host smart-fba6db3c-3aa3-429c-ba11-2dbc39a0e96e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294350874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4294350874
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.918126544
Short name T97
Test name
Test status
Simulation time 1668539703 ps
CPU time 16.84 seconds
Started Oct 01 12:31:12 PM PDT 23
Finished Oct 01 12:31:29 PM PDT 23
Peak memory 212440 kb
Host smart-55d3d869-63f5-43e5-8696-09fbbc1d3278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918126544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.918126544
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1872627442
Short name T239
Test name
Test status
Simulation time 30623647478 ps
CPU time 101.08 seconds
Started Oct 01 12:31:52 PM PDT 23
Finished Oct 01 12:33:33 PM PDT 23
Peak memory 219408 kb
Host smart-df26028f-2cb5-4949-9fa1-e9e97a70eeaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872627442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1872627442
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2357720439
Short name T197
Test name
Test status
Simulation time 109633364399 ps
CPU time 1094.73 seconds
Started Oct 01 12:31:34 PM PDT 23
Finished Oct 01 12:49:49 PM PDT 23
Peak memory 231444 kb
Host smart-5f2c74c9-9517-479a-9498-b749fc1a7524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357720439 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2357720439
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3745108001
Short name T253
Test name
Test status
Simulation time 8197557403 ps
CPU time 15.48 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:40 PM PDT 23
Peak memory 211060 kb
Host smart-5397453f-3ec6-4c81-91ab-1af62bddc259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745108001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3745108001
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.728970974
Short name T406
Test name
Test status
Simulation time 256684563802 ps
CPU time 400.12 seconds
Started Oct 01 12:31:26 PM PDT 23
Finished Oct 01 12:38:07 PM PDT 23
Peak memory 234692 kb
Host smart-3da30eff-3c65-4439-8403-55b62f932866
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728970974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.728970974
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3354719785
Short name T300
Test name
Test status
Simulation time 14895959690 ps
CPU time 32.84 seconds
Started Oct 01 12:31:43 PM PDT 23
Finished Oct 01 12:32:17 PM PDT 23
Peak memory 211520 kb
Host smart-54742df8-e32a-4484-a56a-a851fc73574d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354719785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3354719785
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3577669711
Short name T280
Test name
Test status
Simulation time 1632274996 ps
CPU time 12.78 seconds
Started Oct 01 12:31:31 PM PDT 23
Finished Oct 01 12:31:44 PM PDT 23
Peak memory 211040 kb
Host smart-c17962d5-f020-447a-a82b-fb49cd617dab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577669711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3577669711
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.4086798960
Short name T399
Test name
Test status
Simulation time 2725595622 ps
CPU time 25.47 seconds
Started Oct 01 12:31:38 PM PDT 23
Finished Oct 01 12:32:04 PM PDT 23
Peak memory 212724 kb
Host smart-824cfa1e-a15a-49cb-830f-118438e0aa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086798960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.4086798960
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1659903350
Short name T153
Test name
Test status
Simulation time 10415211443 ps
CPU time 55.94 seconds
Started Oct 01 12:31:03 PM PDT 23
Finished Oct 01 12:31:59 PM PDT 23
Peak memory 216504 kb
Host smart-956a3f06-5ea8-4a7e-80d1-89590ec38d07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659903350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1659903350
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3907536849
Short name T336
Test name
Test status
Simulation time 33363070266 ps
CPU time 1260.44 seconds
Started Oct 01 12:31:30 PM PDT 23
Finished Oct 01 12:52:31 PM PDT 23
Peak memory 229640 kb
Host smart-b7b2fbc0-720c-4203-9480-f08c2ccd3c9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907536849 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.3907536849
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2111982780
Short name T178
Test name
Test status
Simulation time 220494890 ps
CPU time 4.12 seconds
Started Oct 01 12:31:27 PM PDT 23
Finished Oct 01 12:31:32 PM PDT 23
Peak memory 210936 kb
Host smart-384614a3-7402-48a4-b229-42f13ddb83cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111982780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2111982780
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.952376034
Short name T335
Test name
Test status
Simulation time 171621127599 ps
CPU time 297 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:36:21 PM PDT 23
Peak memory 236792 kb
Host smart-61966cb1-7531-4446-b7fd-ea815660cfcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952376034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.952376034
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3873970095
Short name T16
Test name
Test status
Simulation time 2002407897 ps
CPU time 20.91 seconds
Started Oct 01 12:31:36 PM PDT 23
Finished Oct 01 12:31:57 PM PDT 23
Peak memory 211304 kb
Host smart-b9551e5d-ea1d-44b6-92e7-2aa415cb01bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873970095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3873970095
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2769513598
Short name T10
Test name
Test status
Simulation time 386868793 ps
CPU time 5.76 seconds
Started Oct 01 12:31:13 PM PDT 23
Finished Oct 01 12:31:19 PM PDT 23
Peak memory 210924 kb
Host smart-51b174b1-d9af-471b-ac40-581857bc2751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769513598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2769513598
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1655816184
Short name T205
Test name
Test status
Simulation time 184804587 ps
CPU time 10.28 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:31:41 PM PDT 23
Peak memory 212660 kb
Host smart-7d69aee2-0dd6-47e2-9eff-b8e9cfcf2f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655816184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1655816184
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1055274807
Short name T358
Test name
Test status
Simulation time 20126903660 ps
CPU time 74.77 seconds
Started Oct 01 12:31:37 PM PDT 23
Finished Oct 01 12:32:52 PM PDT 23
Peak memory 217464 kb
Host smart-91f207ee-d7ba-4f0f-a7a9-e8213e49f3f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055274807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1055274807
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3950402434
Short name T282
Test name
Test status
Simulation time 162670597810 ps
CPU time 4204.79 seconds
Started Oct 01 12:31:07 PM PDT 23
Finished Oct 01 01:41:12 PM PDT 23
Peak memory 235792 kb
Host smart-008ec375-1705-49a1-a71b-8c97f5fcf0c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950402434 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3950402434
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.248524423
Short name T276
Test name
Test status
Simulation time 334195558 ps
CPU time 4.25 seconds
Started Oct 01 12:31:39 PM PDT 23
Finished Oct 01 12:31:44 PM PDT 23
Peak memory 210960 kb
Host smart-fe09489e-21e2-4850-8353-a564be87fa5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248524423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.248524423
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1684217801
Short name T52
Test name
Test status
Simulation time 56894468015 ps
CPU time 170.51 seconds
Started Oct 01 12:31:25 PM PDT 23
Finished Oct 01 12:34:15 PM PDT 23
Peak memory 234756 kb
Host smart-c9858938-7c5d-4272-97d2-84642b5b7e82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684217801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1684217801
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1811975701
Short name T377
Test name
Test status
Simulation time 4444851276 ps
CPU time 34.64 seconds
Started Oct 01 12:31:32 PM PDT 23
Finished Oct 01 12:32:06 PM PDT 23
Peak memory 211592 kb
Host smart-b775f878-06a1-473f-ae1a-69381582556b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811975701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1811975701
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.725347736
Short name T419
Test name
Test status
Simulation time 1389941847 ps
CPU time 13.16 seconds
Started Oct 01 12:31:06 PM PDT 23
Finished Oct 01 12:31:19 PM PDT 23
Peak memory 211040 kb
Host smart-2ffcec1d-7ebd-469a-973a-f5d8b91ef546
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725347736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.725347736
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.380750235
Short name T409
Test name
Test status
Simulation time 2407473828 ps
CPU time 27.12 seconds
Started Oct 01 12:31:04 PM PDT 23
Finished Oct 01 12:31:32 PM PDT 23
Peak memory 212704 kb
Host smart-287d2467-36db-48f6-b9ce-5abd573b5241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380750235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.380750235
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2680701603
Short name T350
Test name
Test status
Simulation time 123355724 ps
CPU time 8 seconds
Started Oct 01 12:31:42 PM PDT 23
Finished Oct 01 12:31:51 PM PDT 23
Peak memory 211232 kb
Host smart-7154b711-5170-434d-81f7-fbb11712f021
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680701603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2680701603
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1368511924
Short name T40
Test name
Test status
Simulation time 340685005 ps
CPU time 6.48 seconds
Started Oct 01 12:31:22 PM PDT 23
Finished Oct 01 12:31:29 PM PDT 23
Peak memory 211060 kb
Host smart-e0b93cf2-3b14-45f2-941a-aa8452c8c394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368511924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1368511924
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2144299265
Short name T413
Test name
Test status
Simulation time 4757688409 ps
CPU time 181.95 seconds
Started Oct 01 12:31:13 PM PDT 23
Finished Oct 01 12:34:16 PM PDT 23
Peak memory 233724 kb
Host smart-a15cc76f-671d-40ca-9af9-95b49baa5809
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144299265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2144299265
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1371872795
Short name T250
Test name
Test status
Simulation time 689061141 ps
CPU time 11.97 seconds
Started Oct 01 12:31:57 PM PDT 23
Finished Oct 01 12:32:09 PM PDT 23
Peak memory 211052 kb
Host smart-5739c741-5c5f-401d-bc29-90774630b52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371872795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1371872795
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2764920862
Short name T157
Test name
Test status
Simulation time 10440513971 ps
CPU time 13.84 seconds
Started Oct 01 12:31:19 PM PDT 23
Finished Oct 01 12:31:33 PM PDT 23
Peak memory 211000 kb
Host smart-b44c237c-2532-4e5b-b986-109fa862f386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2764920862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2764920862
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2382407597
Short name T289
Test name
Test status
Simulation time 3014167994 ps
CPU time 15.41 seconds
Started Oct 01 12:31:13 PM PDT 23
Finished Oct 01 12:31:28 PM PDT 23
Peak memory 212956 kb
Host smart-addc263e-9d54-42ec-a9ef-e3ba69ddd8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382407597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2382407597
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1649733902
Short name T400
Test name
Test status
Simulation time 5119720917 ps
CPU time 37.05 seconds
Started Oct 01 12:31:14 PM PDT 23
Finished Oct 01 12:31:52 PM PDT 23
Peak memory 215796 kb
Host smart-aa662960-25fe-4eb5-97f9-5b57c5e6f807
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649733902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1649733902
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3767328510
Short name T418
Test name
Test status
Simulation time 333186744 ps
CPU time 4.44 seconds
Started Oct 01 12:19:59 PM PDT 23
Finished Oct 01 12:20:04 PM PDT 23
Peak memory 211012 kb
Host smart-b9e0a2b4-7b09-4261-95dc-b1a92cc166f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767328510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3767328510
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1340429070
Short name T233
Test name
Test status
Simulation time 331017483016 ps
CPU time 591.36 seconds
Started Oct 01 12:19:36 PM PDT 23
Finished Oct 01 12:29:29 PM PDT 23
Peak memory 227300 kb
Host smart-64c16bdd-bf63-4132-a260-838db4595e81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340429070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1340429070
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2473410803
Short name T342
Test name
Test status
Simulation time 4433788010 ps
CPU time 16.42 seconds
Started Oct 01 12:20:32 PM PDT 23
Finished Oct 01 12:20:48 PM PDT 23
Peak memory 211688 kb
Host smart-cb4aedd2-e0ee-4e5d-9cfd-c67cc45397be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473410803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2473410803
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3658888747
Short name T154
Test name
Test status
Simulation time 8596518899 ps
CPU time 17.52 seconds
Started Oct 01 12:18:40 PM PDT 23
Finished Oct 01 12:18:58 PM PDT 23
Peak memory 210276 kb
Host smart-b7094cc0-0888-466b-8d7e-85115c54fe78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658888747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3658888747
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.944824569
Short name T37
Test name
Test status
Simulation time 3969380478 ps
CPU time 66.08 seconds
Started Oct 01 12:19:35 PM PDT 23
Finished Oct 01 12:20:43 PM PDT 23
Peak memory 236976 kb
Host smart-c9957b1b-9da7-4800-93ca-09ae944bf68c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944824569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.944824569
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2899414100
Short name T148
Test name
Test status
Simulation time 366043400 ps
CPU time 9.97 seconds
Started Oct 01 12:21:15 PM PDT 23
Finished Oct 01 12:21:31 PM PDT 23
Peak memory 212508 kb
Host smart-d5a25941-5859-4ba1-bf76-b653db582764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899414100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2899414100
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.399982273
Short name T278
Test name
Test status
Simulation time 4729035014 ps
CPU time 12.21 seconds
Started Oct 01 12:18:40 PM PDT 23
Finished Oct 01 12:18:52 PM PDT 23
Peak memory 210436 kb
Host smart-985ca174-2cc1-4131-9aec-45b470d413bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399982273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.399982273
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.404474999
Short name T21
Test name
Test status
Simulation time 51558912339 ps
CPU time 453.67 seconds
Started Oct 01 12:19:41 PM PDT 23
Finished Oct 01 12:27:15 PM PDT 23
Peak memory 232920 kb
Host smart-405115a3-4765-4d23-88fd-a319c2735b0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404474999 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.404474999
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1779984316
Short name T209
Test name
Test status
Simulation time 2618158992 ps
CPU time 8.61 seconds
Started Oct 01 12:31:57 PM PDT 23
Finished Oct 01 12:32:06 PM PDT 23
Peak memory 211152 kb
Host smart-151924b1-91cc-41da-82f2-309237abc182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779984316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1779984316
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3515776419
Short name T311
Test name
Test status
Simulation time 26182780962 ps
CPU time 26.39 seconds
Started Oct 01 12:31:44 PM PDT 23
Finished Oct 01 12:32:11 PM PDT 23
Peak memory 211588 kb
Host smart-fe603f18-0989-40bf-986f-d88a44f7f21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515776419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3515776419
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1401775983
Short name T204
Test name
Test status
Simulation time 383354607 ps
CPU time 5.63 seconds
Started Oct 01 12:31:32 PM PDT 23
Finished Oct 01 12:31:38 PM PDT 23
Peak memory 210888 kb
Host smart-8f408807-6b13-4b8c-b9fa-f1ee5a082cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401775983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1401775983
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3693862456
Short name T263
Test name
Test status
Simulation time 3347356318 ps
CPU time 16.24 seconds
Started Oct 01 12:31:43 PM PDT 23
Finished Oct 01 12:31:59 PM PDT 23
Peak memory 213348 kb
Host smart-687b7838-495c-4925-831e-1a8f603b24c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693862456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3693862456
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1507900327
Short name T398
Test name
Test status
Simulation time 768664874 ps
CPU time 15.17 seconds
Started Oct 01 12:31:48 PM PDT 23
Finished Oct 01 12:32:04 PM PDT 23
Peak memory 213488 kb
Host smart-2d7a4765-1d16-4126-a129-fda5248886d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507900327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1507900327
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1445079327
Short name T427
Test name
Test status
Simulation time 50516451233 ps
CPU time 6264.53 seconds
Started Oct 01 12:31:26 PM PDT 23
Finished Oct 01 02:15:51 PM PDT 23
Peak memory 235820 kb
Host smart-7dc496a5-afe9-4f8a-a350-d92b5eac4154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445079327 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1445079327
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1006415531
Short name T332
Test name
Test status
Simulation time 1641378413 ps
CPU time 13.31 seconds
Started Oct 01 12:31:17 PM PDT 23
Finished Oct 01 12:31:30 PM PDT 23
Peak memory 211084 kb
Host smart-51cebeed-2319-4d94-82b6-54238d16b547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006415531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1006415531
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2738828805
Short name T381
Test name
Test status
Simulation time 21728556795 ps
CPU time 193.11 seconds
Started Oct 01 12:31:28 PM PDT 23
Finished Oct 01 12:34:43 PM PDT 23
Peak memory 237744 kb
Host smart-f0c02b1b-1e4d-498d-8ec4-2f4ea1727430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738828805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2738828805
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2691999472
Short name T202
Test name
Test status
Simulation time 2351955747 ps
CPU time 17.42 seconds
Started Oct 01 12:31:07 PM PDT 23
Finished Oct 01 12:31:24 PM PDT 23
Peak memory 211448 kb
Host smart-7c690ecc-63e3-4fc3-89cc-97f60628d2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691999472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2691999472
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.496722407
Short name T236
Test name
Test status
Simulation time 1827517240 ps
CPU time 11.03 seconds
Started Oct 01 12:31:43 PM PDT 23
Finished Oct 01 12:31:54 PM PDT 23
Peak memory 210884 kb
Host smart-93df3eb5-544f-4a82-8b66-76367f37bcaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496722407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.496722407
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3671240423
Short name T192
Test name
Test status
Simulation time 12344344989 ps
CPU time 34.39 seconds
Started Oct 01 12:31:19 PM PDT 23
Finished Oct 01 12:31:54 PM PDT 23
Peak memory 213812 kb
Host smart-9deb08d5-59fc-4d56-8b27-97f00184585f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671240423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3671240423
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2888800231
Short name T395
Test name
Test status
Simulation time 19542237253 ps
CPU time 50.89 seconds
Started Oct 01 12:31:36 PM PDT 23
Finished Oct 01 12:32:28 PM PDT 23
Peak memory 212820 kb
Host smart-c475a601-612a-4577-8fc2-01e354b4901c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888800231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2888800231
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.645330260
Short name T372
Test name
Test status
Simulation time 346932321 ps
CPU time 4.27 seconds
Started Oct 01 12:31:20 PM PDT 23
Finished Oct 01 12:31:25 PM PDT 23
Peak memory 210980 kb
Host smart-dd06446c-b6e2-40e7-9592-6e0a76afcecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645330260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.645330260
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1498773485
Short name T308
Test name
Test status
Simulation time 11212013486 ps
CPU time 178.13 seconds
Started Oct 01 12:31:25 PM PDT 23
Finished Oct 01 12:34:29 PM PDT 23
Peak memory 228416 kb
Host smart-b4eef508-723f-4000-8782-8ddf6f610711
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498773485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1498773485
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.712597268
Short name T18
Test name
Test status
Simulation time 1648143679 ps
CPU time 19.54 seconds
Started Oct 01 12:31:32 PM PDT 23
Finished Oct 01 12:31:52 PM PDT 23
Peak memory 211084 kb
Host smart-ba62e6d7-e868-4a28-aec8-b3233adfb115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712597268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.712597268
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1912845579
Short name T349
Test name
Test status
Simulation time 8650740344 ps
CPU time 15.52 seconds
Started Oct 01 12:31:15 PM PDT 23
Finished Oct 01 12:31:30 PM PDT 23
Peak memory 211144 kb
Host smart-ce3f2726-9305-497a-bc98-4bd64173ccaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912845579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1912845579
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3225787054
Short name T394
Test name
Test status
Simulation time 38382733125 ps
CPU time 26.27 seconds
Started Oct 01 12:31:17 PM PDT 23
Finished Oct 01 12:31:44 PM PDT 23
Peak memory 213124 kb
Host smart-b4003254-e739-41af-9299-3daa5e6dea0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225787054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3225787054
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2357721744
Short name T297
Test name
Test status
Simulation time 16437954600 ps
CPU time 43.36 seconds
Started Oct 01 12:31:31 PM PDT 23
Finished Oct 01 12:32:15 PM PDT 23
Peak memory 219332 kb
Host smart-7bce2279-eded-4194-9e0a-0f3821c0b478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357721744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2357721744
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3636467212
Short name T232
Test name
Test status
Simulation time 501645695 ps
CPU time 7.32 seconds
Started Oct 01 12:31:33 PM PDT 23
Finished Oct 01 12:31:41 PM PDT 23
Peak memory 210920 kb
Host smart-fa74060f-ebd7-4eb2-a97e-4cffe6a6bca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636467212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3636467212
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2723318841
Short name T279
Test name
Test status
Simulation time 68627195696 ps
CPU time 713.84 seconds
Started Oct 01 12:31:46 PM PDT 23
Finished Oct 01 12:43:41 PM PDT 23
Peak memory 225492 kb
Host smart-2732a35d-1165-4636-8157-5fac64a50c4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723318841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2723318841
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1427392067
Short name T91
Test name
Test status
Simulation time 664665347 ps
CPU time 9.78 seconds
Started Oct 01 12:31:40 PM PDT 23
Finished Oct 01 12:31:51 PM PDT 23
Peak memory 211228 kb
Host smart-5c7ab0ce-037f-4ce8-a356-a457603946a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427392067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1427392067
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3494629293
Short name T261
Test name
Test status
Simulation time 1869996075 ps
CPU time 15.41 seconds
Started Oct 01 12:31:50 PM PDT 23
Finished Oct 01 12:32:06 PM PDT 23
Peak memory 210964 kb
Host smart-67bdb0ec-f951-4b1f-b7cf-afd32aaed65c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494629293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3494629293
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2751789162
Short name T296
Test name
Test status
Simulation time 4135972992 ps
CPU time 24.82 seconds
Started Oct 01 12:31:19 PM PDT 23
Finished Oct 01 12:31:44 PM PDT 23
Peak memory 212120 kb
Host smart-6034fa5f-e29d-483b-aec1-e23610f88f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751789162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2751789162
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1123833345
Short name T208
Test name
Test status
Simulation time 8866820360 ps
CPU time 69.8 seconds
Started Oct 01 12:31:24 PM PDT 23
Finished Oct 01 12:32:34 PM PDT 23
Peak memory 215904 kb
Host smart-581633cd-6969-4ab7-bdc1-12d34de565f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123833345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1123833345
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.259296681
Short name T182
Test name
Test status
Simulation time 126003881272 ps
CPU time 705 seconds
Started Oct 01 12:31:53 PM PDT 23
Finished Oct 01 12:43:44 PM PDT 23
Peak memory 229488 kb
Host smart-b7149eb8-f783-4efc-9d93-5b6dd624d17d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259296681 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.259296681
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1766620933
Short name T285
Test name
Test status
Simulation time 1600882547 ps
CPU time 14.03 seconds
Started Oct 01 12:31:39 PM PDT 23
Finished Oct 01 12:31:53 PM PDT 23
Peak memory 210948 kb
Host smart-924b3a3e-b64a-4782-b4ef-640cdd6c65aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766620933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1766620933
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3863423162
Short name T49
Test name
Test status
Simulation time 10104225257 ps
CPU time 224.63 seconds
Started Oct 01 12:31:37 PM PDT 23
Finished Oct 01 12:35:22 PM PDT 23
Peak memory 212368 kb
Host smart-61f91296-a636-4d51-8c1c-dcddd99ae194
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863423162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3863423162
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1584346183
Short name T314
Test name
Test status
Simulation time 3091915627 ps
CPU time 14.57 seconds
Started Oct 01 12:31:32 PM PDT 23
Finished Oct 01 12:31:47 PM PDT 23
Peak memory 211324 kb
Host smart-4aba1661-6bcd-484e-a5c6-c92c63ef2989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584346183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1584346183
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3265637636
Short name T245
Test name
Test status
Simulation time 8932217724 ps
CPU time 17.7 seconds
Started Oct 01 12:31:50 PM PDT 23
Finished Oct 01 12:32:08 PM PDT 23
Peak memory 211184 kb
Host smart-8c42ce11-c9b5-4a0a-966f-fa1024b69453
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265637636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3265637636
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4202446058
Short name T367
Test name
Test status
Simulation time 5064944596 ps
CPU time 25.16 seconds
Started Oct 01 12:30:45 PM PDT 23
Finished Oct 01 12:31:11 PM PDT 23
Peak memory 213360 kb
Host smart-f80ae08b-9cf7-4cb2-9bf6-952700b7203e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202446058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4202446058
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.131437843
Short name T371
Test name
Test status
Simulation time 2249303537 ps
CPU time 16.08 seconds
Started Oct 01 12:31:31 PM PDT 23
Finished Oct 01 12:31:47 PM PDT 23
Peak memory 213060 kb
Host smart-5d4f4579-83ea-4dec-a58a-095fd0b6c0df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131437843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.131437843
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3793101358
Short name T329
Test name
Test status
Simulation time 8714016381 ps
CPU time 12.57 seconds
Started Oct 01 12:31:30 PM PDT 23
Finished Oct 01 12:31:43 PM PDT 23
Peak memory 211196 kb
Host smart-3b3ee023-57ca-473f-91f6-4738e0b46948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793101358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3793101358
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2292421278
Short name T213
Test name
Test status
Simulation time 10905681087 ps
CPU time 195.81 seconds
Started Oct 01 12:31:06 PM PDT 23
Finished Oct 01 12:34:22 PM PDT 23
Peak memory 237620 kb
Host smart-14930b7e-4f71-4136-b5ca-2dedaf1efce3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292421278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2292421278
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2720308421
Short name T194
Test name
Test status
Simulation time 1909452947 ps
CPU time 12.93 seconds
Started Oct 01 12:31:33 PM PDT 23
Finished Oct 01 12:31:47 PM PDT 23
Peak memory 211252 kb
Host smart-170d176b-7475-4882-9e25-0b0439cbab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720308421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2720308421
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3177527464
Short name T234
Test name
Test status
Simulation time 2058702973 ps
CPU time 16.25 seconds
Started Oct 01 12:31:30 PM PDT 23
Finished Oct 01 12:31:47 PM PDT 23
Peak memory 211060 kb
Host smart-1b2762e8-0664-4750-b121-97e35e444690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177527464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3177527464
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.663239522
Short name T428
Test name
Test status
Simulation time 242099025 ps
CPU time 10.39 seconds
Started Oct 01 12:31:08 PM PDT 23
Finished Oct 01 12:31:19 PM PDT 23
Peak memory 212576 kb
Host smart-06d8bd35-5589-426a-b568-059ff11c4907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663239522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.663239522
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2434030291
Short name T206
Test name
Test status
Simulation time 6124705721 ps
CPU time 33.15 seconds
Started Oct 01 12:31:23 PM PDT 23
Finished Oct 01 12:31:56 PM PDT 23
Peak memory 219228 kb
Host smart-98477e3b-0811-402d-aee7-b0717580d924
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434030291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2434030291
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.309684499
Short name T237
Test name
Test status
Simulation time 142453887923 ps
CPU time 2239.85 seconds
Started Oct 01 12:31:29 PM PDT 23
Finished Oct 01 01:08:51 PM PDT 23
Peak memory 235796 kb
Host smart-1ba02645-625f-46e9-b5b9-696310d80548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309684499 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.309684499
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3078844711
Short name T163
Test name
Test status
Simulation time 1288488656 ps
CPU time 11.77 seconds
Started Oct 01 12:31:12 PM PDT 23
Finished Oct 01 12:31:24 PM PDT 23
Peak memory 210900 kb
Host smart-0d5a1dfc-44a6-469f-b5e5-0042cdbaec45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078844711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3078844711
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.144468328
Short name T309
Test name
Test status
Simulation time 42593486573 ps
CPU time 232.25 seconds
Started Oct 01 12:31:07 PM PDT 23
Finished Oct 01 12:35:00 PM PDT 23
Peak memory 232432 kb
Host smart-4c2e24bc-fd7b-4d66-a8ac-324d0952ce32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144468328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.144468328
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1434515685
Short name T215
Test name
Test status
Simulation time 12631631832 ps
CPU time 27.84 seconds
Started Oct 01 12:31:19 PM PDT 23
Finished Oct 01 12:31:47 PM PDT 23
Peak memory 211524 kb
Host smart-f90d68f9-5b30-4d4a-b592-e225102cd5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434515685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1434515685
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2674098803
Short name T292
Test name
Test status
Simulation time 4522744350 ps
CPU time 17.52 seconds
Started Oct 01 12:31:51 PM PDT 23
Finished Oct 01 12:32:09 PM PDT 23
Peak memory 211164 kb
Host smart-acf5181b-c22e-4b36-a830-657ba08c8e5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674098803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2674098803
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2351896050
Short name T257
Test name
Test status
Simulation time 3797785902 ps
CPU time 31.96 seconds
Started Oct 01 12:31:19 PM PDT 23
Finished Oct 01 12:31:51 PM PDT 23
Peak memory 213116 kb
Host smart-2e0a2b9d-bab8-4cc7-b1c6-dbecd971fa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351896050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2351896050
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.4225931084
Short name T227
Test name
Test status
Simulation time 29729911164 ps
CPU time 70.87 seconds
Started Oct 01 12:31:45 PM PDT 23
Finished Oct 01 12:32:56 PM PDT 23
Peak memory 216536 kb
Host smart-1884bb80-0666-47fc-a7a5-6f4a8785a62b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225931084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.4225931084
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3258656811
Short name T203
Test name
Test status
Simulation time 1164485010 ps
CPU time 11.1 seconds
Started Oct 01 12:31:59 PM PDT 23
Finished Oct 01 12:32:11 PM PDT 23
Peak memory 211044 kb
Host smart-55324fb5-b243-4758-a100-bd9b43daaef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258656811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3258656811
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4290369590
Short name T51
Test name
Test status
Simulation time 53070487377 ps
CPU time 230.89 seconds
Started Oct 01 12:31:26 PM PDT 23
Finished Oct 01 12:35:17 PM PDT 23
Peak memory 233768 kb
Host smart-0d3bb0c4-8536-477c-90f8-f8d0c850b7a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290369590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4290369590
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4052205611
Short name T231
Test name
Test status
Simulation time 11282442751 ps
CPU time 26.8 seconds
Started Oct 01 12:31:35 PM PDT 23
Finished Oct 01 12:32:03 PM PDT 23
Peak memory 211488 kb
Host smart-14f8544c-c535-470b-96ad-1813428750d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052205611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4052205611
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1051958062
Short name T325
Test name
Test status
Simulation time 3278045979 ps
CPU time 8.45 seconds
Started Oct 01 12:31:48 PM PDT 23
Finished Oct 01 12:31:56 PM PDT 23
Peak memory 211176 kb
Host smart-e323126c-938d-4c91-ae2c-1b219c611b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051958062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1051958062
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1102938302
Short name T408
Test name
Test status
Simulation time 1639227873 ps
CPU time 10.2 seconds
Started Oct 01 12:31:26 PM PDT 23
Finished Oct 01 12:31:37 PM PDT 23
Peak memory 213184 kb
Host smart-2bc4fb14-173e-4ed4-9c32-a55c1fa49a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102938302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1102938302
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3049324677
Short name T258
Test name
Test status
Simulation time 6593225907 ps
CPU time 67.69 seconds
Started Oct 01 12:31:29 PM PDT 23
Finished Oct 01 12:32:49 PM PDT 23
Peak memory 216572 kb
Host smart-e11d235e-347d-42e0-b770-ad166eb610c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049324677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3049324677
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.83198095
Short name T210
Test name
Test status
Simulation time 100934723923 ps
CPU time 1683.81 seconds
Started Oct 01 12:31:41 PM PDT 23
Finished Oct 01 12:59:46 PM PDT 23
Peak memory 235772 kb
Host smart-b08c90aa-ee25-4064-94f2-02573e3f64e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83198095 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.83198095
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2574019066
Short name T431
Test name
Test status
Simulation time 592672543 ps
CPU time 4.36 seconds
Started Oct 01 12:31:37 PM PDT 23
Finished Oct 01 12:31:42 PM PDT 23
Peak memory 210948 kb
Host smart-555fd8f5-144a-47c6-adfb-ede9f233a8d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574019066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2574019066
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.300364325
Short name T301
Test name
Test status
Simulation time 7382262818 ps
CPU time 31.67 seconds
Started Oct 01 12:32:13 PM PDT 23
Finished Oct 01 12:32:45 PM PDT 23
Peak memory 211420 kb
Host smart-de86fa24-1df3-424f-8afc-eb774942881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300364325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.300364325
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3137331277
Short name T403
Test name
Test status
Simulation time 357815455 ps
CPU time 7.94 seconds
Started Oct 01 12:31:35 PM PDT 23
Finished Oct 01 12:31:44 PM PDT 23
Peak memory 210920 kb
Host smart-afa3e52d-9bd3-4baf-b36b-a116f45e8ac6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3137331277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3137331277
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1933435821
Short name T191
Test name
Test status
Simulation time 192183969 ps
CPU time 10.01 seconds
Started Oct 01 12:31:28 PM PDT 23
Finished Oct 01 12:31:41 PM PDT 23
Peak memory 212648 kb
Host smart-1fbe7877-7684-4562-b6c7-f0f20c06366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933435821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1933435821
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.723397220
Short name T401
Test name
Test status
Simulation time 8106551393 ps
CPU time 35.37 seconds
Started Oct 01 12:31:31 PM PDT 23
Finished Oct 01 12:32:06 PM PDT 23
Peak memory 214424 kb
Host smart-86f5525b-bf6f-4419-a647-ea918e90a4d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723397220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.723397220
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.737936206
Short name T174
Test name
Test status
Simulation time 92966815936 ps
CPU time 6179.29 seconds
Started Oct 01 12:31:44 PM PDT 23
Finished Oct 01 02:14:44 PM PDT 23
Peak memory 232732 kb
Host smart-03c4e585-3291-408e-9208-3c87ff3ffae9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737936206 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.737936206
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3742498466
Short name T176
Test name
Test status
Simulation time 2201720791 ps
CPU time 16.8 seconds
Started Oct 01 12:31:15 PM PDT 23
Finished Oct 01 12:31:32 PM PDT 23
Peak memory 211032 kb
Host smart-2b680a5f-e450-4953-ba78-45817c7a8b80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742498466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3742498466
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1002754523
Short name T302
Test name
Test status
Simulation time 28515807926 ps
CPU time 138.63 seconds
Started Oct 01 12:31:57 PM PDT 23
Finished Oct 01 12:34:16 PM PDT 23
Peak memory 237768 kb
Host smart-550ed419-423b-4553-a373-5d04a1e915b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002754523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1002754523
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1727806136
Short name T271
Test name
Test status
Simulation time 3310263840 ps
CPU time 29.03 seconds
Started Oct 01 12:31:59 PM PDT 23
Finished Oct 01 12:32:28 PM PDT 23
Peak memory 211076 kb
Host smart-590eec87-ca82-47af-8fc5-d36aa1350632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727806136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1727806136
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.587254989
Short name T388
Test name
Test status
Simulation time 5802898387 ps
CPU time 13.95 seconds
Started Oct 01 12:31:41 PM PDT 23
Finished Oct 01 12:31:55 PM PDT 23
Peak memory 211184 kb
Host smart-e8e53a28-52c7-4bd8-954a-ceed47e52587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587254989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.587254989
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1149590639
Short name T248
Test name
Test status
Simulation time 2056665347 ps
CPU time 23.7 seconds
Started Oct 01 12:32:18 PM PDT 23
Finished Oct 01 12:32:42 PM PDT 23
Peak memory 212880 kb
Host smart-84904179-8f89-4d00-82d1-fb478b2bef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149590639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1149590639
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2550101136
Short name T199
Test name
Test status
Simulation time 10162799308 ps
CPU time 90.52 seconds
Started Oct 01 12:31:44 PM PDT 23
Finished Oct 01 12:33:15 PM PDT 23
Peak memory 217844 kb
Host smart-ce6c5dc9-49c3-4415-9d84-9d835fcfb225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550101136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2550101136
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3750592403
Short name T224
Test name
Test status
Simulation time 25541445269 ps
CPU time 535.63 seconds
Started Oct 01 12:31:49 PM PDT 23
Finished Oct 01 12:40:45 PM PDT 23
Peak memory 227620 kb
Host smart-6eaeaffb-f316-45fc-b789-26b4fa611be2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750592403 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3750592403
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2358665752
Short name T328
Test name
Test status
Simulation time 6604549230 ps
CPU time 14.28 seconds
Started Oct 01 12:21:20 PM PDT 23
Finished Oct 01 12:21:35 PM PDT 23
Peak memory 211064 kb
Host smart-9c3c7563-351a-48b3-aa9f-7efae4c17537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358665752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2358665752
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2443752675
Short name T95
Test name
Test status
Simulation time 91685670388 ps
CPU time 279 seconds
Started Oct 01 12:23:42 PM PDT 23
Finished Oct 01 12:28:21 PM PDT 23
Peak memory 234860 kb
Host smart-3bf05e2a-8750-4c8c-8eff-a6c61a49bec0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443752675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2443752675
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.503854539
Short name T219
Test name
Test status
Simulation time 3601259558 ps
CPU time 20.21 seconds
Started Oct 01 12:21:04 PM PDT 23
Finished Oct 01 12:21:25 PM PDT 23
Peak memory 211216 kb
Host smart-b558f44a-44e0-4750-a751-141a7cd048dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503854539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.503854539
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.574554263
Short name T365
Test name
Test status
Simulation time 99753845 ps
CPU time 5.36 seconds
Started Oct 01 12:20:49 PM PDT 23
Finished Oct 01 12:20:54 PM PDT 23
Peak memory 211016 kb
Host smart-d8548e8f-a77f-47e6-9aa7-3143146b2afd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=574554263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.574554263
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3043237965
Short name T326
Test name
Test status
Simulation time 12261572564 ps
CPU time 31.21 seconds
Started Oct 01 12:19:36 PM PDT 23
Finished Oct 01 12:20:09 PM PDT 23
Peak memory 213884 kb
Host smart-3f7d7188-f37d-41b3-ae0f-a5e693a6d3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043237965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3043237965
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1316752961
Short name T351
Test name
Test status
Simulation time 13250566375 ps
CPU time 131.78 seconds
Started Oct 01 12:19:41 PM PDT 23
Finished Oct 01 12:21:53 PM PDT 23
Peak memory 216756 kb
Host smart-a415bd2b-d825-4b3f-925d-bf0b197d3e35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316752961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1316752961
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.795212227
Short name T322
Test name
Test status
Simulation time 1550391285 ps
CPU time 5.28 seconds
Started Oct 01 12:30:53 PM PDT 23
Finished Oct 01 12:30:58 PM PDT 23
Peak memory 210940 kb
Host smart-62eea470-67dc-4614-8e39-b8efde19440d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795212227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.795212227
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1175413643
Short name T359
Test name
Test status
Simulation time 119332501372 ps
CPU time 171.78 seconds
Started Oct 01 12:20:53 PM PDT 23
Finished Oct 01 12:23:45 PM PDT 23
Peak memory 228260 kb
Host smart-257c3915-a4e4-45f3-80b1-d34d919c0494
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175413643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1175413643
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2154800237
Short name T412
Test name
Test status
Simulation time 693582347 ps
CPU time 9.71 seconds
Started Oct 01 12:22:57 PM PDT 23
Finished Oct 01 12:23:06 PM PDT 23
Peak memory 211380 kb
Host smart-9cfb6ba7-9833-4def-a3ad-74a0a34cacf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154800237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2154800237
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.104892050
Short name T340
Test name
Test status
Simulation time 7706581029 ps
CPU time 16.39 seconds
Started Oct 01 12:30:25 PM PDT 23
Finished Oct 01 12:30:42 PM PDT 23
Peak memory 211136 kb
Host smart-161e72eb-3e17-4133-b86a-d4c4516f0899
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104892050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.104892050
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2731330426
Short name T410
Test name
Test status
Simulation time 3389187693 ps
CPU time 33.34 seconds
Started Oct 01 12:20:51 PM PDT 23
Finished Oct 01 12:21:24 PM PDT 23
Peak memory 212988 kb
Host smart-5445f7e4-65d6-4673-ad55-6cf476775dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731330426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2731330426
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1394842439
Short name T283
Test name
Test status
Simulation time 3360473326 ps
CPU time 24.71 seconds
Started Oct 01 12:22:51 PM PDT 23
Finished Oct 01 12:23:16 PM PDT 23
Peak memory 215852 kb
Host smart-e37ba760-5798-41d0-bb62-df1527b223bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394842439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1394842439
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.764426639
Short name T320
Test name
Test status
Simulation time 46096791484 ps
CPU time 398.64 seconds
Started Oct 01 12:23:04 PM PDT 23
Finished Oct 01 12:29:43 PM PDT 23
Peak memory 231752 kb
Host smart-e722df41-f311-47c6-94f5-a4db2a9cd763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764426639 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.764426639
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1826515467
Short name T214
Test name
Test status
Simulation time 1660126882 ps
CPU time 8.55 seconds
Started Oct 01 12:30:45 PM PDT 23
Finished Oct 01 12:30:59 PM PDT 23
Peak memory 211036 kb
Host smart-3b5ec428-794c-4328-b788-6c072552aeac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826515467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1826515467
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4175282577
Short name T48
Test name
Test status
Simulation time 9893030537 ps
CPU time 81.35 seconds
Started Oct 01 12:30:52 PM PDT 23
Finished Oct 01 12:32:13 PM PDT 23
Peak memory 237684 kb
Host smart-7301dd95-349c-40de-b27d-db01c384ca2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175282577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.4175282577
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3193828927
Short name T207
Test name
Test status
Simulation time 3043743894 ps
CPU time 27.28 seconds
Started Oct 01 12:31:21 PM PDT 23
Finished Oct 01 12:31:48 PM PDT 23
Peak memory 211840 kb
Host smart-0dafffc8-351d-4bbc-ada4-21f0b5414187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193828927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3193828927
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3115064213
Short name T273
Test name
Test status
Simulation time 4257152634 ps
CPU time 16.77 seconds
Started Oct 01 12:30:54 PM PDT 23
Finished Oct 01 12:31:11 PM PDT 23
Peak memory 211104 kb
Host smart-d26d8325-3631-4681-b524-5a9e8008fcba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115064213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3115064213
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3578852186
Short name T222
Test name
Test status
Simulation time 2681127441 ps
CPU time 23.66 seconds
Started Oct 01 12:30:54 PM PDT 23
Finished Oct 01 12:31:18 PM PDT 23
Peak memory 212884 kb
Host smart-b4ee81fd-a604-4f40-a880-60670ad80a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578852186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3578852186
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.734244351
Short name T4
Test name
Test status
Simulation time 1095148825 ps
CPU time 22.46 seconds
Started Oct 01 12:30:37 PM PDT 23
Finished Oct 01 12:31:00 PM PDT 23
Peak memory 215984 kb
Host smart-4ccaa458-f028-4852-8256-93e78d992fa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734244351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.734244351
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3351944272
Short name T305
Test name
Test status
Simulation time 25149676449 ps
CPU time 1425.18 seconds
Started Oct 01 12:30:46 PM PDT 23
Finished Oct 01 12:54:31 PM PDT 23
Peak memory 227692 kb
Host smart-5463d311-5688-4af3-b7ba-1713c5ec5075
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351944272 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3351944272
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3973481465
Short name T397
Test name
Test status
Simulation time 690198685 ps
CPU time 5.41 seconds
Started Oct 01 12:30:55 PM PDT 23
Finished Oct 01 12:31:04 PM PDT 23
Peak memory 210892 kb
Host smart-06ba9d52-d8a6-45cc-9fe0-ae02902694b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973481465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3973481465
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.568064529
Short name T324
Test name
Test status
Simulation time 22180804878 ps
CPU time 260.88 seconds
Started Oct 01 12:30:46 PM PDT 23
Finished Oct 01 12:35:07 PM PDT 23
Peak memory 238624 kb
Host smart-39bac77d-0230-4861-a1bc-6b3fa49d68cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568064529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.568064529
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.92608475
Short name T344
Test name
Test status
Simulation time 23243081785 ps
CPU time 28.01 seconds
Started Oct 01 12:31:05 PM PDT 23
Finished Oct 01 12:31:39 PM PDT 23
Peak memory 211492 kb
Host smart-150e89e3-7df1-4204-af07-b966f8caba97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92608475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.92608475
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.192477522
Short name T93
Test name
Test status
Simulation time 4139106117 ps
CPU time 9.5 seconds
Started Oct 01 12:31:22 PM PDT 23
Finished Oct 01 12:31:32 PM PDT 23
Peak memory 211084 kb
Host smart-37bbacb4-a091-4c5f-b524-11f905f332cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192477522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.192477522
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1319832843
Short name T429
Test name
Test status
Simulation time 1907197986 ps
CPU time 16.8 seconds
Started Oct 01 12:30:45 PM PDT 23
Finished Oct 01 12:31:02 PM PDT 23
Peak memory 211744 kb
Host smart-d8065246-10af-49de-b84b-22d4956b7732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319832843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1319832843
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.160517403
Short name T287
Test name
Test status
Simulation time 6409144619 ps
CPU time 54.39 seconds
Started Oct 01 12:31:05 PM PDT 23
Finished Oct 01 12:31:59 PM PDT 23
Peak memory 216184 kb
Host smart-13f5f348-41ae-4304-a8d9-45830e6768fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160517403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.160517403
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2700248901
Short name T298
Test name
Test status
Simulation time 186961704736 ps
CPU time 1619.72 seconds
Started Oct 01 12:31:33 PM PDT 23
Finished Oct 01 12:58:34 PM PDT 23
Peak memory 237428 kb
Host smart-21609a49-18f2-4531-80c9-c42a9579850d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700248901 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2700248901
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1836366528
Short name T432
Test name
Test status
Simulation time 1751979550 ps
CPU time 14.92 seconds
Started Oct 01 12:30:53 PM PDT 23
Finished Oct 01 12:31:08 PM PDT 23
Peak memory 211156 kb
Host smart-318799f3-d309-4ece-b487-e2a99022cfab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836366528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1836366528
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1323769642
Short name T426
Test name
Test status
Simulation time 20198242602 ps
CPU time 290.45 seconds
Started Oct 01 12:30:52 PM PDT 23
Finished Oct 01 12:35:43 PM PDT 23
Peak memory 224480 kb
Host smart-ccd5a44b-252f-4fef-b3cf-dca520377167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323769642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1323769642
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4170173815
Short name T333
Test name
Test status
Simulation time 1276249673 ps
CPU time 9.59 seconds
Started Oct 01 12:30:53 PM PDT 23
Finished Oct 01 12:31:03 PM PDT 23
Peak memory 211204 kb
Host smart-3953d385-a122-4a5a-b050-538f525766d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170173815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4170173815
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2611281994
Short name T254
Test name
Test status
Simulation time 858836782 ps
CPU time 10.36 seconds
Started Oct 01 12:31:06 PM PDT 23
Finished Oct 01 12:31:16 PM PDT 23
Peak memory 211044 kb
Host smart-719ee767-dc0d-420b-9e9e-0d920e0c7a7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611281994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2611281994
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4218552413
Short name T102
Test name
Test status
Simulation time 990053105 ps
CPU time 9.86 seconds
Started Oct 01 12:31:02 PM PDT 23
Finished Oct 01 12:31:12 PM PDT 23
Peak memory 212840 kb
Host smart-6b940e63-e53e-4e53-a313-0a688acaae20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218552413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4218552413
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1791719301
Short name T384
Test name
Test status
Simulation time 4981423872 ps
CPU time 65.55 seconds
Started Oct 01 12:30:45 PM PDT 23
Finished Oct 01 12:31:51 PM PDT 23
Peak memory 219212 kb
Host smart-a0a65c8e-e32f-4d6d-8f17-6c9b9ca56b6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791719301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1791719301
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1961471050
Short name T23
Test name
Test status
Simulation time 151477822724 ps
CPU time 4604.2 seconds
Started Oct 01 12:31:05 PM PDT 23
Finished Oct 01 01:47:50 PM PDT 23
Peak memory 235668 kb
Host smart-6b054427-db69-459a-a9b1-d4a23d667902
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961471050 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1961471050
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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