Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	189076	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1931398

1

T24

613

T25

18

T26

227

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	527778	1			T24	146		T25	2		T26	20
values[0x0]	737498	1			T24	238		T25	8		T26	96
values[0x1]	855198	1			T24	266		T25	10		T26	111

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	84397	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2036077

1

T24

633

T25

18

T26

227

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8698	1			T26	9		T29	3		T30	1
valid_sources[0x01]	7955	1			T24	3		T29	2		T30	1
valid_sources[0x02]	7772	1			T24	4		T29	2		T33	1
valid_sources[0x03]	7971	1			T24	4		T30	4		T33	1
valid_sources[0x04]	7581	1			T24	4		T26	1		T27	1
valid_sources[0x05]	7608	1			T24	3		T26	12		T29	2
valid_sources[0x06]	7456	1			T24	1		T29	2		T30	5
valid_sources[0x07]	8745	1			T24	3		T29	2		T33	4
valid_sources[0x08]	8273	1			T24	2		T27	26		T30	1
valid_sources[0x09]	7433	1			T24	2		T29	5		T30	2
valid_sources[0x0a]	8967	1			T24	2		T30	2		T33	1
valid_sources[0x0b]	8702	1			T24	3		T29	1		T30	2
valid_sources[0x0c]	8287	1			T24	7		T29	1		T30	1
valid_sources[0x0d]	8359	1			T24	3		T29	2		T33	5
valid_sources[0x0e]	7899	1			T24	4		T29	3		T30	2
valid_sources[0x0f]	7646	1			T24	2		T29	3		T30	3
valid_sources[0x10]	8439	1			T24	2		T30	1		T33	2
valid_sources[0x11]	7853	1			T24	3		T26	7		T27	2
valid_sources[0x12]	7952	1			T24	2		T29	1		T33	2
valid_sources[0x13]	7472	1			T24	1		T29	1		T30	1
valid_sources[0x14]	8442	1			T24	2		T29	1		T30	2
valid_sources[0x15]	7914	1			T24	1		T29	2		T30	3
valid_sources[0x16]	7658	1			T26	1		T29	1		T33	2
valid_sources[0x17]	7623	1			T24	3		T29	1		T30	1
valid_sources[0x18]	7246	1			T24	1		T27	1		T30	1
valid_sources[0x19]	8905	1			T24	4		T29	2		T30	3
valid_sources[0x1a]	8038	1			T29	1		T55	1		T57	6
valid_sources[0x1b]	9209	1			T24	2		T29	4		T30	2
valid_sources[0x1c]	9275	1			T24	1		T29	2		T30	1
valid_sources[0x1d]	9002	1			T24	2		T29	4		T30	4
valid_sources[0x1e]	8967	1			T24	2		T30	4		T54	1
valid_sources[0x1f]	8804	1			T24	5		T29	3		T30	1
valid_sources[0x20]	8261	1			T24	4		T29	1		T33	1
valid_sources[0x21]	9547	1			T24	2		T30	1		T33	6
valid_sources[0x22]	8438	1			T24	2		T29	2		T30	3
valid_sources[0x23]	9325	1			T24	1		T29	1		T30	2
valid_sources[0x24]	8481	1			T24	1		T29	1		T33	1
valid_sources[0x25]	7776	1			T24	4		T30	6		T33	2
valid_sources[0x26]	7421	1			T24	1		T29	1		T33	2
valid_sources[0x27]	9224	1			T24	2		T26	10		T30	2
valid_sources[0x28]	8672	1			T24	3		T29	1		T33	2
valid_sources[0x29]	9152	1			T24	3		T29	3		T60	1
valid_sources[0x2a]	7118	1			T24	3		T29	3		T30	1
valid_sources[0x2b]	7376	1			T24	2		T30	1		T33	2
valid_sources[0x2c]	8606	1			T24	2		T27	18		T29	1
valid_sources[0x2d]	8758	1			T24	2		T29	2		T30	2
valid_sources[0x2e]	7760	1			T24	1		T29	2		T30	1
valid_sources[0x2f]	8037	1			T30	3		T33	2		T54	1
valid_sources[0x30]	8576	1			T24	4		T29	2		T30	5
valid_sources[0x31]	9401	1			T24	3		T26	1		T29	2
valid_sources[0x32]	6748	1			T24	4		T29	1		T33	3
valid_sources[0x33]	8606	1			T24	4		T30	1		T33	3
valid_sources[0x34]	8031	1			T24	5		T27	11		T29	2
valid_sources[0x35]	8379	1			T24	3		T26	3		T29	2
valid_sources[0x36]	7988	1			T24	1		T29	1		T33	2
valid_sources[0x37]	8465	1			T24	1		T30	3		T54	1
valid_sources[0x38]	8580	1			T24	2		T29	3		T30	1
valid_sources[0x39]	8030	1			T24	1		T29	4		T30	2
valid_sources[0x3a]	7972	1			T24	4		T26	2		T29	1
valid_sources[0x3b]	8398	1			T24	1		T29	1		T30	2
valid_sources[0x3c]	7296	1			T24	8		T29	1		T30	6
valid_sources[0x3d]	7165	1			T24	2		T29	1		T30	2
valid_sources[0x3e]	7963	1			T24	2		T54	1		T55	1
valid_sources[0x3f]	7582	1			T24	2		T26	1		T29	5
valid_sources[0x40]	8317	1			T24	3		T30	2		T33	1
valid_sources[0x41]	7710	1			T24	2		T30	1		T55	2
valid_sources[0x42]	7260	1			T24	4		T29	1		T33	4
valid_sources[0x43]	8197	1			T24	2		T29	1		T30	1
valid_sources[0x44]	9073	1			T29	2		T30	1		T33	4
valid_sources[0x45]	9170	1			T24	3		T29	1		T30	2
valid_sources[0x46]	9467	1			T24	2		T26	4		T27	11
valid_sources[0x47]	8999	1			T24	3		T29	3		T30	1
valid_sources[0x48]	8688	1			T24	3		T30	1		T33	3
valid_sources[0x49]	7190	1			T24	1		T54	2		T64	1
valid_sources[0x4a]	7911	1			T24	3		T29	1		T30	2
valid_sources[0x4b]	8087	1			T24	5		T29	2		T30	1
valid_sources[0x4c]	8350	1			T24	2		T29	1		T30	2
valid_sources[0x4d]	9402	1			T24	1		T27	24		T29	1
valid_sources[0x4e]	8223	1			T24	3		T29	2		T33	8
valid_sources[0x4f]	7993	1			T29	3		T30	3		T33	5
valid_sources[0x50]	8258	1			T24	3		T29	2		T30	1
valid_sources[0x51]	7626	1			T24	1		T60	3		T54	3
valid_sources[0x52]	7682	1			T24	6		T30	2		T54	1
valid_sources[0x53]	7777	1			T24	4		T29	2		T30	1
valid_sources[0x54]	8259	1			T24	3		T29	1		T30	1
valid_sources[0x55]	8049	1			T24	2		T29	2		T30	1
valid_sources[0x56]	7968	1			T24	1		T33	3		T54	1
valid_sources[0x57]	9163	1			T24	1		T29	2		T30	3
valid_sources[0x58]	8579	1			T24	1		T29	2		T54	1
valid_sources[0x59]	8230	1			T24	5		T26	1		T29	2
valid_sources[0x5a]	7748	1			T24	3		T30	1		T33	4
valid_sources[0x5b]	8519	1			T24	6		T26	1		T30	1
valid_sources[0x5c]	8672	1			T24	2		T29	2		T30	1
valid_sources[0x5d]	6833	1			T24	2		T29	1		T33	2
valid_sources[0x5e]	8438	1			T24	3		T29	1		T30	2
valid_sources[0x5f]	7628	1			T24	2		T29	2		T30	3
valid_sources[0x60]	7105	1			T24	4		T30	2		T54	2
valid_sources[0x61]	7966	1			T24	4		T27	19		T30	1
valid_sources[0x62]	9370	1			T24	1		T29	2		T33	2
valid_sources[0x63]	9214	1			T24	3		T29	2		T30	2
valid_sources[0x64]	9376	1			T24	2		T29	2		T30	1
valid_sources[0x65]	8399	1			T24	3		T29	2		T30	1
valid_sources[0x66]	8240	1			T24	2		T29	3		T30	3
valid_sources[0x67]	8949	1			T24	1		T26	7		T29	2
valid_sources[0x68]	8347	1			T24	6		T26	2		T33	1
valid_sources[0x69]	12012	1			T24	4		T29	3		T30	2
valid_sources[0x6a]	8419	1			T24	3		T26	4		T29	2
valid_sources[0x6b]	7601	1			T24	2		T29	1		T30	1
valid_sources[0x6c]	8400	1			T24	1		T29	2		T33	1
valid_sources[0x6d]	7302	1			T24	1		T29	2		T30	3
valid_sources[0x6e]	8084	1			T24	2		T26	8		T29	2
valid_sources[0x6f]	9615	1			T24	2		T29	2		T30	2
valid_sources[0x70]	7173	1			T24	2		T30	1		T33	4
valid_sources[0x71]	8710	1			T24	5		T29	1		T54	1
valid_sources[0x72]	7379	1			T24	5		T29	4		T30	2
valid_sources[0x73]	7876	1			T24	6		T29	2		T33	1
valid_sources[0x74]	7704	1			T24	4		T29	1		T30	2
valid_sources[0x75]	8897	1			T24	4		T26	11		T29	1
valid_sources[0x76]	7215	1			T29	3		T30	3		T33	1
valid_sources[0x77]	8718	1			T24	2		T29	3		T30	3
valid_sources[0x78]	9514	1			T24	2		T29	2		T30	1
valid_sources[0x79]	8571	1			T29	1		T30	4		T33	3
valid_sources[0x7a]	8804	1			T29	1		T30	1		T33	2
valid_sources[0x7b]	8357	1			T24	3		T26	4		T30	1
valid_sources[0x7c]	8267	1			T24	3		T29	4		T33	3
valid_sources[0x7d]	8586	1			T24	3		T33	1		T54	1
valid_sources[0x7e]	8172	1			T24	3		T29	3		T33	2
valid_sources[0x7f]	7829	1			T24	3		T29	1		T30	4
valid_sources[0x80]	8823	1			T24	3		T29	1		T30	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

486858

1

T24

142

T25

1

T26

20

values[0x0]

all_enables

biggest_size

722454

1

T24

235

T25

8

T26

96

values[0x1]

all_enables

biggest_size

722086

1

T24

236

T25

9

T26

111

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	426852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1877587

1

T24

251

T29

40

T30

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	518887	1			T24	73		T27	6		T29	40
values[0x0]	738938	1			T24	106		T32	5		T33	3
values[0x1]	1046614	1			T24	163		T27	2		T32	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	162061	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2142378

1

T24

303

T27

5

T29

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8866	1			T59	1		T115	4		T126	1
valid_sources[0x01]	9711	1			T30	1		T54	4		T58	1
valid_sources[0x02]	8244	1			T54	2		T57	1		T59	2
valid_sources[0x03]	9437	1			T24	5		T54	3		T57	15
valid_sources[0x04]	7959	1			T24	5		T30	3		T54	2
valid_sources[0x05]	10034	1			T54	1		T57	1		T59	2
valid_sources[0x06]	9294	1			T54	2		T57	11		T61	3
valid_sources[0x07]	10383	1			T54	1		T59	1		T61	2
valid_sources[0x08]	10000	1			T24	1		T54	1		T59	2
valid_sources[0x09]	8333	1			T33	4		T54	2		T57	1
valid_sources[0x0a]	8414	1			T54	4		T68	1		T63	1
valid_sources[0x0b]	7990	1			T54	3		T57	2		T59	1
valid_sources[0x0c]	8268	1			T57	1		T59	1		T61	2
valid_sources[0x0d]	8103	1			T59	1		T61	2		T127	2
valid_sources[0x0e]	8918	1			T54	4		T59	2		T61	2
valid_sources[0x0f]	8265	1			T24	3		T54	4		T57	3
valid_sources[0x10]	9709	1			T59	2		T63	2		T126	1
valid_sources[0x11]	9092	1			T54	4		T59	1		T68	1
valid_sources[0x12]	9140	1			T54	1		T57	4		T59	4
valid_sources[0x13]	8606	1			T24	1		T63	1		T126	1
valid_sources[0x14]	8730	1			T57	1		T77	3		T126	1
valid_sources[0x15]	8850	1			T24	17		T54	3		T57	1
valid_sources[0x16]	8761	1			T57	4		T59	4		T61	1
valid_sources[0x17]	9728	1			T54	1		T57	5		T59	4
valid_sources[0x18]	9135	1			T33	1		T54	1		T57	1
valid_sources[0x19]	8273	1			T57	1		T59	3		T69	2
valid_sources[0x1a]	8943	1			T24	4		T54	1		T57	2
valid_sources[0x1b]	8457	1			T24	5		T54	3		T59	1
valid_sources[0x1c]	8805	1			T30	3		T54	3		T57	3
valid_sources[0x1d]	9539	1			T57	7		T59	5		T61	3
valid_sources[0x1e]	10690	1			T54	2		T57	10		T59	1
valid_sources[0x1f]	10425	1			T57	1		T59	2		T61	3
valid_sources[0x20]	9010	1			T24	2		T30	1		T54	4
valid_sources[0x21]	8409	1			T57	4		T68	1		T63	1
valid_sources[0x22]	9715	1			T24	1		T54	1		T59	1
valid_sources[0x23]	9533	1			T54	2		T57	7		T68	1
valid_sources[0x24]	7833	1			T24	3		T54	1		T57	2
valid_sources[0x25]	10198	1			T54	1		T63	2		T72	1
valid_sources[0x26]	8317	1			T29	2		T54	1		T57	1
valid_sources[0x27]	8165	1			T24	2		T54	4		T61	2
valid_sources[0x28]	10722	1			T24	10		T57	2		T59	1
valid_sources[0x29]	9303	1			T24	6		T54	4		T57	2
valid_sources[0x2a]	9915	1			T54	3		T57	4		T59	3
valid_sources[0x2b]	9621	1			T54	2		T57	8		T59	4
valid_sources[0x2c]	9199	1			T54	2		T57	1		T59	1
valid_sources[0x2d]	8770	1			T54	1		T59	1		T61	1
valid_sources[0x2e]	11512	1			T24	2		T30	2		T54	2
valid_sources[0x2f]	8098	1			T24	1		T54	3		T57	1
valid_sources[0x30]	8503	1			T54	2		T61	2		T63	2
valid_sources[0x31]	8943	1			T54	3		T59	1		T61	3
valid_sources[0x32]	9832	1			T24	11		T54	2		T57	1
valid_sources[0x33]	11158	1			T54	4		T58	1		T59	1
valid_sources[0x34]	8858	1			T54	3		T57	5		T58	2
valid_sources[0x35]	8861	1			T54	2		T59	1		T61	2
valid_sources[0x36]	9295	1			T54	3		T57	3		T59	4
valid_sources[0x37]	8459	1			T29	1		T54	3		T59	3
valid_sources[0x38]	9847	1			T24	1		T57	3		T59	1
valid_sources[0x39]	9039	1			T54	1		T57	5		T59	3
valid_sources[0x3a]	8479	1			T24	2		T30	2		T54	2
valid_sources[0x3b]	8997	1			T24	1		T54	3		T57	2
valid_sources[0x3c]	10203	1			T54	7		T59	2		T61	3
valid_sources[0x3d]	9011	1			T54	1		T61	5		T127	2
valid_sources[0x3e]	8324	1			T54	4		T57	3		T59	1
valid_sources[0x3f]	9809	1			T29	1		T54	2		T78	1
valid_sources[0x40]	9214	1			T54	2		T61	1		T63	1
valid_sources[0x41]	9253	1			T24	11		T33	4		T54	2
valid_sources[0x42]	9398	1			T24	2		T54	6		T57	4
valid_sources[0x43]	7935	1			T29	2		T54	5		T57	5
valid_sources[0x44]	8963	1			T54	4		T57	1		T59	1
valid_sources[0x45]	9017	1			T30	1		T57	2		T59	1
valid_sources[0x46]	9005	1			T24	3		T29	1		T54	1
valid_sources[0x47]	8788	1			T54	1		T57	6		T59	3
valid_sources[0x48]	9130	1			T54	3		T57	9		T59	5
valid_sources[0x49]	8620	1			T54	2		T59	4		T63	3
valid_sources[0x4a]	8619	1			T54	2		T57	4		T59	1
valid_sources[0x4b]	9660	1			T29	6		T54	5		T59	1
valid_sources[0x4c]	8446	1			T57	3		T68	1		T69	3
valid_sources[0x4d]	8799	1			T24	3		T54	3		T57	4
valid_sources[0x4e]	9456	1			T24	7		T32	1		T57	1
valid_sources[0x4f]	8659	1			T30	1		T57	2		T59	2
valid_sources[0x50]	9447	1			T54	2		T59	3		T68	1
valid_sources[0x51]	8687	1			T29	3		T54	4		T59	6
valid_sources[0x52]	8499	1			T57	1		T59	4		T75	1
valid_sources[0x53]	8130	1			T54	1		T57	3		T59	3
valid_sources[0x54]	8630	1			T54	6		T59	2		T126	1
valid_sources[0x55]	8864	1			T54	3		T40	40		T59	1
valid_sources[0x56]	8330	1			T54	3		T57	1		T59	2
valid_sources[0x57]	9486	1			T54	2		T57	4		T59	7
valid_sources[0x58]	9026	1			T54	2		T68	1		T75	1
valid_sources[0x59]	10115	1			T54	1		T59	1		T63	2
valid_sources[0x5a]	8595	1			T54	2		T59	1		T63	2
valid_sources[0x5b]	8503	1			T54	1		T59	1		T61	2
valid_sources[0x5c]	8616	1			T24	3		T54	1		T57	5
valid_sources[0x5d]	9649	1			T24	1		T54	1		T57	2
valid_sources[0x5e]	9454	1			T54	1		T57	5		T59	2
valid_sources[0x5f]	9484	1			T24	1		T29	1		T54	2
valid_sources[0x60]	8819	1			T29	3		T54	2		T57	2
valid_sources[0x61]	8831	1			T24	1		T54	4		T59	1
valid_sources[0x62]	9152	1			T29	2		T54	1		T63	1
valid_sources[0x63]	9253	1			T29	1		T54	4		T59	1
valid_sources[0x64]	9255	1			T54	3		T57	1		T61	1
valid_sources[0x65]	9211	1			T59	2		T61	2		T127	2
valid_sources[0x66]	9690	1			T30	2		T54	1		T58	1
valid_sources[0x67]	9710	1			T54	2		T57	1		T59	1
valid_sources[0x68]	8256	1			T32	1		T57	8		T59	3
valid_sources[0x69]	9150	1			T24	6		T54	2		T57	5
valid_sources[0x6a]	8994	1			T24	7		T54	3		T57	2
valid_sources[0x6b]	9659	1			T54	3		T57	2		T69	1
valid_sources[0x6c]	8267	1			T24	3		T54	6		T57	1
valid_sources[0x6d]	8274	1			T54	4		T59	2		T68	1
valid_sources[0x6e]	9656	1			T24	2		T54	1		T57	3
valid_sources[0x6f]	9472	1			T59	1		T68	2		T61	4
valid_sources[0x70]	8981	1			T54	3		T57	1		T59	1
valid_sources[0x71]	9203	1			T32	1		T54	2		T68	1
valid_sources[0x72]	9510	1			T57	4		T59	1		T61	6
valid_sources[0x73]	9013	1			T59	3		T63	2		T127	1
valid_sources[0x74]	8792	1			T57	1		T59	2		T127	3
valid_sources[0x75]	8290	1			T24	3		T57	1		T59	1
valid_sources[0x76]	9391	1			T54	1		T57	5		T59	2
valid_sources[0x77]	9577	1			T54	1		T59	5		T61	1
valid_sources[0x78]	9428	1			T24	3		T29	1		T54	3
valid_sources[0x79]	8140	1			T24	8		T54	1		T59	3
valid_sources[0x7a]	8706	1			T24	2		T54	3		T59	2
valid_sources[0x7b]	9677	1			T54	3		T59	1		T63	1
valid_sources[0x7c]	8961	1			T24	12		T54	1		T57	1
valid_sources[0x7d]	8632	1			T54	4		T57	1		T59	2
valid_sources[0x7e]	8330	1			T54	1		T59	1		T69	1
valid_sources[0x7f]	9507	1			T54	4		T59	2		T61	4
valid_sources[0x80]	9493	1			T24	7		T59	2		T61	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

472704

1

T24

73

T29

40

T30

40

values[0x0]

all_enables

biggest_size

703152

1

T24

95

T32

5

T54

182

values[0x1]

all_enables

biggest_size

701731

1

T24

83

T32

1

T54

181