Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5232831

1

T24

1420

T27

10

T32

13

full_word

2250938

1

T24

353

T29

40

T30

40

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7483479	1			T24	1773		T29	40		T30	40
auto[TlIntgErrCmd]	85	1			T33	6		T55	1		T58	6
auto[TlIntgErrData]	102	1			T27	3		T33	8		T55	4
auto[TlIntgErrBoth]	103	1			T27	7		T33	6		T55	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

899297

1

T24

139

T27

7

T29

40

auto[1]

6584472

1

T24

1634

T27

3

T32

19

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	381238	1			T24	57		T32	1		T54	30
auto[TlIntgErrNone]	partial	auto[1]	4851328	1			T24	1363		T32	12		T54	361
auto[TlIntgErrNone]	full_word	auto[0]	517931	1			T24	82		T29	40		T30	40
auto[TlIntgErrNone]	full_word	auto[1]	1732982	1			T24	271		T32	7		T54	392
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T33	2		T55	1		T58	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T33	4		T58	3		T76	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T114	1		T116	1		T117	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T58	2		T62	1		T78	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T27	3		T33	3		T55	3
auto[TlIntgErrData]	partial	auto[1]	54	1			T33	5		T55	1		T58	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T58	1		T118	1		T119	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T75	1		T120	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T27	4		T33	3		T55	3
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T27	3		T33	3		T55	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T75	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T76	1		T75	1		T118	1