SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
rom_ctrl_kmac_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 0 | 7 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_kmac_done | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
cp_kmac_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
kmac_first | 609 | 1 | T24 | 1 | T29 | 3 | T30 | 21 | ||||
same_cycle | 18 | 1 | T69 | 1 | T121 | 1 | T88 | 1 | ||||
rom_first | 1473 | 1 | T25 | 1 | T26 | 1 | T27 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
stall_repeat | 93004045 | 1 | T24 | 20836 | T25 | 63776 | T26 | 71474 | ||||
stall_long | 9841672 | 1 | T24 | 2325 | T25 | 6763 | T26 | 7372 | ||||
stall_1 | 802103 | 1 | T24 | 1176 | T25 | 281 | T26 | 186 | ||||
zero_delay_5 | 4297446 | 1 | T24 | 2 | T29 | 4 | T30 | 171780 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |