Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.35	97.11	92.68	97.88	100.00	98.37	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	98.21	92.86		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_rom_top	100.00	100.00				100.00	100.00
u_tl_adapter_rom	93.77	91.56	83.06	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	453	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
117	1	1
122	1	1
123	1	1
124	1	1
125	1	1
128	1	1
222	1	1
268	1	1
323	1	1
425	8	8
426	8	8
428	8	8
429	8	8
431	8	8
432	8	8
436	1	1
438	1	1
441	1	1
442	1	1
443	1	1
444	1	1
449	1	1
453	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       222
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       268
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       436
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T35,T36
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       438
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T4

 LINE       449
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T38,T39

 LINE       453
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T34,T35,T36

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
rst_ni	Yes	Yes	T27,T29,T30	Yes	T24,T25,T26	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T25,T26,T27	Yes	T24,T25,T26	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T24,T27,T29	Yes	T24,T27,T29	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T24,T27,T29	Yes	T24,T27,T29	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T24,T27,T32	Yes	T24,T27,T32	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T24,T27,T29	Yes	T24,T27,T29	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T24,T27,T32	Yes	T24,T27,T32	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T24,T27,T32	Yes	T24,T27,T32	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T24,T27,T29	Yes	T24,T27,T29	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T24,T27,T32	Yes	T24,T27,T32	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T24,T27,T32	Yes	T24,T27,T32	INPUT
rom_tl_i.a_valid	Yes	Yes	T24,T27,T29	Yes	T24,T27,T29	INPUT
rom_tl_o.a_ready	Yes	Yes	T27,T29,T30	Yes	T24,T25,T26	OUTPUT
rom_tl_o.d_error	Yes	Yes	T24,T27,T32	Yes	T24,T27,T32	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T40	Yes	T29,T30,T40	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T24,T27,*T29	Yes	T24,T27,T29	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T24,T29,T30	Yes	T24,T29,T30	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T24,T27,T29	Yes	T24,T27,T29	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T24,T27,T32	Yes	T24,T27,T32	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T24,*T27,*T32	Yes	T24,T27,T32	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T24,T27,T29	Yes	T24,T27,T29	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T25,T26,T27	Yes	T24,T25,T26	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T24,T26,T27	Yes	T24,T26,T27	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T24,T25,T26	Yes	T24,T26,T27	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T24,T26,T29	Yes	T24,T26,T29	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T24,T26,T27	Yes	T24,T25,T26	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
regs_tl_i.a_valid	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
regs_tl_o.a_ready	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
regs_tl_o.d_error	Yes	Yes	T27,T32,T33	Yes	T24,T27,T32	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T24,*T25,*T26	Yes	T24,T25,T26	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T25,T26,T27	Yes	T24,T25,T26	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T24,T27,T29	Yes	T24,T25,T27	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T24,*T26,*T27	Yes	T24,T25,T26	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T24,T25,T26	Yes	T29,T30,T40	OUTPUT
keymgr_data_o.valid	Yes	Yes	T29,T30,T40	Yes	T24,T25,T26	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T29,T30,T40	Yes	T26,T29,T30	OUTPUT
kmac_data_i.error	No	Yes	T4,T9,T22	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T29,T30,T40	Yes	T29,T30,T40	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T29,T30,T40	Yes	T29,T30,T40	INPUT
kmac_data_i.done	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
kmac_data_i.ready	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
kmac_data_o.last	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	222	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	222	(tl_rom_h2d_upstream.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	253493292	253313682	0	0
BusRomIndicesMatch_A	253470732	253299061	0	0
FpvSecCmFifoRptrCheck_A	253493292	0	0	0
FpvSecCmFifoWptrCheck_A	253493292	0	0	0
FpvSecCmRegWeOnehotCheck_A	253493292	60	0	0
KeymgrDataODataKnown_A	253493292	94301081	0	0
KeymgrDataODataKnown_AKnownEnable	253493292	253313682	0	0
KeymgrDataOValidKnown_A	253493292	253313682	0	0
KeymgrValidChk_A	253493292	0	0	341
KmacDataODataKnown_A	253493292	158868969	0	0
KmacDataODataKnown_AKnownEnable	253493292	253313682	0	0
KmacDataOValidKnown_A	253493292	253313682	0	0
PwrmgrDataChk_A	253493292	0	0	341
PwrmgrDataOKnown_A	253493292	253313682	0	0
RegsTlOAReadyKnown_A	253493292	253313682	0	0
RegsTlODDataKnown_A	253493292	12089446	0	0
RegsTlODDataKnown_AKnownEnable	253493292	253313682	0	0
RegsTlODValidKnown_A	253493292	253313682	0	0
RomTlOAReadyKnown_A	253493292	253313682	0	0
RomTlODDataKnown_A	253493292	18107262	0	0
RomTlODDataKnown_AKnownEnable	253493292	253313682	0	0
RomTlODValidKnown_A	253493292	253313682	0	0
StabilityChkKmac_A	253493292	158866338	0	0
StabilityChkkeymgr_A	253493292	94299761	0	0
TlAccessChk_A	253493292	159012601	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	253493292	60	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	253493292	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	253493292	543	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	253493292	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253470732	253299061	0	0
T1	179906	179295	0	0
T2	158109	156225	0	0
T3	237119	234384	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263609	260333	0	0
T9	204820	204676	0	0
T10	263325	263130	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	60	0	0
T34	14158	10	0	0
T35	17882	10	0	0
T36	144340	20	0	0
T39	146385	0	0	0
T41	0	10	0	0
T42	0	10	0	0
T43	86094	0	0	0
T44	297136	0	0	0
T45	41584	0	0	0
T46	49561	0	0	0
T47	272052	0	0	0
T48	183643	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	94301081	0	0
T1	179906	6654	0	0
T2	158765	7305	0	0
T3	237350	22731	0	0
T4	16635	51	0	0
T5	963535	6619	0	0
T6	323614	243457	0	0
T7	262791	1266	0	0
T8	263872	27163	0	0
T9	204820	64	0	0
T10	263353	5331	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	0	0	341

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	158868969	0	0
T1	179906	172241	0	0
T2	158765	148171	0	0
T3	237350	205952	0	0
T4	16635	16368	0	0
T5	963535	956178	0	0
T6	323614	800845	0	0
T7	262791	261225	0	0
T8	263872	230634	0	0
T9	204820	204434	0	0
T10	263353	262454	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	0	0	341

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	12089446	0	0
T1	179906	128	0	0
T2	158765	22	0	0
T3	237350	33	0	0
T4	16635	2	0	0
T5	963535	128	0	0
T6	323614	211676	0	0
T7	262791	32	0	0
T8	263872	40	0	0
T9	204820	1	0	0
T10	263353	74	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	18107262	0	0
T1	179906	300	0	0
T2	158765	18	0	0
T3	237350	6	0	0
T4	16635	0	0	0
T5	963535	938	0	0
T6	323614	259371	0	0
T7	262791	86	0	0
T8	263872	9	0	0
T9	204820	0	0	0
T10	263353	28	0	0
T11	0	501459	0	0
T15	0	507	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	253313682	0	0
T1	179906	179295	0	0
T2	158765	156484	0	0
T3	237350	234504	0	0
T4	16635	16476	0	0
T5	963535	963102	0	0
T6	323614	323569	0	0
T7	262791	262639	0	0
T8	263872	260401	0	0
T9	204820	204676	0	0
T10	263353	263143	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	158866338	0	0
T1	179906	172233	0	0
T2	158765	148141	0	0
T3	237350	205914	0	0
T4	16635	16366	0	0
T5	963535	956172	0	0
T6	323614	800834	0	0
T7	262791	261223	0	0
T8	263872	230587	0	0
T9	204820	204432	0	0
T10	263353	262451	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	94299761	0	0
T1	179906	6647	0	0
T2	158765	7291	0	0
T3	237350	22715	0	0
T4	16635	50	0	0
T5	963535	6614	0	0
T6	323614	243457	0	0
T7	262791	1264	0	0
T8	263872	27145	0	0
T9	204820	63	0	0
T10	263353	5320	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	159012601	0	0
T1	179906	172641	0	0
T2	158765	149179	0	0
T3	237350	211773	0	0
T4	16635	16425	0	0
T5	963535	956483	0	0
T6	323614	801117	0	0
T7	262791	261373	0	0
T8	263872	233238	0	0
T9	204820	204612	0	0
T10	263353	262609	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	60	0	0
T34	14158	10	0	0
T35	17882	10	0	0
T36	144340	20	0	0
T39	146385	0	0	0
T41	0	10	0	0
T42	0	10	0	0
T43	86094	0	0	0
T44	297136	0	0	0
T45	41584	0	0	0
T46	49561	0	0	0
T47	272052	0	0	0
T48	183643	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	543	0	0
T2	158765	5	0	0
T3	237350	10	0	0
T4	16635	0	0	0
T5	963535	0	0	0
T6	323614	0	0	0
T7	262791	0	0	0
T8	263872	15	0	0
T9	204820	0	0	0
T10	263353	15	0	0
T21	0	10	0	0
T22	41388	0	0	0
T49	0	5	0	0
T50	0	15	0	0
T51	0	15	0	0
T52	0	11	0	0
T53	0	20	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253493292	0	0	0