Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
253493292 |
253313682 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
253493292 |
253313682 |
0 |
0 |
T1 |
179906 |
179295 |
0 |
0 |
T2 |
158765 |
156484 |
0 |
0 |
T3 |
237350 |
234504 |
0 |
0 |
T4 |
16635 |
16476 |
0 |
0 |
T5 |
963535 |
963102 |
0 |
0 |
T6 |
323614 |
323569 |
0 |
0 |
T7 |
262791 |
262639 |
0 |
0 |
T8 |
263872 |
260401 |
0 |
0 |
T9 |
204820 |
204676 |
0 |
0 |
T10 |
263353 |
263143 |
0 |
0 |