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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 97.11 93.12 97.88 100.00 98.69 97.89 99.30


Total test records in report: 481
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T269 /workspace/coverage/default/37.rom_ctrl_stress_all.9305237 Oct 08 03:44:26 PM PDT 23 Oct 08 03:44:47 PM PDT 23 1425513602 ps
T270 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2955298419 Oct 08 03:48:44 PM PDT 23 Oct 08 03:49:21 PM PDT 23 17079239870 ps
T271 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1366123444 Oct 08 03:43:52 PM PDT 23 Oct 08 03:51:48 PM PDT 23 220673035245 ps
T272 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2184327562 Oct 08 03:53:40 PM PDT 23 Oct 08 03:56:38 PM PDT 23 22703900979 ps
T273 /workspace/coverage/default/30.rom_ctrl_alert_test.395504646 Oct 08 03:52:57 PM PDT 23 Oct 08 03:53:02 PM PDT 23 1380100001 ps
T42 /workspace/coverage/default/1.rom_ctrl_sec_cm.2922705107 Oct 08 03:43:58 PM PDT 23 Oct 08 03:44:58 PM PDT 23 4936945156 ps
T274 /workspace/coverage/default/41.rom_ctrl_alert_test.602853031 Oct 08 03:49:20 PM PDT 23 Oct 08 03:49:31 PM PDT 23 1133007769 ps
T275 /workspace/coverage/default/48.rom_ctrl_stress_all.2939522404 Oct 08 03:55:51 PM PDT 23 Oct 08 03:56:04 PM PDT 23 663527108 ps
T276 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3670086992 Oct 08 03:52:41 PM PDT 23 Oct 08 03:58:02 PM PDT 23 33789061587 ps
T277 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.4149666788 Oct 08 03:47:50 PM PDT 23 Oct 08 04:22:06 PM PDT 23 28730567358 ps
T278 /workspace/coverage/default/1.rom_ctrl_smoke.4050451630 Oct 08 03:42:45 PM PDT 23 Oct 08 03:43:22 PM PDT 23 3002719630 ps
T279 /workspace/coverage/default/38.rom_ctrl_smoke.3922661426 Oct 08 03:52:27 PM PDT 23 Oct 08 03:52:54 PM PDT 23 5666644196 ps
T280 /workspace/coverage/default/12.rom_ctrl_alert_test.4165207463 Oct 08 03:53:26 PM PDT 23 Oct 08 03:53:37 PM PDT 23 1062609908 ps
T281 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.906436702 Oct 08 03:49:51 PM PDT 23 Oct 08 03:53:37 PM PDT 23 78710029740 ps
T282 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2196821375 Oct 08 03:49:18 PM PDT 23 Oct 08 03:53:51 PM PDT 23 47407784300 ps
T283 /workspace/coverage/default/21.rom_ctrl_smoke.2494999445 Oct 08 03:45:28 PM PDT 23 Oct 08 03:46:05 PM PDT 23 28518780163 ps
T284 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.240964207 Oct 08 03:54:54 PM PDT 23 Oct 08 03:55:09 PM PDT 23 1819103544 ps
T285 /workspace/coverage/default/13.rom_ctrl_alert_test.1284407076 Oct 08 03:50:19 PM PDT 23 Oct 08 03:50:26 PM PDT 23 409811955 ps
T286 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2143437386 Oct 08 03:50:26 PM PDT 23 Oct 08 03:55:18 PM PDT 23 114946417890 ps
T287 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1080553591 Oct 08 03:55:33 PM PDT 23 Oct 08 03:56:00 PM PDT 23 2880379029 ps
T288 /workspace/coverage/default/24.rom_ctrl_stress_all.3694913848 Oct 08 03:54:50 PM PDT 23 Oct 08 03:55:00 PM PDT 23 264327040 ps
T289 /workspace/coverage/default/2.rom_ctrl_smoke.749224789 Oct 08 03:44:43 PM PDT 23 Oct 08 03:44:58 PM PDT 23 424974142 ps
T290 /workspace/coverage/default/34.rom_ctrl_smoke.1724953730 Oct 08 03:53:33 PM PDT 23 Oct 08 03:54:03 PM PDT 23 12184084313 ps
T291 /workspace/coverage/default/22.rom_ctrl_smoke.1796059840 Oct 08 03:43:59 PM PDT 23 Oct 08 03:44:10 PM PDT 23 782100033 ps
T292 /workspace/coverage/default/41.rom_ctrl_smoke.3826895528 Oct 08 03:47:08 PM PDT 23 Oct 08 03:47:46 PM PDT 23 17150711364 ps
T293 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2716986354 Oct 08 03:43:57 PM PDT 23 Oct 08 05:01:37 PM PDT 23 69897036070 ps
T294 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1922819171 Oct 08 03:51:54 PM PDT 23 Oct 08 03:59:05 PM PDT 23 43691701768 ps
T295 /workspace/coverage/default/32.rom_ctrl_smoke.1096260549 Oct 08 03:46:18 PM PDT 23 Oct 08 03:46:29 PM PDT 23 190624997 ps
T296 /workspace/coverage/default/5.rom_ctrl_stress_all.4009826670 Oct 08 03:52:56 PM PDT 23 Oct 08 03:53:05 PM PDT 23 119173105 ps
T297 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1181864602 Oct 08 03:50:11 PM PDT 23 Oct 08 03:50:17 PM PDT 23 197523363 ps
T298 /workspace/coverage/default/10.rom_ctrl_stress_all.694434456 Oct 08 03:46:43 PM PDT 23 Oct 08 03:47:26 PM PDT 23 4131854070 ps
T299 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3483622764 Oct 08 03:47:02 PM PDT 23 Oct 08 03:47:19 PM PDT 23 3261260443 ps
T105 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.646072047 Oct 08 03:45:31 PM PDT 23 Oct 08 04:15:09 PM PDT 23 47310505432 ps
T300 /workspace/coverage/default/45.rom_ctrl_smoke.587793903 Oct 08 03:46:06 PM PDT 23 Oct 08 03:46:36 PM PDT 23 6604577161 ps
T13 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2579180994 Oct 08 03:47:01 PM PDT 23 Oct 08 03:47:11 PM PDT 23 504757283 ps
T301 /workspace/coverage/default/36.rom_ctrl_alert_test.3016995708 Oct 08 03:52:57 PM PDT 23 Oct 08 03:53:09 PM PDT 23 1174655246 ps
T302 /workspace/coverage/default/27.rom_ctrl_alert_test.3360317843 Oct 08 03:47:38 PM PDT 23 Oct 08 03:47:43 PM PDT 23 827628224 ps
T303 /workspace/coverage/default/19.rom_ctrl_stress_all.3441962824 Oct 08 03:46:13 PM PDT 23 Oct 08 03:47:20 PM PDT 23 6412332114 ps
T304 /workspace/coverage/default/33.rom_ctrl_stress_all.1145326615 Oct 08 03:49:29 PM PDT 23 Oct 08 03:49:47 PM PDT 23 1450728980 ps
T305 /workspace/coverage/default/31.rom_ctrl_alert_test.1327614382 Oct 08 03:53:03 PM PDT 23 Oct 08 03:53:16 PM PDT 23 7263105109 ps
T306 /workspace/coverage/default/20.rom_ctrl_smoke.3289747444 Oct 08 03:48:44 PM PDT 23 Oct 08 03:49:13 PM PDT 23 9784046583 ps
T307 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3910777487 Oct 08 03:47:08 PM PDT 23 Oct 08 03:47:26 PM PDT 23 1236235364 ps
T308 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.294247023 Oct 08 03:44:00 PM PDT 23 Oct 08 03:44:10 PM PDT 23 438071238 ps
T309 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4156440791 Oct 08 03:52:58 PM PDT 23 Oct 08 05:48:01 PM PDT 23 54979018839 ps
T310 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.126125723 Oct 08 03:50:29 PM PDT 23 Oct 08 03:50:41 PM PDT 23 1110972120 ps
T311 /workspace/coverage/default/30.rom_ctrl_stress_all.680729186 Oct 08 03:47:30 PM PDT 23 Oct 08 03:47:43 PM PDT 23 619597051 ps
T312 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1649127690 Oct 08 03:50:22 PM PDT 23 Oct 08 03:50:30 PM PDT 23 1918406742 ps
T51 /workspace/coverage/default/4.rom_ctrl_sec_cm.2610553725 Oct 08 03:46:35 PM PDT 23 Oct 08 03:48:27 PM PDT 23 342023038 ps
T313 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2886498798 Oct 08 03:54:45 PM PDT 23 Oct 08 03:54:59 PM PDT 23 2197056095 ps
T314 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3933064560 Oct 08 03:43:22 PM PDT 23 Oct 08 03:49:14 PM PDT 23 34438663301 ps
T315 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2238581562 Oct 08 03:49:04 PM PDT 23 Oct 08 03:52:49 PM PDT 23 34884143489 ps
T316 /workspace/coverage/default/13.rom_ctrl_smoke.2300295554 Oct 08 03:48:24 PM PDT 23 Oct 08 03:48:35 PM PDT 23 760060859 ps
T317 /workspace/coverage/default/18.rom_ctrl_alert_test.2465692925 Oct 08 03:43:24 PM PDT 23 Oct 08 03:43:40 PM PDT 23 4097742822 ps
T318 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2900096287 Oct 08 03:44:13 PM PDT 23 Oct 08 03:44:20 PM PDT 23 1543570238 ps
T319 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1576888300 Oct 08 03:51:42 PM PDT 23 Oct 08 03:51:48 PM PDT 23 102241141 ps
T320 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.952553837 Oct 08 03:42:59 PM PDT 23 Oct 08 03:43:10 PM PDT 23 6345730079 ps
T321 /workspace/coverage/default/25.rom_ctrl_alert_test.1572947912 Oct 08 03:43:54 PM PDT 23 Oct 08 03:44:06 PM PDT 23 1183835162 ps
T322 /workspace/coverage/default/19.rom_ctrl_smoke.393870723 Oct 08 03:48:50 PM PDT 23 Oct 08 03:49:00 PM PDT 23 904209949 ps
T323 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3744527666 Oct 08 03:44:58 PM PDT 23 Oct 08 04:02:38 PM PDT 23 44963380732 ps
T324 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1827972065 Oct 08 03:49:02 PM PDT 23 Oct 08 03:49:12 PM PDT 23 173941209 ps
T325 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.124000253 Oct 08 03:47:51 PM PDT 23 Oct 08 03:56:05 PM PDT 23 184069523345 ps
T326 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.670777771 Oct 08 03:54:04 PM PDT 23 Oct 08 03:54:14 PM PDT 23 538765078 ps
T327 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2320127890 Oct 08 03:47:57 PM PDT 23 Oct 08 03:50:01 PM PDT 23 3442070124 ps
T328 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3982441951 Oct 08 03:47:42 PM PDT 23 Oct 08 03:48:06 PM PDT 23 8611953160 ps
T329 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1963192633 Oct 08 03:43:52 PM PDT 23 Oct 08 03:43:57 PM PDT 23 817855436 ps
T330 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2184319212 Oct 08 03:56:14 PM PDT 23 Oct 08 03:56:26 PM PDT 23 2099331107 ps
T331 /workspace/coverage/default/42.rom_ctrl_smoke.2520922497 Oct 08 03:45:43 PM PDT 23 Oct 08 03:46:10 PM PDT 23 3967934357 ps
T332 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.250709082 Oct 08 03:45:28 PM PDT 23 Oct 08 03:45:35 PM PDT 23 544979248 ps
T333 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3066736157 Oct 08 03:50:44 PM PDT 23 Oct 08 04:15:27 PM PDT 23 41206205737 ps
T334 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.968304747 Oct 08 03:51:26 PM PDT 23 Oct 08 03:51:40 PM PDT 23 3283966485 ps
T335 /workspace/coverage/default/22.rom_ctrl_stress_all.683097175 Oct 08 03:53:00 PM PDT 23 Oct 08 03:53:22 PM PDT 23 6977376773 ps
T336 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.23807740 Oct 08 03:51:36 PM PDT 23 Oct 08 03:54:04 PM PDT 23 30580689732 ps
T337 /workspace/coverage/default/37.rom_ctrl_alert_test.1582185384 Oct 08 03:52:58 PM PDT 23 Oct 08 03:53:08 PM PDT 23 1617174076 ps
T338 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3810939929 Oct 08 03:45:50 PM PDT 23 Oct 08 03:46:18 PM PDT 23 12353456103 ps
T339 /workspace/coverage/default/46.rom_ctrl_stress_all.2489243185 Oct 08 03:55:40 PM PDT 23 Oct 08 03:55:59 PM PDT 23 1515607554 ps
T340 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2496459093 Oct 08 03:49:20 PM PDT 23 Oct 08 04:08:22 PM PDT 23 141634233265 ps
T341 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3701519726 Oct 08 03:45:31 PM PDT 23 Oct 08 03:45:45 PM PDT 23 1558864891 ps
T342 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2601624902 Oct 08 03:55:16 PM PDT 23 Oct 08 06:53:28 PM PDT 23 47232596263 ps
T343 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3534490267 Oct 08 03:54:53 PM PDT 23 Oct 08 03:58:16 PM PDT 23 67893488173 ps
T344 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.81219101 Oct 08 03:50:28 PM PDT 23 Oct 08 03:50:34 PM PDT 23 192808601 ps
T345 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2917812305 Oct 08 03:45:12 PM PDT 23 Oct 08 03:45:42 PM PDT 23 13266027740 ps
T346 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3878019865 Oct 08 03:42:46 PM PDT 23 Oct 08 03:48:57 PM PDT 23 218441031297 ps
T347 /workspace/coverage/default/40.rom_ctrl_alert_test.3992601131 Oct 08 03:45:32 PM PDT 23 Oct 08 03:45:45 PM PDT 23 1492104767 ps
T348 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3377968263 Oct 08 03:53:20 PM PDT 23 Oct 08 03:53:44 PM PDT 23 9550911488 ps
T349 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3176195770 Oct 08 03:45:31 PM PDT 23 Oct 08 03:45:41 PM PDT 23 692333416 ps
T350 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2714709837 Oct 08 03:54:04 PM PDT 23 Oct 08 03:54:35 PM PDT 23 7347079378 ps
T351 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3201912426 Oct 08 03:44:29 PM PDT 23 Oct 08 05:08:45 PM PDT 23 53689943878 ps
T352 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3299289332 Oct 08 03:46:00 PM PDT 23 Oct 08 03:55:15 PM PDT 23 56149873467 ps
T353 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3839719867 Oct 08 03:44:06 PM PDT 23 Oct 08 03:44:16 PM PDT 23 175455490 ps
T354 /workspace/coverage/default/21.rom_ctrl_alert_test.4226291903 Oct 08 03:54:32 PM PDT 23 Oct 08 03:54:36 PM PDT 23 346767055 ps
T355 /workspace/coverage/default/25.rom_ctrl_smoke.2660246903 Oct 08 03:43:53 PM PDT 23 Oct 08 03:44:09 PM PDT 23 3149951764 ps
T356 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1167796057 Oct 08 03:42:57 PM PDT 23 Oct 08 03:43:21 PM PDT 23 7855414393 ps
T357 /workspace/coverage/default/14.rom_ctrl_stress_all.53998544 Oct 08 03:44:03 PM PDT 23 Oct 08 03:45:56 PM PDT 23 10640932962 ps
T358 /workspace/coverage/default/9.rom_ctrl_smoke.1199948336 Oct 08 03:44:01 PM PDT 23 Oct 08 03:44:12 PM PDT 23 193903742 ps
T359 /workspace/coverage/default/17.rom_ctrl_stress_all.302148682 Oct 08 03:46:33 PM PDT 23 Oct 08 03:47:14 PM PDT 23 9427880031 ps
T360 /workspace/coverage/default/33.rom_ctrl_alert_test.3854198916 Oct 08 03:47:21 PM PDT 23 Oct 08 03:47:28 PM PDT 23 4085043467 ps
T361 /workspace/coverage/default/16.rom_ctrl_stress_all.1386893123 Oct 08 03:43:36 PM PDT 23 Oct 08 03:44:15 PM PDT 23 17606139879 ps
T362 /workspace/coverage/default/49.rom_ctrl_alert_test.10804815 Oct 08 03:44:38 PM PDT 23 Oct 08 03:44:53 PM PDT 23 1839376120 ps
T363 /workspace/coverage/default/40.rom_ctrl_stress_all.2691492911 Oct 08 03:46:28 PM PDT 23 Oct 08 03:46:37 PM PDT 23 107812263 ps
T364 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.541628331 Oct 08 03:43:54 PM PDT 23 Oct 08 03:49:14 PM PDT 23 113807838694 ps
T365 /workspace/coverage/default/24.rom_ctrl_alert_test.2459229984 Oct 08 03:44:57 PM PDT 23 Oct 08 03:45:13 PM PDT 23 7901604698 ps
T366 /workspace/coverage/default/8.rom_ctrl_alert_test.2391844003 Oct 08 03:46:43 PM PDT 23 Oct 08 03:46:52 PM PDT 23 2974366781 ps
T367 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4252089031 Oct 08 03:53:28 PM PDT 23 Oct 08 03:53:52 PM PDT 23 9901585239 ps
T368 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1988039912 Oct 08 03:44:25 PM PDT 23 Oct 08 03:44:31 PM PDT 23 376785612 ps
T369 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3304437970 Oct 08 03:47:16 PM PDT 23 Oct 08 04:24:44 PM PDT 23 34926992803 ps
T370 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.735141065 Oct 08 03:54:32 PM PDT 23 Oct 08 03:54:49 PM PDT 23 2003497458 ps
T371 /workspace/coverage/default/18.rom_ctrl_smoke.4217889633 Oct 08 03:45:31 PM PDT 23 Oct 08 03:46:05 PM PDT 23 6466840289 ps
T372 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1892182990 Oct 08 03:47:39 PM PDT 23 Oct 08 03:48:05 PM PDT 23 2540360557 ps
T373 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.502895339 Oct 08 03:46:48 PM PDT 23 Oct 08 03:47:01 PM PDT 23 895945069 ps
T374 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2820595878 Oct 08 03:46:01 PM PDT 23 Oct 08 04:16:36 PM PDT 23 31449981455 ps
T375 /workspace/coverage/default/11.rom_ctrl_stress_all.581371001 Oct 08 03:56:00 PM PDT 23 Oct 08 03:56:37 PM PDT 23 4129979438 ps
T376 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2733761313 Oct 08 03:44:23 PM PDT 23 Oct 08 03:44:35 PM PDT 23 2431626468 ps
T377 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1894716144 Oct 08 03:52:20 PM PDT 23 Oct 08 03:58:52 PM PDT 23 36921228074 ps
T378 /workspace/coverage/default/17.rom_ctrl_alert_test.632561637 Oct 08 03:56:18 PM PDT 23 Oct 08 03:56:29 PM PDT 23 1118418601 ps
T379 /workspace/coverage/default/23.rom_ctrl_stress_all.3269576333 Oct 08 03:43:55 PM PDT 23 Oct 08 03:44:21 PM PDT 23 2484589553 ps
T380 /workspace/coverage/default/39.rom_ctrl_stress_all.1463888876 Oct 08 03:51:53 PM PDT 23 Oct 08 03:52:11 PM PDT 23 3197157770 ps
T381 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1280385114 Oct 08 03:44:24 PM PDT 23 Oct 08 03:44:30 PM PDT 23 346083719 ps
T382 /workspace/coverage/default/23.rom_ctrl_smoke.513473087 Oct 08 03:44:53 PM PDT 23 Oct 08 03:45:36 PM PDT 23 5155759971 ps
T383 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.798343647 Oct 08 03:44:22 PM PDT 23 Oct 08 03:44:28 PM PDT 23 99411074 ps
T384 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2387439227 Oct 08 03:44:57 PM PDT 23 Oct 08 03:53:07 PM PDT 23 90932762775 ps
T385 /workspace/coverage/default/43.rom_ctrl_alert_test.1421570069 Oct 08 03:50:26 PM PDT 23 Oct 08 03:50:37 PM PDT 23 991016143 ps
T386 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3015547008 Oct 08 03:44:53 PM PDT 23 Oct 08 03:45:25 PM PDT 23 11740999850 ps
T387 /workspace/coverage/default/0.rom_ctrl_stress_all.2708209130 Oct 08 03:45:16 PM PDT 23 Oct 08 03:45:39 PM PDT 23 902870879 ps
T388 /workspace/coverage/default/40.rom_ctrl_smoke.1149237959 Oct 08 03:47:52 PM PDT 23 Oct 08 03:48:20 PM PDT 23 5379587806 ps
T389 /workspace/coverage/default/11.rom_ctrl_alert_test.458663662 Oct 08 03:54:17 PM PDT 23 Oct 08 03:54:32 PM PDT 23 6655189045 ps
T390 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4111909400 Oct 08 03:49:54 PM PDT 23 Oct 08 03:50:26 PM PDT 23 13927613847 ps
T391 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3182392806 Oct 08 03:44:34 PM PDT 23 Oct 08 03:44:44 PM PDT 23 341739092 ps
T392 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3649844223 Oct 08 03:46:13 PM PDT 23 Oct 08 03:48:51 PM PDT 23 4750108231 ps
T393 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2177240389 Oct 08 03:43:59 PM PDT 23 Oct 08 03:44:14 PM PDT 23 6245794441 ps
T394 /workspace/coverage/default/28.rom_ctrl_smoke.1102298346 Oct 08 03:45:42 PM PDT 23 Oct 08 03:46:07 PM PDT 23 2730251831 ps
T395 /workspace/coverage/default/46.rom_ctrl_alert_test.839353943 Oct 08 03:45:43 PM PDT 23 Oct 08 03:45:58 PM PDT 23 1675912556 ps
T396 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2111387031 Oct 08 03:51:09 PM PDT 23 Oct 08 03:58:09 PM PDT 23 64252977765 ps
T397 /workspace/coverage/default/36.rom_ctrl_smoke.1950062766 Oct 08 03:54:21 PM PDT 23 Oct 08 03:54:41 PM PDT 23 4591760154 ps
T398 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3847456077 Oct 08 03:51:18 PM PDT 23 Oct 08 03:51:46 PM PDT 23 13117414076 ps
T399 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.214749233 Oct 08 03:44:03 PM PDT 23 Oct 08 03:44:33 PM PDT 23 24137470888 ps
T400 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.4199296042 Oct 08 03:46:46 PM PDT 23 Oct 08 04:02:29 PM PDT 23 25164354391 ps
T401 /workspace/coverage/default/5.rom_ctrl_alert_test.1743831342 Oct 08 03:49:56 PM PDT 23 Oct 08 03:50:12 PM PDT 23 8653373110 ps
T402 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.455312454 Oct 08 03:54:04 PM PDT 23 Oct 08 03:58:36 PM PDT 23 72537823529 ps
T403 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2501969784 Oct 08 03:48:50 PM PDT 23 Oct 08 04:07:28 PM PDT 23 70707973350 ps
T404 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2949109380 Oct 08 03:45:18 PM PDT 23 Oct 08 03:45:35 PM PDT 23 9611996756 ps
T405 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3890314 Oct 08 03:45:10 PM PDT 23 Oct 08 03:45:22 PM PDT 23 995056158 ps
T406 /workspace/coverage/default/49.rom_ctrl_smoke.224640903 Oct 08 03:55:58 PM PDT 23 Oct 08 03:56:34 PM PDT 23 17147045567 ps
T407 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3971035952 Oct 08 03:54:17 PM PDT 23 Oct 08 03:54:29 PM PDT 23 255373526 ps
T28 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.151599897 Oct 08 03:45:41 PM PDT 23 Oct 08 06:20:09 PM PDT 23 30136692829 ps
T408 /workspace/coverage/default/18.rom_ctrl_stress_all.1036431814 Oct 08 03:46:35 PM PDT 23 Oct 08 03:47:31 PM PDT 23 5704228700 ps
T409 /workspace/coverage/default/39.rom_ctrl_alert_test.904763193 Oct 08 03:55:25 PM PDT 23 Oct 08 03:55:33 PM PDT 23 1550777859 ps
T410 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1069824428 Oct 08 03:44:10 PM PDT 23 Oct 08 03:44:26 PM PDT 23 1897713429 ps
T411 /workspace/coverage/default/47.rom_ctrl_stress_all.1046192900 Oct 08 03:54:58 PM PDT 23 Oct 08 03:56:12 PM PDT 23 6893680032 ps
T412 /workspace/coverage/default/26.rom_ctrl_alert_test.3461686893 Oct 08 03:54:51 PM PDT 23 Oct 08 03:55:05 PM PDT 23 6002324210 ps
T413 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1167953611 Oct 08 03:54:17 PM PDT 23 Oct 08 03:56:05 PM PDT 23 14138661557 ps
T414 /workspace/coverage/default/30.rom_ctrl_smoke.2579726346 Oct 08 03:47:46 PM PDT 23 Oct 08 03:47:56 PM PDT 23 186239678 ps
T415 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1870334243 Oct 08 03:44:45 PM PDT 23 Oct 08 03:44:51 PM PDT 23 466875385 ps
T416 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1867952399 Oct 08 03:53:59 PM PDT 23 Oct 08 03:54:09 PM PDT 23 2188640567 ps
T417 /workspace/coverage/default/43.rom_ctrl_smoke.3233536629 Oct 08 03:45:34 PM PDT 23 Oct 08 03:46:05 PM PDT 23 26905562178 ps
T52 /workspace/coverage/default/0.rom_ctrl_sec_cm.1423576334 Oct 08 03:44:38 PM PDT 23 Oct 08 03:46:36 PM PDT 23 10095464501 ps
T418 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3915378533 Oct 08 03:48:29 PM PDT 23 Oct 08 03:57:35 PM PDT 23 327649616573 ps
T419 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1987998664 Oct 08 03:53:34 PM PDT 23 Oct 08 03:53:49 PM PDT 23 5951968646 ps
T420 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1496054343 Oct 08 03:44:05 PM PDT 23 Oct 08 03:50:54 PM PDT 23 37214844792 ps
T421 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1849047309 Oct 08 03:43:40 PM PDT 23 Oct 08 03:43:50 PM PDT 23 173933538 ps
T422 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1418585414 Oct 08 03:44:56 PM PDT 23 Oct 08 03:45:20 PM PDT 23 2212313599 ps
T423 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1419563291 Oct 08 03:48:03 PM PDT 23 Oct 08 03:48:34 PM PDT 23 7872081607 ps
T424 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1276144967 Oct 08 03:48:06 PM PDT 23 Oct 08 03:53:39 PM PDT 23 64909359176 ps
T425 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2882823253 Oct 08 03:53:40 PM PDT 23 Oct 08 03:53:51 PM PDT 23 356175369 ps
T426 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2145367823 Oct 08 03:45:13 PM PDT 23 Oct 08 03:52:16 PM PDT 23 41797539510 ps
T427 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2733147438 Oct 08 03:47:01 PM PDT 23 Oct 08 04:40:14 PM PDT 23 80229074966 ps
T428 /workspace/coverage/default/49.rom_ctrl_stress_all.3111683498 Oct 08 03:54:56 PM PDT 23 Oct 08 03:55:48 PM PDT 23 23435741087 ps
T429 /workspace/coverage/default/29.rom_ctrl_stress_all.2880120934 Oct 08 03:48:27 PM PDT 23 Oct 08 03:49:08 PM PDT 23 16195394092 ps
T430 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3642245889 Oct 08 03:43:36 PM PDT 23 Oct 08 05:38:13 PM PDT 23 43556819811 ps
T431 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1224633246 Oct 08 03:47:47 PM PDT 23 Oct 08 03:50:15 PM PDT 23 13063269603 ps
T432 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3978154470 Oct 08 02:01:51 PM PDT 23 Oct 08 02:02:04 PM PDT 23 475934964 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3509677160 Oct 08 02:02:38 PM PDT 23 Oct 08 02:02:45 PM PDT 23 383432182 ps
T434 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.722465407 Oct 08 01:59:17 PM PDT 23 Oct 08 01:59:30 PM PDT 23 6675333790 ps
T435 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3584104217 Oct 08 02:08:41 PM PDT 23 Oct 08 02:08:57 PM PDT 23 3223456537 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1872044049 Oct 08 01:56:43 PM PDT 23 Oct 08 01:56:55 PM PDT 23 4598278612 ps
T110 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4214290982 Oct 08 02:03:41 PM PDT 23 Oct 08 02:05:07 PM PDT 23 2065824658 ps
T93 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4271039807 Oct 08 02:06:27 PM PDT 23 Oct 08 02:06:32 PM PDT 23 171334280 ps
T437 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.28745008 Oct 08 02:03:28 PM PDT 23 Oct 08 02:03:44 PM PDT 23 6920978718 ps
T438 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.40488257 Oct 08 02:08:54 PM PDT 23 Oct 08 02:09:04 PM PDT 23 3138107485 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4036863528 Oct 08 02:09:48 PM PDT 23 Oct 08 02:10:02 PM PDT 23 6273178358 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.929666021 Oct 08 02:08:49 PM PDT 23 Oct 08 02:08:54 PM PDT 23 106550866 ps
T440 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3021030720 Oct 08 02:08:05 PM PDT 23 Oct 08 02:13:24 PM PDT 23 172468859767 ps
T441 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2850993854 Oct 08 01:59:38 PM PDT 23 Oct 08 02:02:19 PM PDT 23 16999617091 ps
T442 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.670801476 Oct 08 01:58:49 PM PDT 23 Oct 08 01:58:54 PM PDT 23 309208628 ps
T443 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2076814425 Oct 08 02:08:00 PM PDT 23 Oct 08 02:08:14 PM PDT 23 816471096 ps
T97 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3061756575 Oct 08 02:08:53 PM PDT 23 Oct 08 02:11:33 PM PDT 23 75333836729 ps
T106 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1942762250 Oct 08 02:02:48 PM PDT 23 Oct 08 02:04:06 PM PDT 23 1700770387 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1602731016 Oct 08 02:08:37 PM PDT 23 Oct 08 02:09:59 PM PDT 23 1842810703 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1364582203 Oct 08 02:05:28 PM PDT 23 Oct 08 02:05:32 PM PDT 23 87575301 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3167940185 Oct 08 02:04:02 PM PDT 23 Oct 08 02:04:45 PM PDT 23 1404347317 ps
T445 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3184651229 Oct 08 02:09:14 PM PDT 23 Oct 08 02:09:30 PM PDT 23 8237416470 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1684219219 Oct 08 02:01:02 PM PDT 23 Oct 08 02:07:25 PM PDT 23 175849317940 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3852432272 Oct 08 02:10:25 PM PDT 23 Oct 08 02:10:39 PM PDT 23 4443850548 ps
T448 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.533722624 Oct 08 01:57:25 PM PDT 23 Oct 08 01:59:55 PM PDT 23 24743151888 ps
T449 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3357705976 Oct 08 02:04:59 PM PDT 23 Oct 08 02:05:04 PM PDT 23 272039429 ps
T450 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1184726518 Oct 08 02:02:18 PM PDT 23 Oct 08 02:02:31 PM PDT 23 3761164467 ps
T451 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.252585565 Oct 08 02:05:10 PM PDT 23 Oct 08 02:05:16 PM PDT 23 669684390 ps
T452 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1059575349 Oct 08 02:07:25 PM PDT 23 Oct 08 02:07:45 PM PDT 23 2089695625 ps
T453 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3416305145 Oct 08 02:06:00 PM PDT 23 Oct 08 02:06:13 PM PDT 23 908588031 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1235390197 Oct 08 02:02:08 PM PDT 23 Oct 08 02:02:21 PM PDT 23 1227396103 ps
T455 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.707001174 Oct 08 02:04:59 PM PDT 23 Oct 08 02:05:51 PM PDT 23 1024884310 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3754863177 Oct 08 02:03:55 PM PDT 23 Oct 08 02:04:01 PM PDT 23 596215498 ps
T457 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.505846308 Oct 08 02:02:22 PM PDT 23 Oct 08 02:03:12 PM PDT 23 1914390594 ps
T458 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3865676041 Oct 08 02:03:55 PM PDT 23 Oct 08 02:04:12 PM PDT 23 7915139560 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1413079969 Oct 08 02:02:06 PM PDT 23 Oct 08 02:02:21 PM PDT 23 12607948564 ps
T460 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.405057849 Oct 08 01:58:40 PM PDT 23 Oct 08 01:59:59 PM PDT 23 3301930115 ps
T461 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3743178241 Oct 08 01:58:09 PM PDT 23 Oct 08 01:58:21 PM PDT 23 3767995177 ps
T462 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3901996719 Oct 08 02:10:23 PM PDT 23 Oct 08 02:10:41 PM PDT 23 4186439621 ps
T109 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1475205156 Oct 08 02:09:48 PM PDT 23 Oct 08 02:11:10 PM PDT 23 3428455781 ps
T463 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3098705764 Oct 08 02:10:26 PM PDT 23 Oct 08 02:10:41 PM PDT 23 1210894589 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1210152091 Oct 08 02:00:17 PM PDT 23 Oct 08 02:01:04 PM PDT 23 5724178145 ps
T464 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2214851702 Oct 08 02:10:35 PM PDT 23 Oct 08 02:10:45 PM PDT 23 2918044233 ps
T465 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2944989476 Oct 08 01:57:36 PM PDT 23 Oct 08 01:57:48 PM PDT 23 2322169911 ps
T466 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2794215946 Oct 08 02:09:35 PM PDT 23 Oct 08 02:09:48 PM PDT 23 2770259472 ps
T467 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2600618872 Oct 08 01:59:04 PM PDT 23 Oct 08 01:59:12 PM PDT 23 905836791 ps
T95 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2769870806 Oct 08 02:01:36 PM PDT 23 Oct 08 02:03:46 PM PDT 23 11334260767 ps
T468 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.585536515 Oct 08 02:10:27 PM PDT 23 Oct 08 02:13:47 PM PDT 23 90274983636 ps
T469 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2004470444 Oct 08 01:56:54 PM PDT 23 Oct 08 01:57:04 PM PDT 23 1871347024 ps
T470 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2867893101 Oct 08 02:09:13 PM PDT 23 Oct 08 02:10:07 PM PDT 23 4411835596 ps
T471 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3111122060 Oct 08 02:08:06 PM PDT 23 Oct 08 02:08:54 PM PDT 23 3912135720 ps
T96 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2645470072 Oct 08 02:04:44 PM PDT 23 Oct 08 02:06:27 PM PDT 23 7445059624 ps
T472 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1114317605 Oct 08 01:58:15 PM PDT 23 Oct 08 01:58:27 PM PDT 23 2587414832 ps
T473 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3152413110 Oct 08 02:02:12 PM PDT 23 Oct 08 02:04:45 PM PDT 23 29168110194 ps
T474 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3810001717 Oct 08 01:57:34 PM PDT 23 Oct 08 01:57:46 PM PDT 23 24756233944 ps
T475 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3648476330 Oct 08 02:10:23 PM PDT 23 Oct 08 02:10:39 PM PDT 23 1880416617 ps
T476 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3535007192 Oct 08 01:58:50 PM PDT 23 Oct 08 01:58:54 PM PDT 23 88132495 ps
T477 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4209956851 Oct 08 01:56:47 PM PDT 23 Oct 08 01:57:04 PM PDT 23 2217043367 ps
T478 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3334522371 Oct 08 02:00:12 PM PDT 23 Oct 08 02:00:18 PM PDT 23 346557461 ps
T114 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2004046373 Oct 08 02:04:10 PM PDT 23 Oct 08 02:04:54 PM PDT 23 3198671239 ps
T479 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.302400995 Oct 08 01:58:23 PM PDT 23 Oct 08 01:58:32 PM PDT 23 433432717 ps
T480 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2590829034 Oct 08 02:06:29 PM PDT 23 Oct 08 02:06:40 PM PDT 23 2332194608 ps
T481 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.430771875 Oct 08 02:10:26 PM PDT 23 Oct 08 02:10:36 PM PDT 23 884937821 ps

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.885742534
Short name T24
Test name
Test status
Simulation time 555686463 ps
CPU time 40 seconds
Started Oct 08 01:58:25 PM PDT 23
Finished Oct 08 01:59:05 PM PDT 23
Peak memory 218924 kb
Host smart-db32dc79-74a1-4e8b-8231-211db74bdb07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885742534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.885742534
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3366913553
Short name T5
Test name
Test status
Simulation time 172595361526 ps
CPU time 1829.52 seconds
Started Oct 08 03:50:58 PM PDT 23
Finished Oct 08 04:21:28 PM PDT 23
Peak memory 244688 kb
Host smart-0bf0ae98-02dd-4388-b600-e39f1475708a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366913553 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3366913553
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1438807395
Short name T47
Test name
Test status
Simulation time 97015576777 ps
CPU time 273.96 seconds
Started Oct 08 02:03:41 PM PDT 23
Finished Oct 08 02:08:15 PM PDT 23
Peak memory 218936 kb
Host smart-6d61c877-a2c6-4c6d-8f0f-bc979887ef2a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438807395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1438807395
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2798713770
Short name T50
Test name
Test status
Simulation time 491224965 ps
CPU time 8.67 seconds
Started Oct 08 02:00:58 PM PDT 23
Finished Oct 08 02:01:07 PM PDT 23
Peak memory 218956 kb
Host smart-00118ca1-9630-448b-892f-bd257d9a09ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798713770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2798713770
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3538861788
Short name T21
Test name
Test status
Simulation time 177503289966 ps
CPU time 485.45 seconds
Started Oct 08 03:46:17 PM PDT 23
Finished Oct 08 03:54:23 PM PDT 23
Peak memory 237740 kb
Host smart-6bb2b775-74af-4af7-924e-b3ce14087d60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538861788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3538861788
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3077402744
Short name T1
Test name
Test status
Simulation time 20967172418 ps
CPU time 31.01 seconds
Started Oct 08 03:43:23 PM PDT 23
Finished Oct 08 03:43:54 PM PDT 23
Peak memory 213728 kb
Host smart-2da52f66-486e-4136-b760-3d5ea2fc2890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077402744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3077402744
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4214290982
Short name T110
Test name
Test status
Simulation time 2065824658 ps
CPU time 85.48 seconds
Started Oct 08 02:03:41 PM PDT 23
Finished Oct 08 02:05:07 PM PDT 23
Peak memory 210948 kb
Host smart-85c2a8e1-36fc-4df8-ab7a-fc1ee1eb805e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214290982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4214290982
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1504950326
Short name T32
Test name
Test status
Simulation time 257713095 ps
CPU time 76.74 seconds
Started Oct 08 01:58:56 PM PDT 23
Finished Oct 08 02:00:13 PM PDT 23
Peak memory 212196 kb
Host smart-d12429cd-d4a3-4dc3-995f-97741fe0401a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504950326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1504950326
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1423576334
Short name T52
Test name
Test status
Simulation time 10095464501 ps
CPU time 117.67 seconds
Started Oct 08 03:44:38 PM PDT 23
Finished Oct 08 03:46:36 PM PDT 23
Peak memory 236284 kb
Host smart-2519ef17-b4f7-4b33-930f-09df910c1e14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423576334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1423576334
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4101396156
Short name T15
Test name
Test status
Simulation time 60960193001 ps
CPU time 6989.54 seconds
Started Oct 08 03:55:22 PM PDT 23
Finished Oct 08 05:51:52 PM PDT 23
Peak memory 238240 kb
Host smart-ddb59605-0d22-4721-b992-a4787789e102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101396156 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4101396156
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3694778090
Short name T17
Test name
Test status
Simulation time 9852075298 ps
CPU time 13.09 seconds
Started Oct 08 03:46:34 PM PDT 23
Finished Oct 08 03:46:47 PM PDT 23
Peak memory 211600 kb
Host smart-ea7d0151-557c-418a-8bd7-18a0563cbf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694778090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3694778090
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.279670842
Short name T76
Test name
Test status
Simulation time 213753127 ps
CPU time 71.72 seconds
Started Oct 08 01:57:15 PM PDT 23
Finished Oct 08 01:58:27 PM PDT 23
Peak memory 218824 kb
Host smart-077f7cd1-2f15-4f8b-865e-664efdc87ef2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279670842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.279670842
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1313115769
Short name T115
Test name
Test status
Simulation time 239250065937 ps
CPU time 4897.32 seconds
Started Oct 08 03:45:38 PM PDT 23
Finished Oct 08 05:07:16 PM PDT 23
Peak memory 233652 kb
Host smart-3fc83a1c-e880-4e7b-b6d5-8eca0c62789c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313115769 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1313115769
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.202805826
Short name T73
Test name
Test status
Simulation time 217217021 ps
CPU time 8.41 seconds
Started Oct 08 01:56:39 PM PDT 23
Finished Oct 08 01:56:48 PM PDT 23
Peak memory 218848 kb
Host smart-a8788556-016d-4cf3-9f64-bda40a69a52e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202805826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.202805826
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1827972065
Short name T324
Test name
Test status
Simulation time 173941209 ps
CPU time 9.83 seconds
Started Oct 08 03:49:02 PM PDT 23
Finished Oct 08 03:49:12 PM PDT 23
Peak memory 211216 kb
Host smart-70effbb4-75cb-4ea0-a1e3-791ae51a2152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827972065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1827972065
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.220260480
Short name T150
Test name
Test status
Simulation time 1697711345 ps
CPU time 14.13 seconds
Started Oct 08 03:44:34 PM PDT 23
Finished Oct 08 03:44:48 PM PDT 23
Peak memory 211072 kb
Host smart-5c61226a-5c43-4c49-89e7-e198bc49a0a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220260480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.220260480
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1210152091
Short name T111
Test name
Test status
Simulation time 5724178145 ps
CPU time 46.76 seconds
Started Oct 08 02:00:17 PM PDT 23
Finished Oct 08 02:01:04 PM PDT 23
Peak memory 218996 kb
Host smart-effa5be7-83bc-4457-b3d9-74af4401018b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210152091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1210152091
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1726804334
Short name T79
Test name
Test status
Simulation time 1194263494 ps
CPU time 7.91 seconds
Started Oct 08 02:01:48 PM PDT 23
Finished Oct 08 02:02:03 PM PDT 23
Peak memory 210732 kb
Host smart-0d9490b1-b89b-4774-8024-2796f3e239d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726804334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1726804334
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2790262663
Short name T136
Test name
Test status
Simulation time 1703678342 ps
CPU time 14.38 seconds
Started Oct 08 01:58:28 PM PDT 23
Finished Oct 08 01:58:42 PM PDT 23
Peak memory 210732 kb
Host smart-e8411144-63ae-40a8-b4dc-a92745ca2072
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790262663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2790262663
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1235390197
Short name T454
Test name
Test status
Simulation time 1227396103 ps
CPU time 13.49 seconds
Started Oct 08 02:02:08 PM PDT 23
Finished Oct 08 02:02:21 PM PDT 23
Peak memory 218296 kb
Host smart-201f2b23-82d5-4dd5-9956-2164a3760555
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235390197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1235390197
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1413079969
Short name T459
Test name
Test status
Simulation time 12607948564 ps
CPU time 15.67 seconds
Started Oct 08 02:02:06 PM PDT 23
Finished Oct 08 02:02:21 PM PDT 23
Peak memory 219028 kb
Host smart-e06ee4ca-f980-4e46-b392-734eac509206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413079969 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1413079969
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.809435368
Short name T37
Test name
Test status
Simulation time 208880931 ps
CPU time 5.71 seconds
Started Oct 08 01:56:42 PM PDT 23
Finished Oct 08 01:56:48 PM PDT 23
Peak memory 210676 kb
Host smart-322510ae-6862-4e8e-b4c4-689422bb2f80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809435368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.809435368
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.442449305
Short name T147
Test name
Test status
Simulation time 1157424404 ps
CPU time 10.83 seconds
Started Oct 08 02:05:26 PM PDT 23
Finished Oct 08 02:05:38 PM PDT 23
Peak memory 210672 kb
Host smart-6a04eb8d-6887-4092-8e31-5a9bf8553e53
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442449305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.442449305
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.889006944
Short name T35
Test name
Test status
Simulation time 641362634 ps
CPU time 8.22 seconds
Started Oct 08 02:05:27 PM PDT 23
Finished Oct 08 02:05:36 PM PDT 23
Peak memory 210548 kb
Host smart-70d14a83-e9b5-4b61-872a-e693ba1ee803
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889006944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
889006944
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2769870806
Short name T95
Test name
Test status
Simulation time 11334260767 ps
CPU time 130.18 seconds
Started Oct 08 02:01:36 PM PDT 23
Finished Oct 08 02:03:46 PM PDT 23
Peak memory 218992 kb
Host smart-1e34a762-9911-406b-941a-93038e2026fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769870806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2769870806
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1519784808
Short name T99
Test name
Test status
Simulation time 108878695 ps
CPU time 4.47 seconds
Started Oct 08 02:01:47 PM PDT 23
Finished Oct 08 02:01:51 PM PDT 23
Peak memory 216476 kb
Host smart-f5c67bb1-053b-4b81-8594-c64f5390f192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519784808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1519784808
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.418215286
Short name T71
Test name
Test status
Simulation time 631474313 ps
CPU time 43.36 seconds
Started Oct 08 02:05:36 PM PDT 23
Finished Oct 08 02:06:20 PM PDT 23
Peak memory 217680 kb
Host smart-d0caab5d-5217-418e-9af2-74f5005fcfbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418215286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.418215286
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.430771875
Short name T481
Test name
Test status
Simulation time 884937821 ps
CPU time 9.66 seconds
Started Oct 08 02:10:26 PM PDT 23
Finished Oct 08 02:10:36 PM PDT 23
Peak memory 210904 kb
Host smart-cd9f5996-6b53-4101-b414-ac208ec37f28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430771875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.430771875
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3786781890
Short name T88
Test name
Test status
Simulation time 12725481819 ps
CPU time 16.52 seconds
Started Oct 08 01:56:44 PM PDT 23
Finished Oct 08 01:57:00 PM PDT 23
Peak memory 217552 kb
Host smart-488457a3-f237-4b3b-9ab6-a641d823a232
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786781890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3786781890
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3098705764
Short name T463
Test name
Test status
Simulation time 1210894589 ps
CPU time 14.01 seconds
Started Oct 08 02:10:26 PM PDT 23
Finished Oct 08 02:10:41 PM PDT 23
Peak memory 218212 kb
Host smart-730f2653-0713-48ba-a7f9-e701deab6d5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098705764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3098705764
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2944989476
Short name T465
Test name
Test status
Simulation time 2322169911 ps
CPU time 12.62 seconds
Started Oct 08 01:57:36 PM PDT 23
Finished Oct 08 01:57:48 PM PDT 23
Peak memory 219076 kb
Host smart-1cb411ce-8e43-4222-b874-408217c47394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944989476 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2944989476
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3852432272
Short name T447
Test name
Test status
Simulation time 4443850548 ps
CPU time 13.48 seconds
Started Oct 08 02:10:25 PM PDT 23
Finished Oct 08 02:10:39 PM PDT 23
Peak memory 210612 kb
Host smart-4bfd9fc2-c0f1-4d92-b89a-12c0c1cd3fcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852432272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3852432272
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2236681901
Short name T130
Test name
Test status
Simulation time 89148781 ps
CPU time 4.61 seconds
Started Oct 08 02:00:34 PM PDT 23
Finished Oct 08 02:00:39 PM PDT 23
Peak memory 210788 kb
Host smart-28155db8-22ef-4c73-872e-9a21dffff519
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236681901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2236681901
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2856895721
Short name T121
Test name
Test status
Simulation time 7630255260 ps
CPU time 15.33 seconds
Started Oct 08 01:59:40 PM PDT 23
Finished Oct 08 01:59:56 PM PDT 23
Peak memory 210760 kb
Host smart-128b9470-7d51-422a-9d1f-c63c61ec9951
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856895721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2856895721
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1684219219
Short name T446
Test name
Test status
Simulation time 175849317940 ps
CPU time 382.75 seconds
Started Oct 08 02:01:02 PM PDT 23
Finished Oct 08 02:07:25 PM PDT 23
Peak memory 219008 kb
Host smart-3d147768-5587-4dc8-b8e6-4fd239f41b9d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684219219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1684219219
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3535007192
Short name T476
Test name
Test status
Simulation time 88132495 ps
CPU time 4.4 seconds
Started Oct 08 01:58:50 PM PDT 23
Finished Oct 08 01:58:54 PM PDT 23
Peak memory 210768 kb
Host smart-4d3615b0-b54d-4a61-9810-ce2282cdf98d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535007192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3535007192
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.302400995
Short name T479
Test name
Test status
Simulation time 433432717 ps
CPU time 8.31 seconds
Started Oct 08 01:58:23 PM PDT 23
Finished Oct 08 01:58:32 PM PDT 23
Peak memory 219108 kb
Host smart-9c37b84f-caef-491f-8f2d-5816f03cd6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302400995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.302400995
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2364164258
Short name T101
Test name
Test status
Simulation time 2147730086 ps
CPU time 17.64 seconds
Started Oct 08 02:08:03 PM PDT 23
Finished Oct 08 02:08:21 PM PDT 23
Peak memory 218896 kb
Host smart-ad5ecd44-991d-45f3-8463-adfc60a9bc87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364164258 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2364164258
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4271039807
Short name T93
Test name
Test status
Simulation time 171334280 ps
CPU time 4.4 seconds
Started Oct 08 02:06:27 PM PDT 23
Finished Oct 08 02:06:32 PM PDT 23
Peak memory 210752 kb
Host smart-d5a06fb6-cb48-4cf2-a087-28ab4dadb5b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271039807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4271039807
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3484708672
Short name T83
Test name
Test status
Simulation time 9469869608 ps
CPU time 114.88 seconds
Started Oct 08 02:07:51 PM PDT 23
Finished Oct 08 02:09:46 PM PDT 23
Peak memory 218952 kb
Host smart-e421c568-dcee-4626-9543-e4fa6752cc2d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484708672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3484708672
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2222325871
Short name T38
Test name
Test status
Simulation time 1259170797 ps
CPU time 9.1 seconds
Started Oct 08 01:59:58 PM PDT 23
Finished Oct 08 02:00:07 PM PDT 23
Peak memory 210620 kb
Host smart-5ed1cdde-63ab-400a-8674-64f5104b2390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222325871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2222325871
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.405057849
Short name T460
Test name
Test status
Simulation time 3301930115 ps
CPU time 78.93 seconds
Started Oct 08 01:58:40 PM PDT 23
Finished Oct 08 01:59:59 PM PDT 23
Peak memory 211040 kb
Host smart-ea08a8cf-b3f3-4bbc-ab5d-94417528a9f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405057849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.405057849
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2747459731
Short name T75
Test name
Test status
Simulation time 92376903 ps
CPU time 4.77 seconds
Started Oct 08 02:04:05 PM PDT 23
Finished Oct 08 02:04:10 PM PDT 23
Peak memory 212740 kb
Host smart-0ce9c254-69c2-4556-9fef-7b11016ff0d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747459731 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2747459731
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1534694248
Short name T145
Test name
Test status
Simulation time 2128678046 ps
CPU time 16.89 seconds
Started Oct 08 02:10:11 PM PDT 23
Finished Oct 08 02:10:29 PM PDT 23
Peak memory 217124 kb
Host smart-95990e98-8f71-4851-a87c-c7775c1d3b61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534694248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1534694248
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1491631488
Short name T49
Test name
Test status
Simulation time 38585258694 ps
CPU time 348.03 seconds
Started Oct 08 01:59:53 PM PDT 23
Finished Oct 08 02:05:41 PM PDT 23
Peak memory 219092 kb
Host smart-3470533d-4e72-474c-8212-66abf8b95b72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491631488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1491631488
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3862294860
Short name T89
Test name
Test status
Simulation time 921479399 ps
CPU time 4.52 seconds
Started Oct 08 02:08:04 PM PDT 23
Finished Oct 08 02:08:09 PM PDT 23
Peak memory 210616 kb
Host smart-19335a78-914f-43ee-bfbc-96b0dc0371f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862294860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3862294860
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2076814425
Short name T443
Test name
Test status
Simulation time 816471096 ps
CPU time 13.8 seconds
Started Oct 08 02:08:00 PM PDT 23
Finished Oct 08 02:08:14 PM PDT 23
Peak memory 218912 kb
Host smart-77f3686c-42d2-420e-b8da-6ccdf7bbba31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076814425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2076814425
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2002340417
Short name T117
Test name
Test status
Simulation time 8610126837 ps
CPU time 15.82 seconds
Started Oct 08 02:02:08 PM PDT 23
Finished Oct 08 02:02:24 PM PDT 23
Peak memory 211656 kb
Host smart-de48de2e-a6b0-49ad-9205-fffd43ddfab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002340417 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2002340417
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2830283786
Short name T92
Test name
Test status
Simulation time 2060699640 ps
CPU time 15.76 seconds
Started Oct 08 02:05:05 PM PDT 23
Finished Oct 08 02:05:21 PM PDT 23
Peak memory 210660 kb
Host smart-c75d4655-970b-4078-b4cb-bf3c328f6c64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830283786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2830283786
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1200484496
Short name T48
Test name
Test status
Simulation time 6409438218 ps
CPU time 98.29 seconds
Started Oct 08 01:57:15 PM PDT 23
Finished Oct 08 01:58:54 PM PDT 23
Peak memory 218992 kb
Host smart-b353b4da-111d-4667-93a9-fa8bb29d5fd8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200484496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1200484496
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2742128348
Short name T86
Test name
Test status
Simulation time 88288193 ps
CPU time 4.25 seconds
Started Oct 08 02:05:07 PM PDT 23
Finished Oct 08 02:05:11 PM PDT 23
Peak memory 210536 kb
Host smart-cd489229-964f-4c8e-a574-100d33ec5fe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742128348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2742128348
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2545862968
Short name T116
Test name
Test status
Simulation time 4408189812 ps
CPU time 21.09 seconds
Started Oct 08 02:03:19 PM PDT 23
Finished Oct 08 02:03:40 PM PDT 23
Peak memory 219148 kb
Host smart-1bec4b94-b3aa-4e4a-b97a-d9c5b57940c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545862968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2545862968
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2225993799
Short name T139
Test name
Test status
Simulation time 5163329366 ps
CPU time 11.94 seconds
Started Oct 08 02:02:51 PM PDT 23
Finished Oct 08 02:03:03 PM PDT 23
Peak memory 218884 kb
Host smart-dec0fcdc-566b-45bb-a83d-badcc10f2c07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225993799 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2225993799
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2074708732
Short name T98
Test name
Test status
Simulation time 2134045540 ps
CPU time 15.69 seconds
Started Oct 08 01:59:34 PM PDT 23
Finished Oct 08 01:59:50 PM PDT 23
Peak memory 217024 kb
Host smart-d8f061ad-7695-46d3-800d-237a8f853bd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074708732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2074708732
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.670801476
Short name T442
Test name
Test status
Simulation time 309208628 ps
CPU time 4.57 seconds
Started Oct 08 01:58:49 PM PDT 23
Finished Oct 08 01:58:54 PM PDT 23
Peak memory 210688 kb
Host smart-47d48f0d-1861-42c6-a6a8-6b2534012ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670801476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.670801476
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3416305145
Short name T453
Test name
Test status
Simulation time 908588031 ps
CPU time 12.76 seconds
Started Oct 08 02:06:00 PM PDT 23
Finished Oct 08 02:06:13 PM PDT 23
Peak memory 218852 kb
Host smart-1837b8b5-6773-4310-bb8e-1758d99d7a37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416305145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3416305145
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.505846308
Short name T457
Test name
Test status
Simulation time 1914390594 ps
CPU time 49.61 seconds
Started Oct 08 02:02:22 PM PDT 23
Finished Oct 08 02:03:12 PM PDT 23
Peak memory 218792 kb
Host smart-aecccab3-5483-4557-9c63-fd9a22d54360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505846308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.505846308
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1276521542
Short name T140
Test name
Test status
Simulation time 1701934566 ps
CPU time 9.66 seconds
Started Oct 08 01:57:36 PM PDT 23
Finished Oct 08 01:57:46 PM PDT 23
Peak memory 210800 kb
Host smart-d5339f4b-14a9-4d66-a197-b9dccdf43919
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276521542 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1276521542
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1364582203
Short name T444
Test name
Test status
Simulation time 87575301 ps
CPU time 4.26 seconds
Started Oct 08 02:05:28 PM PDT 23
Finished Oct 08 02:05:32 PM PDT 23
Peak memory 210736 kb
Host smart-32f4cc4b-4ccc-48d1-a945-c2a3caa959bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364582203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1364582203
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3021030720
Short name T440
Test name
Test status
Simulation time 172468859767 ps
CPU time 318.13 seconds
Started Oct 08 02:08:05 PM PDT 23
Finished Oct 08 02:13:24 PM PDT 23
Peak memory 210800 kb
Host smart-8d1c9264-8024-41d6-8a1d-ddb63481a58f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021030720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3021030720
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4036863528
Short name T439
Test name
Test status
Simulation time 6273178358 ps
CPU time 13.52 seconds
Started Oct 08 02:09:48 PM PDT 23
Finished Oct 08 02:10:02 PM PDT 23
Peak memory 217748 kb
Host smart-bd666b9e-063f-4322-a483-9b67199117ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036863528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4036863528
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1059575349
Short name T452
Test name
Test status
Simulation time 2089695625 ps
CPU time 19.06 seconds
Started Oct 08 02:07:25 PM PDT 23
Finished Oct 08 02:07:45 PM PDT 23
Peak memory 218748 kb
Host smart-2344b9ee-2d5f-4de3-8461-55d7f7fe656c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059575349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1059575349
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1475205156
Short name T109
Test name
Test status
Simulation time 3428455781 ps
CPU time 81.73 seconds
Started Oct 08 02:09:48 PM PDT 23
Finished Oct 08 02:11:10 PM PDT 23
Peak memory 218896 kb
Host smart-79cbc283-feae-4642-865d-399597788f72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475205156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1475205156
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3184651229
Short name T445
Test name
Test status
Simulation time 8237416470 ps
CPU time 15.98 seconds
Started Oct 08 02:09:14 PM PDT 23
Finished Oct 08 02:09:30 PM PDT 23
Peak memory 218928 kb
Host smart-33bf3423-6766-4f78-9ea0-1c34c8d24c53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184651229 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3184651229
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.722465407
Short name T434
Test name
Test status
Simulation time 6675333790 ps
CPU time 12.87 seconds
Started Oct 08 01:59:17 PM PDT 23
Finished Oct 08 01:59:30 PM PDT 23
Peak memory 217500 kb
Host smart-d88fe4d1-2dd8-4538-b0ab-7d5664dd15ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722465407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.722465407
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3519400697
Short name T82
Test name
Test status
Simulation time 5932781222 ps
CPU time 96.6 seconds
Started Oct 08 01:57:14 PM PDT 23
Finished Oct 08 01:58:51 PM PDT 23
Peak memory 210700 kb
Host smart-1b126499-be81-4393-aba8-e854e6c64212
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519400697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3519400697
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.445393179
Short name T128
Test name
Test status
Simulation time 1055187160 ps
CPU time 10.67 seconds
Started Oct 08 02:01:09 PM PDT 23
Finished Oct 08 02:01:20 PM PDT 23
Peak memory 210756 kb
Host smart-35037025-bd61-4df4-b602-905a52a48639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445393179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.445393179
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4096203970
Short name T119
Test name
Test status
Simulation time 1326245129 ps
CPU time 16.57 seconds
Started Oct 08 02:07:07 PM PDT 23
Finished Oct 08 02:07:24 PM PDT 23
Peak memory 218908 kb
Host smart-5467dfe5-7443-43f5-a841-ab16ea449d80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096203970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4096203970
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.583511329
Short name T39
Test name
Test status
Simulation time 2944375440 ps
CPU time 8.94 seconds
Started Oct 08 02:07:46 PM PDT 23
Finished Oct 08 02:07:55 PM PDT 23
Peak memory 219140 kb
Host smart-e82bd88e-bd8e-4d88-b8f0-a946b1edf199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583511329 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.583511329
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3648476330
Short name T475
Test name
Test status
Simulation time 1880416617 ps
CPU time 14.75 seconds
Started Oct 08 02:10:23 PM PDT 23
Finished Oct 08 02:10:39 PM PDT 23
Peak memory 217096 kb
Host smart-38d51513-00dd-4da4-a912-79641b153997
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648476330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3648476330
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2645470072
Short name T96
Test name
Test status
Simulation time 7445059624 ps
CPU time 103.04 seconds
Started Oct 08 02:04:44 PM PDT 23
Finished Oct 08 02:06:27 PM PDT 23
Peak memory 210780 kb
Host smart-206f1596-1375-4176-bec0-f86b08c52eab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645470072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2645470072
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3901996719
Short name T462
Test name
Test status
Simulation time 4186439621 ps
CPU time 16.62 seconds
Started Oct 08 02:10:23 PM PDT 23
Finished Oct 08 02:10:41 PM PDT 23
Peak memory 217544 kb
Host smart-b9d7c5d0-1656-4bc3-bf5c-0c62d3a7d85c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901996719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3901996719
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3814558239
Short name T77
Test name
Test status
Simulation time 3277557514 ps
CPU time 15.35 seconds
Started Oct 08 01:57:25 PM PDT 23
Finished Oct 08 01:57:41 PM PDT 23
Peak memory 218972 kb
Host smart-b1702058-9c20-4706-89c7-96055119972e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814558239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3814558239
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1602731016
Short name T107
Test name
Test status
Simulation time 1842810703 ps
CPU time 82.26 seconds
Started Oct 08 02:08:37 PM PDT 23
Finished Oct 08 02:09:59 PM PDT 23
Peak memory 210844 kb
Host smart-cb0ead1b-3a0f-4147-a4fb-356172feeed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602731016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1602731016
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3810001717
Short name T474
Test name
Test status
Simulation time 24756233944 ps
CPU time 11.78 seconds
Started Oct 08 01:57:34 PM PDT 23
Finished Oct 08 01:57:46 PM PDT 23
Peak memory 213688 kb
Host smart-ece8569b-17dc-472e-b032-877e53ed52fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810001717 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3810001717
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2041064562
Short name T34
Test name
Test status
Simulation time 7317284646 ps
CPU time 15.85 seconds
Started Oct 08 01:59:40 PM PDT 23
Finished Oct 08 01:59:56 PM PDT 23
Peak memory 210828 kb
Host smart-f5a7aeca-b010-48d6-b41c-fc9a1f924da2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041064562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2041064562
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.533722624
Short name T448
Test name
Test status
Simulation time 24743151888 ps
CPU time 149.45 seconds
Started Oct 08 01:57:25 PM PDT 23
Finished Oct 08 01:59:55 PM PDT 23
Peak memory 210716 kb
Host smart-4f60d3d4-da19-4dd9-a150-83a80846c90f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533722624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.533722624
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.40488257
Short name T438
Test name
Test status
Simulation time 3138107485 ps
CPU time 9.19 seconds
Started Oct 08 02:08:54 PM PDT 23
Finished Oct 08 02:09:04 PM PDT 23
Peak memory 217588 kb
Host smart-966454c0-32a9-4018-93e0-1fea6a58efe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40488257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ct
rl_same_csr_outstanding.40488257
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3978154470
Short name T432
Test name
Test status
Simulation time 475934964 ps
CPU time 9.22 seconds
Started Oct 08 02:01:51 PM PDT 23
Finished Oct 08 02:02:04 PM PDT 23
Peak memory 218852 kb
Host smart-5eea45bc-9c1e-43ed-8b1b-dbbdf1f47fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978154470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3978154470
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2650447427
Short name T108
Test name
Test status
Simulation time 2253683296 ps
CPU time 50.08 seconds
Started Oct 08 01:57:31 PM PDT 23
Finished Oct 08 01:58:21 PM PDT 23
Peak memory 211980 kb
Host smart-3101bed6-2f9f-40e7-8dec-a3e1bacc401c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650447427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2650447427
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3234685327
Short name T142
Test name
Test status
Simulation time 9133198062 ps
CPU time 16.21 seconds
Started Oct 08 01:57:31 PM PDT 23
Finished Oct 08 01:57:47 PM PDT 23
Peak memory 218900 kb
Host smart-b793f75a-28ef-4afd-970f-cf2ec534836e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234685327 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3234685327
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2621107664
Short name T137
Test name
Test status
Simulation time 347312063 ps
CPU time 4.39 seconds
Started Oct 08 01:58:56 PM PDT 23
Finished Oct 08 01:59:00 PM PDT 23
Peak memory 210620 kb
Host smart-23a389c7-03f8-4e34-9dab-154376d5e740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621107664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2621107664
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2850993854
Short name T441
Test name
Test status
Simulation time 16999617091 ps
CPU time 160.63 seconds
Started Oct 08 01:59:38 PM PDT 23
Finished Oct 08 02:02:19 PM PDT 23
Peak memory 218852 kb
Host smart-4a8b862c-7145-4191-8fd8-e49768e23cef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850993854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2850993854
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3368782961
Short name T123
Test name
Test status
Simulation time 226524555 ps
CPU time 8.01 seconds
Started Oct 08 01:59:38 PM PDT 23
Finished Oct 08 01:59:46 PM PDT 23
Peak memory 210756 kb
Host smart-2e17e604-22f4-4522-b184-84685302cfed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368782961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3368782961
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2191188096
Short name T129
Test name
Test status
Simulation time 1339099056 ps
CPU time 11.82 seconds
Started Oct 08 01:57:30 PM PDT 23
Finished Oct 08 01:57:42 PM PDT 23
Peak memory 218976 kb
Host smart-7c994ee3-0949-45bf-8a46-cd3a9f4230e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191188096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2191188096
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2092186905
Short name T46
Test name
Test status
Simulation time 443186227 ps
CPU time 5.12 seconds
Started Oct 08 01:57:50 PM PDT 23
Finished Oct 08 01:57:56 PM PDT 23
Peak memory 214008 kb
Host smart-0d8d2295-b243-471c-bee0-656d78734328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092186905 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2092186905
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2718581882
Short name T122
Test name
Test status
Simulation time 988745884 ps
CPU time 5.98 seconds
Started Oct 08 02:00:14 PM PDT 23
Finished Oct 08 02:00:21 PM PDT 23
Peak memory 210764 kb
Host smart-04d003fc-4abe-4bb2-83bd-6443c5735fbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718581882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2718581882
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3061756575
Short name T97
Test name
Test status
Simulation time 75333836729 ps
CPU time 160.07 seconds
Started Oct 08 02:08:53 PM PDT 23
Finished Oct 08 02:11:33 PM PDT 23
Peak memory 210968 kb
Host smart-314d64a3-dafc-4aa0-9b38-2fb5f55d4365
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061756575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3061756575
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2379043843
Short name T132
Test name
Test status
Simulation time 175151154 ps
CPU time 4.36 seconds
Started Oct 08 02:57:29 PM PDT 23
Finished Oct 08 02:57:34 PM PDT 23
Peak memory 210608 kb
Host smart-c4977a85-5c94-4558-84a1-09e769d56674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379043843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2379043843
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3838471143
Short name T72
Test name
Test status
Simulation time 2524589571 ps
CPU time 15.84 seconds
Started Oct 08 02:00:37 PM PDT 23
Finished Oct 08 02:00:53 PM PDT 23
Peak memory 218964 kb
Host smart-b0c8b075-7bfd-4006-b9fe-8351fab46eee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838471143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3838471143
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3167940185
Short name T113
Test name
Test status
Simulation time 1404347317 ps
CPU time 42.8 seconds
Started Oct 08 02:04:02 PM PDT 23
Finished Oct 08 02:04:45 PM PDT 23
Peak memory 211800 kb
Host smart-9f4e9540-d75c-4e66-9cc6-64c9ffaebbe3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167940185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3167940185
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1060922907
Short name T125
Test name
Test status
Simulation time 5850493069 ps
CPU time 12.65 seconds
Started Oct 08 02:07:05 PM PDT 23
Finished Oct 08 02:07:18 PM PDT 23
Peak memory 210612 kb
Host smart-2690141e-8bc7-4d8a-9654-647d4ef918a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060922907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1060922907
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2025672599
Short name T134
Test name
Test status
Simulation time 1029142596 ps
CPU time 10.63 seconds
Started Oct 08 01:56:42 PM PDT 23
Finished Oct 08 01:56:53 PM PDT 23
Peak memory 210768 kb
Host smart-01aba3f7-e448-41d3-b758-2959937df302
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025672599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2025672599
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.899389503
Short name T80
Test name
Test status
Simulation time 1217708785 ps
CPU time 8.03 seconds
Started Oct 08 01:56:44 PM PDT 23
Finished Oct 08 01:56:52 PM PDT 23
Peak memory 210700 kb
Host smart-a8b219f4-a178-43fe-9ef6-f7807253270a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899389503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.899389503
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3509677160
Short name T433
Test name
Test status
Simulation time 383432182 ps
CPU time 7.16 seconds
Started Oct 08 02:02:38 PM PDT 23
Finished Oct 08 02:02:45 PM PDT 23
Peak memory 212980 kb
Host smart-d2da7c91-c1c4-4feb-b606-815da473cc3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509677160 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3509677160
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4209956851
Short name T477
Test name
Test status
Simulation time 2217043367 ps
CPU time 16.12 seconds
Started Oct 08 01:56:47 PM PDT 23
Finished Oct 08 01:57:04 PM PDT 23
Peak memory 217312 kb
Host smart-36e8cbbd-712e-4e6c-91cc-6dd73cc482f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209956851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.4209956851
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1872044049
Short name T436
Test name
Test status
Simulation time 4598278612 ps
CPU time 11.11 seconds
Started Oct 08 01:56:43 PM PDT 23
Finished Oct 08 01:56:55 PM PDT 23
Peak memory 210692 kb
Host smart-6605c377-5334-457d-b5ad-48303871cc4c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872044049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1872044049
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2861013954
Short name T127
Test name
Test status
Simulation time 3171846438 ps
CPU time 12.7 seconds
Started Oct 08 01:56:44 PM PDT 23
Finished Oct 08 01:56:57 PM PDT 23
Peak memory 210820 kb
Host smart-6583bdca-4b2f-49c8-922a-d92a5f5d995b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861013954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2861013954
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4132392128
Short name T84
Test name
Test status
Simulation time 1946297312 ps
CPU time 97.12 seconds
Started Oct 08 02:03:33 PM PDT 23
Finished Oct 08 02:05:11 PM PDT 23
Peak memory 210740 kb
Host smart-23c4c8c5-7bb7-4876-bfcd-76afffc7a873
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132392128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4132392128
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3334522371
Short name T478
Test name
Test status
Simulation time 346557461 ps
CPU time 5.55 seconds
Started Oct 08 02:00:12 PM PDT 23
Finished Oct 08 02:00:18 PM PDT 23
Peak memory 216104 kb
Host smart-42ac1fb2-4556-45bf-964b-861a221f3506
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334522371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3334522371
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2345366282
Short name T85
Test name
Test status
Simulation time 1829464062 ps
CPU time 18.02 seconds
Started Oct 08 01:56:45 PM PDT 23
Finished Oct 08 01:57:03 PM PDT 23
Peak memory 219016 kb
Host smart-4340e180-cf04-4ac3-89d9-8af4a1ce9702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345366282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2345366282
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2717031853
Short name T144
Test name
Test status
Simulation time 234754610 ps
CPU time 77.38 seconds
Started Oct 08 01:58:43 PM PDT 23
Finished Oct 08 02:00:01 PM PDT 23
Peak memory 218852 kb
Host smart-9daa26b4-c8e4-4ede-bd4e-675a985a60d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717031853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2717031853
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1552746734
Short name T102
Test name
Test status
Simulation time 2459155990 ps
CPU time 8.3 seconds
Started Oct 08 02:01:19 PM PDT 23
Finished Oct 08 02:01:28 PM PDT 23
Peak memory 216048 kb
Host smart-ab71f5e6-0cbb-4072-b76c-06a48ece12f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552746734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1552746734
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.977079710
Short name T40
Test name
Test status
Simulation time 165055359 ps
CPU time 4.74 seconds
Started Oct 08 02:10:26 PM PDT 23
Finished Oct 08 02:10:31 PM PDT 23
Peak memory 216240 kb
Host smart-2f8810af-76da-4f12-8da6-15a31e9c7865
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977079710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.977079710
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3743178241
Short name T461
Test name
Test status
Simulation time 3767995177 ps
CPU time 11.6 seconds
Started Oct 08 01:58:09 PM PDT 23
Finished Oct 08 01:58:21 PM PDT 23
Peak memory 218348 kb
Host smart-7713473c-e95d-45e4-a640-403e7cfb0928
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743178241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3743178241
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3558186777
Short name T133
Test name
Test status
Simulation time 335260439 ps
CPU time 4.52 seconds
Started Oct 08 02:07:03 PM PDT 23
Finished Oct 08 02:07:08 PM PDT 23
Peak memory 210860 kb
Host smart-c8d223c4-08d9-4293-ba18-db915c4b57e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558186777 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3558186777
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3865643200
Short name T135
Test name
Test status
Simulation time 2808706445 ps
CPU time 13.01 seconds
Started Oct 08 02:10:28 PM PDT 23
Finished Oct 08 02:10:41 PM PDT 23
Peak memory 210612 kb
Host smart-dd7c877e-b629-451b-b164-3932653fcefc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865643200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3865643200
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1245732874
Short name T33
Test name
Test status
Simulation time 2401428287 ps
CPU time 7.54 seconds
Started Oct 08 01:58:08 PM PDT 23
Finished Oct 08 01:58:16 PM PDT 23
Peak memory 210688 kb
Host smart-f1e42d78-c8ca-448f-a130-044681f2ae40
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245732874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1245732874
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4161506157
Short name T138
Test name
Test status
Simulation time 1522238814 ps
CPU time 8.68 seconds
Started Oct 08 02:06:29 PM PDT 23
Finished Oct 08 02:06:38 PM PDT 23
Peak memory 210624 kb
Host smart-f440a889-a469-4bcc-b06c-66e9e460676f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161506157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4161506157
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.585536515
Short name T468
Test name
Test status
Simulation time 90274983636 ps
CPU time 199.6 seconds
Started Oct 08 02:10:27 PM PDT 23
Finished Oct 08 02:13:47 PM PDT 23
Peak memory 218916 kb
Host smart-09d11eba-645d-4a57-b79f-ddaf3aa29732
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585536515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.585536515
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2794215946
Short name T466
Test name
Test status
Simulation time 2770259472 ps
CPU time 12.4 seconds
Started Oct 08 02:09:35 PM PDT 23
Finished Oct 08 02:09:48 PM PDT 23
Peak memory 217400 kb
Host smart-158d1b4a-8f96-492e-b89b-3049c6bec2e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794215946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2794215946
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4230886747
Short name T104
Test name
Test status
Simulation time 1646332871 ps
CPU time 16.71 seconds
Started Oct 08 02:06:30 PM PDT 23
Finished Oct 08 02:06:47 PM PDT 23
Peak memory 218800 kb
Host smart-40f983d5-70fc-410c-9321-0a112e9523af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230886747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4230886747
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3111122060
Short name T471
Test name
Test status
Simulation time 3912135720 ps
CPU time 47.77 seconds
Started Oct 08 02:08:06 PM PDT 23
Finished Oct 08 02:08:54 PM PDT 23
Peak memory 211896 kb
Host smart-36decb97-938b-4987-8aaa-3eb7e2b804bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111122060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3111122060
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1542521280
Short name T91
Test name
Test status
Simulation time 10027790105 ps
CPU time 15.83 seconds
Started Oct 08 02:08:51 PM PDT 23
Finished Oct 08 02:09:07 PM PDT 23
Peak memory 210824 kb
Host smart-50ffacca-0725-439c-94bd-e60c1effa58c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542521280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1542521280
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1888482087
Short name T141
Test name
Test status
Simulation time 2936777941 ps
CPU time 9.51 seconds
Started Oct 08 01:59:59 PM PDT 23
Finished Oct 08 02:00:09 PM PDT 23
Peak memory 210800 kb
Host smart-db841178-34d8-4136-8db2-37fa7331f0a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888482087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1888482087
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3635437598
Short name T146
Test name
Test status
Simulation time 1823781856 ps
CPU time 15.42 seconds
Started Oct 08 01:57:36 PM PDT 23
Finished Oct 08 01:57:51 PM PDT 23
Peak memory 217744 kb
Host smart-007d6eab-6f73-488c-a5c0-c34c9cb87e6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635437598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3635437598
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3375784532
Short name T74
Test name
Test status
Simulation time 268003276 ps
CPU time 6.85 seconds
Started Oct 08 02:01:45 PM PDT 23
Finished Oct 08 02:01:52 PM PDT 23
Peak memory 213440 kb
Host smart-41a49a2f-803f-4e4d-b175-1ab819164919
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375784532 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3375784532
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2893759766
Short name T87
Test name
Test status
Simulation time 1877436706 ps
CPU time 13.42 seconds
Started Oct 08 02:04:35 PM PDT 23
Finished Oct 08 02:04:48 PM PDT 23
Peak memory 210636 kb
Host smart-d185d36d-7de0-4634-a39b-f97014dfb90d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893759766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2893759766
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3419050489
Short name T120
Test name
Test status
Simulation time 6032299046 ps
CPU time 14.07 seconds
Started Oct 08 02:02:39 PM PDT 23
Finished Oct 08 02:02:53 PM PDT 23
Peak memory 210700 kb
Host smart-6d4285ff-7189-475d-8be7-0e522f2d05ac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419050489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3419050489
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3754863177
Short name T456
Test name
Test status
Simulation time 596215498 ps
CPU time 5.27 seconds
Started Oct 08 02:03:55 PM PDT 23
Finished Oct 08 02:04:01 PM PDT 23
Peak memory 208588 kb
Host smart-b14bb9b3-365d-4568-a7a9-c5abeb80cffa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754863177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3754863177
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2867893101
Short name T470
Test name
Test status
Simulation time 4411835596 ps
CPU time 54.1 seconds
Started Oct 08 02:09:13 PM PDT 23
Finished Oct 08 02:10:07 PM PDT 23
Peak memory 210780 kb
Host smart-50c5ab2a-2350-4743-8f8e-35f741907228
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867893101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2867893101
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1114317605
Short name T472
Test name
Test status
Simulation time 2587414832 ps
CPU time 12.18 seconds
Started Oct 08 01:58:15 PM PDT 23
Finished Oct 08 01:58:27 PM PDT 23
Peak memory 210740 kb
Host smart-bdbc4afb-64f6-4d66-8c8c-20789ff0de58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114317605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1114317605
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.289841955
Short name T69
Test name
Test status
Simulation time 6545239803 ps
CPU time 16.28 seconds
Started Oct 08 02:04:36 PM PDT 23
Finished Oct 08 02:04:52 PM PDT 23
Peak memory 218864 kb
Host smart-a484db2a-ce02-4142-86e1-92571f5570f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289841955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.289841955
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.657963093
Short name T45
Test name
Test status
Simulation time 1838369008 ps
CPU time 81.07 seconds
Started Oct 08 02:03:55 PM PDT 23
Finished Oct 08 02:05:17 PM PDT 23
Peak memory 208692 kb
Host smart-6d68b731-543e-48be-a666-919079a35333
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657963093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.657963093
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3508991913
Short name T118
Test name
Test status
Simulation time 1397929055 ps
CPU time 7.16 seconds
Started Oct 08 02:03:55 PM PDT 23
Finished Oct 08 02:04:03 PM PDT 23
Peak memory 211052 kb
Host smart-61eeb6a0-d302-427c-92b3-ba9b039dafaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508991913 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3508991913
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.929666021
Short name T94
Test name
Test status
Simulation time 106550866 ps
CPU time 4.36 seconds
Started Oct 08 02:08:49 PM PDT 23
Finished Oct 08 02:08:54 PM PDT 23
Peak memory 210884 kb
Host smart-0dfb9b17-babf-490d-af52-c888c03301eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929666021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.929666021
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2600618872
Short name T467
Test name
Test status
Simulation time 905836791 ps
CPU time 7.23 seconds
Started Oct 08 01:59:04 PM PDT 23
Finished Oct 08 01:59:12 PM PDT 23
Peak memory 216156 kb
Host smart-f9255361-79f9-46b7-9e67-e16abe12b254
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600618872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2600618872
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1320025880
Short name T143
Test name
Test status
Simulation time 1435832560 ps
CPU time 17.32 seconds
Started Oct 08 02:09:15 PM PDT 23
Finished Oct 08 02:09:32 PM PDT 23
Peak memory 213588 kb
Host smart-5caf4cd8-4d03-482e-b88f-62575cea86b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320025880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1320025880
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1942762250
Short name T106
Test name
Test status
Simulation time 1700770387 ps
CPU time 77.87 seconds
Started Oct 08 02:02:48 PM PDT 23
Finished Oct 08 02:04:06 PM PDT 23
Peak memory 219036 kb
Host smart-c6c0f9c5-d6ab-4c1a-9b4c-f1fc0eca199c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942762250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1942762250
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1184726518
Short name T450
Test name
Test status
Simulation time 3761164467 ps
CPU time 12.33 seconds
Started Oct 08 02:02:18 PM PDT 23
Finished Oct 08 02:02:31 PM PDT 23
Peak memory 214180 kb
Host smart-98d35708-bd46-4ac0-afb4-21648f5557d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184726518 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1184726518
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.252585565
Short name T451
Test name
Test status
Simulation time 669684390 ps
CPU time 5.74 seconds
Started Oct 08 02:05:10 PM PDT 23
Finished Oct 08 02:05:16 PM PDT 23
Peak memory 210656 kb
Host smart-953c8772-0397-42a0-aa85-ee7fc3a11e02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252585565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.252585565
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3152413110
Short name T473
Test name
Test status
Simulation time 29168110194 ps
CPU time 152.59 seconds
Started Oct 08 02:02:12 PM PDT 23
Finished Oct 08 02:04:45 PM PDT 23
Peak memory 218784 kb
Host smart-befba025-87ff-4447-958a-dd088712203d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152413110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3152413110
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3659076339
Short name T78
Test name
Test status
Simulation time 87347186 ps
CPU time 4.42 seconds
Started Oct 08 02:03:27 PM PDT 23
Finished Oct 08 02:03:31 PM PDT 23
Peak memory 210660 kb
Host smart-0c8b05cd-5d1d-44e6-bc02-8b4e012c907f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659076339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3659076339
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2004470444
Short name T469
Test name
Test status
Simulation time 1871347024 ps
CPU time 9.31 seconds
Started Oct 08 01:56:54 PM PDT 23
Finished Oct 08 01:57:04 PM PDT 23
Peak memory 218920 kb
Host smart-ce10d538-f0f0-4dff-9389-a97fe4bc2ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004470444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2004470444
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2004046373
Short name T114
Test name
Test status
Simulation time 3198671239 ps
CPU time 43.03 seconds
Started Oct 08 02:04:10 PM PDT 23
Finished Oct 08 02:04:54 PM PDT 23
Peak memory 212040 kb
Host smart-d0c072ce-6e3c-42a8-b9e2-1f65e8b60b35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004046373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2004046373
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3357705976
Short name T449
Test name
Test status
Simulation time 272039429 ps
CPU time 5.7 seconds
Started Oct 08 02:04:59 PM PDT 23
Finished Oct 08 02:05:04 PM PDT 23
Peak memory 214012 kb
Host smart-56155ba1-dc43-43cc-bd77-a4d08d2f5d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357705976 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3357705976
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2493731074
Short name T36
Test name
Test status
Simulation time 1183286691 ps
CPU time 4.27 seconds
Started Oct 08 02:10:35 PM PDT 23
Finished Oct 08 02:10:39 PM PDT 23
Peak memory 210648 kb
Host smart-37037b6f-fc08-424c-8f04-0520936c46e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493731074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2493731074
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1869179417
Short name T81
Test name
Test status
Simulation time 10886115531 ps
CPU time 114.23 seconds
Started Oct 08 01:59:02 PM PDT 23
Finished Oct 08 02:00:56 PM PDT 23
Peak memory 218604 kb
Host smart-84d0ddf2-c21e-4e26-92ad-c52f9169f8ab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869179417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1869179417
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3206740377
Short name T126
Test name
Test status
Simulation time 360552714 ps
CPU time 6.49 seconds
Started Oct 08 02:08:51 PM PDT 23
Finished Oct 08 02:08:57 PM PDT 23
Peak memory 216740 kb
Host smart-c6cd0f70-c722-4e29-ae2d-ae9b33f3a845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206740377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3206740377
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3865676041
Short name T458
Test name
Test status
Simulation time 7915139560 ps
CPU time 16.81 seconds
Started Oct 08 02:03:55 PM PDT 23
Finished Oct 08 02:04:12 PM PDT 23
Peak memory 216952 kb
Host smart-2532b605-ccd7-4bd2-90fc-c86e2bfc2764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865676041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3865676041
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2591340213
Short name T131
Test name
Test status
Simulation time 865838788 ps
CPU time 42.7 seconds
Started Oct 08 02:03:55 PM PDT 23
Finished Oct 08 02:04:38 PM PDT 23
Peak memory 209980 kb
Host smart-921980c7-441a-462f-a8ca-a05f1fb5e9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591340213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2591340213
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.157606771
Short name T70
Test name
Test status
Simulation time 1041094317 ps
CPU time 10.56 seconds
Started Oct 08 02:04:58 PM PDT 23
Finished Oct 08 02:05:08 PM PDT 23
Peak memory 219088 kb
Host smart-9e4234f7-ac2b-49a5-a4a2-0853b9e81f2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157606771 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.157606771
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3610509152
Short name T148
Test name
Test status
Simulation time 4402664424 ps
CPU time 11.84 seconds
Started Oct 08 02:02:50 PM PDT 23
Finished Oct 08 02:03:02 PM PDT 23
Peak memory 210944 kb
Host smart-08d0ce43-d3db-4cd5-ba15-b083f5ca75d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610509152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3610509152
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.28745008
Short name T437
Test name
Test status
Simulation time 6920978718 ps
CPU time 15.7 seconds
Started Oct 08 02:03:28 PM PDT 23
Finished Oct 08 02:03:44 PM PDT 23
Peak memory 210700 kb
Host smart-d8d81ef8-402e-4b09-a0e2-c13a908998f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28745008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctr
l_same_csr_outstanding.28745008
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2214851702
Short name T464
Test name
Test status
Simulation time 2918044233 ps
CPU time 10.32 seconds
Started Oct 08 02:10:35 PM PDT 23
Finished Oct 08 02:10:45 PM PDT 23
Peak memory 218984 kb
Host smart-526ade17-9346-443b-af74-71a1deebc841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214851702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2214851702
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2955243377
Short name T68
Test name
Test status
Simulation time 11937790611 ps
CPU time 83.34 seconds
Started Oct 08 02:03:28 PM PDT 23
Finished Oct 08 02:04:52 PM PDT 23
Peak memory 211172 kb
Host smart-67c39f5f-e731-4bb6-a3c5-4a6f9da942b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955243377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2955243377
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3584104217
Short name T435
Test name
Test status
Simulation time 3223456537 ps
CPU time 16.07 seconds
Started Oct 08 02:08:41 PM PDT 23
Finished Oct 08 02:08:57 PM PDT 23
Peak memory 218972 kb
Host smart-90674211-9295-430b-81da-45560d196d05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584104217 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3584104217
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1399466177
Short name T124
Test name
Test status
Simulation time 689830943 ps
CPU time 5.43 seconds
Started Oct 08 01:59:03 PM PDT 23
Finished Oct 08 01:59:08 PM PDT 23
Peak memory 210652 kb
Host smart-83d8f415-e11d-4fec-8954-ce44b5898b68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399466177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1399466177
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.707001174
Short name T455
Test name
Test status
Simulation time 1024884310 ps
CPU time 51.92 seconds
Started Oct 08 02:04:59 PM PDT 23
Finished Oct 08 02:05:51 PM PDT 23
Peak memory 210612 kb
Host smart-87075f75-e92a-423f-b618-e87fa85f3b5e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707001174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.707001174
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2590829034
Short name T480
Test name
Test status
Simulation time 2332194608 ps
CPU time 11.36 seconds
Started Oct 08 02:06:29 PM PDT 23
Finished Oct 08 02:06:40 PM PDT 23
Peak memory 210664 kb
Host smart-d93a4cb4-8914-4eb6-84ed-c56f13d22ecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590829034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2590829034
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1403985533
Short name T103
Test name
Test status
Simulation time 2307836373 ps
CPU time 15.31 seconds
Started Oct 08 01:57:07 PM PDT 23
Finished Oct 08 01:57:22 PM PDT 23
Peak memory 218964 kb
Host smart-cbe9e840-8341-450b-b3ac-55d83bf58a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403985533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1403985533
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2494032702
Short name T112
Test name
Test status
Simulation time 888032369 ps
CPU time 80.29 seconds
Started Oct 08 02:04:59 PM PDT 23
Finished Oct 08 02:06:19 PM PDT 23
Peak memory 210756 kb
Host smart-ceee919e-0895-4126-b795-194b843231bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494032702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2494032702
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1808479115
Short name T208
Test name
Test status
Simulation time 2368843688 ps
CPU time 5.51 seconds
Started Oct 08 03:47:57 PM PDT 23
Finished Oct 08 03:48:03 PM PDT 23
Peak memory 211148 kb
Host smart-a7267a9f-3f22-48b4-9a6e-b968423189d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808479115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1808479115
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2320127890
Short name T327
Test name
Test status
Simulation time 3442070124 ps
CPU time 123.97 seconds
Started Oct 08 03:47:57 PM PDT 23
Finished Oct 08 03:50:01 PM PDT 23
Peak memory 224380 kb
Host smart-e8e7d033-af13-44b9-a336-6bf3cc8ec900
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320127890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2320127890
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.799452295
Short name T224
Test name
Test status
Simulation time 2746496503 ps
CPU time 10.13 seconds
Started Oct 08 03:55:49 PM PDT 23
Finished Oct 08 03:55:59 PM PDT 23
Peak memory 211180 kb
Host smart-3f98a989-dcad-4208-bfdd-4e5f1459592b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=799452295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.799452295
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4232383470
Short name T242
Test name
Test status
Simulation time 3279533111 ps
CPU time 30.08 seconds
Started Oct 08 03:53:08 PM PDT 23
Finished Oct 08 03:53:39 PM PDT 23
Peak memory 212276 kb
Host smart-ba889bf8-362d-4cb4-8019-9487c2c10d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232383470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4232383470
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2708209130
Short name T387
Test name
Test status
Simulation time 902870879 ps
CPU time 22.79 seconds
Started Oct 08 03:45:16 PM PDT 23
Finished Oct 08 03:45:39 PM PDT 23
Peak memory 215276 kb
Host smart-8d611f28-6a61-4e06-8a54-13c67645f3cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708209130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2708209130
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1722454565
Short name T213
Test name
Test status
Simulation time 55266845943 ps
CPU time 7999.66 seconds
Started Oct 08 03:49:11 PM PDT 23
Finished Oct 08 06:02:33 PM PDT 23
Peak memory 236384 kb
Host smart-f8a98079-0f4b-4d4c-bea6-2cd67fb862d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722454565 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1722454565
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.518283638
Short name T201
Test name
Test status
Simulation time 7640860797 ps
CPU time 14.08 seconds
Started Oct 08 03:44:42 PM PDT 23
Finished Oct 08 03:44:57 PM PDT 23
Peak memory 210772 kb
Host smart-5a91ca0a-0be5-438c-b1db-7b18971387c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518283638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.518283638
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3878019865
Short name T346
Test name
Test status
Simulation time 218441031297 ps
CPU time 370.55 seconds
Started Oct 08 03:42:46 PM PDT 23
Finished Oct 08 03:48:57 PM PDT 23
Peak memory 236672 kb
Host smart-54948dfc-6b68-4b8f-b100-57867183382d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878019865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3878019865
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.754907464
Short name T264
Test name
Test status
Simulation time 4083507786 ps
CPU time 33.92 seconds
Started Oct 08 03:47:04 PM PDT 23
Finished Oct 08 03:47:39 PM PDT 23
Peak memory 211272 kb
Host smart-bb5f265f-5382-47cc-8ced-3e1b6d261401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754907464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.754907464
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.126125723
Short name T310
Test name
Test status
Simulation time 1110972120 ps
CPU time 12.22 seconds
Started Oct 08 03:50:29 PM PDT 23
Finished Oct 08 03:50:41 PM PDT 23
Peak memory 211092 kb
Host smart-fac74140-2309-44ac-a7b8-932154482a94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126125723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.126125723
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2922705107
Short name T42
Test name
Test status
Simulation time 4936945156 ps
CPU time 60.31 seconds
Started Oct 08 03:43:58 PM PDT 23
Finished Oct 08 03:44:58 PM PDT 23
Peak memory 237560 kb
Host smart-d808d8ef-1476-4a5d-8821-68715047050b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922705107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2922705107
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4050451630
Short name T278
Test name
Test status
Simulation time 3002719630 ps
CPU time 35.49 seconds
Started Oct 08 03:42:45 PM PDT 23
Finished Oct 08 03:43:22 PM PDT 23
Peak memory 212636 kb
Host smart-d31ff810-28cf-4bf0-92a2-ede7ad48b8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050451630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4050451630
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2982593427
Short name T57
Test name
Test status
Simulation time 596966736 ps
CPU time 8.9 seconds
Started Oct 08 03:42:47 PM PDT 23
Finished Oct 08 03:42:56 PM PDT 23
Peak memory 211344 kb
Host smart-52211747-c79b-44b2-b7f9-0281c554854d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982593427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2982593427
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2453915801
Short name T211
Test name
Test status
Simulation time 59278125439 ps
CPU time 290.07 seconds
Started Oct 08 03:56:27 PM PDT 23
Finished Oct 08 04:01:17 PM PDT 23
Peak memory 236680 kb
Host smart-efad95a2-45dc-4d95-90d0-42472d699a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453915801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2453915801
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3182392806
Short name T391
Test name
Test status
Simulation time 341739092 ps
CPU time 9.74 seconds
Started Oct 08 03:44:34 PM PDT 23
Finished Oct 08 03:44:44 PM PDT 23
Peak memory 211412 kb
Host smart-1b151807-671c-481a-b401-e9da11277f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182392806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3182392806
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.250709082
Short name T332
Test name
Test status
Simulation time 544979248 ps
CPU time 6.26 seconds
Started Oct 08 03:45:28 PM PDT 23
Finished Oct 08 03:45:35 PM PDT 23
Peak memory 211000 kb
Host smart-73b6a585-2db3-4844-9216-53ccd5863bd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250709082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.250709082
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1101168477
Short name T31
Test name
Test status
Simulation time 19478908838 ps
CPU time 36.56 seconds
Started Oct 08 03:45:26 PM PDT 23
Finished Oct 08 03:46:03 PM PDT 23
Peak memory 213508 kb
Host smart-7e02fe0f-7041-4ec3-bae4-7fa70eadbf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101168477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1101168477
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.694434456
Short name T298
Test name
Test status
Simulation time 4131854070 ps
CPU time 43.37 seconds
Started Oct 08 03:46:43 PM PDT 23
Finished Oct 08 03:47:26 PM PDT 23
Peak memory 215732 kb
Host smart-d502c549-31f2-4499-9923-ebaad3f5b802
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694434456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.694434456
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.458663662
Short name T389
Test name
Test status
Simulation time 6655189045 ps
CPU time 13.72 seconds
Started Oct 08 03:54:17 PM PDT 23
Finished Oct 08 03:54:32 PM PDT 23
Peak memory 209124 kb
Host smart-605ea688-a0c7-4e7c-b7bc-1cc1920c9f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458663662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.458663662
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1323020956
Short name T202
Test name
Test status
Simulation time 28183932572 ps
CPU time 187.87 seconds
Started Oct 08 03:49:35 PM PDT 23
Finished Oct 08 03:52:43 PM PDT 23
Peak memory 224464 kb
Host smart-627fe7cb-e30b-4938-9b70-b1bf09dabc78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323020956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1323020956
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1709087334
Short name T56
Test name
Test status
Simulation time 305724446 ps
CPU time 5.62 seconds
Started Oct 08 03:54:17 PM PDT 23
Finished Oct 08 03:54:23 PM PDT 23
Peak memory 208992 kb
Host smart-897f5a90-ecf3-4615-92d3-73d4317c6923
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709087334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1709087334
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1269786598
Short name T159
Test name
Test status
Simulation time 8737261537 ps
CPU time 29.1 seconds
Started Oct 08 03:44:35 PM PDT 23
Finished Oct 08 03:45:04 PM PDT 23
Peak memory 213368 kb
Host smart-54fd742b-d66f-4e94-914d-c919c478f771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269786598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1269786598
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.581371001
Short name T375
Test name
Test status
Simulation time 4129979438 ps
CPU time 37.34 seconds
Started Oct 08 03:56:00 PM PDT 23
Finished Oct 08 03:56:37 PM PDT 23
Peak memory 212920 kb
Host smart-dcffbc2a-2540-4e3b-a2fa-76d04793b8f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581371001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.581371001
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4165207463
Short name T280
Test name
Test status
Simulation time 1062609908 ps
CPU time 10.51 seconds
Started Oct 08 03:53:26 PM PDT 23
Finished Oct 08 03:53:37 PM PDT 23
Peak memory 211080 kb
Host smart-48993d73-30a2-46aa-a857-46ea1984e363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165207463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4165207463
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1544401331
Short name T268
Test name
Test status
Simulation time 21908470226 ps
CPU time 224.09 seconds
Started Oct 08 03:45:49 PM PDT 23
Finished Oct 08 03:49:33 PM PDT 23
Peak memory 233368 kb
Host smart-88b36e1d-de09-4e57-ac3c-9b91ee6f40f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544401331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1544401331
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1855554453
Short name T249
Test name
Test status
Simulation time 3217325151 ps
CPU time 28.05 seconds
Started Oct 08 03:43:07 PM PDT 23
Finished Oct 08 03:43:36 PM PDT 23
Peak memory 211388 kb
Host smart-c5082e26-e98e-4973-9673-85404cc9a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855554453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1855554453
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.616365283
Short name T263
Test name
Test status
Simulation time 98746281 ps
CPU time 5.69 seconds
Started Oct 08 03:43:08 PM PDT 23
Finished Oct 08 03:43:14 PM PDT 23
Peak memory 210992 kb
Host smart-104e0b40-8957-45e8-a262-47786f1ae398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616365283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.616365283
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1841834647
Short name T166
Test name
Test status
Simulation time 2362080405 ps
CPU time 29.89 seconds
Started Oct 08 03:48:04 PM PDT 23
Finished Oct 08 03:48:35 PM PDT 23
Peak memory 212796 kb
Host smart-e89861f9-917d-483c-bd1e-05a1407e837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841834647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1841834647
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3570578042
Short name T2
Test name
Test status
Simulation time 1175960310 ps
CPU time 17.75 seconds
Started Oct 08 03:44:50 PM PDT 23
Finished Oct 08 03:45:08 PM PDT 23
Peak memory 215648 kb
Host smart-e53ab29b-08f5-4a7c-ac78-209f07f624f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570578042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3570578042
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1284407076
Short name T285
Test name
Test status
Simulation time 409811955 ps
CPU time 6.92 seconds
Started Oct 08 03:50:19 PM PDT 23
Finished Oct 08 03:50:26 PM PDT 23
Peak memory 210952 kb
Host smart-daab2032-4ce5-452f-85f8-70cee0abad63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284407076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1284407076
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3933064560
Short name T314
Test name
Test status
Simulation time 34438663301 ps
CPU time 352.28 seconds
Started Oct 08 03:43:22 PM PDT 23
Finished Oct 08 03:49:14 PM PDT 23
Peak memory 236788 kb
Host smart-ec7c67e4-f8b7-4686-8408-ca55ca7a7e3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933064560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3933064560
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4252089031
Short name T367
Test name
Test status
Simulation time 9901585239 ps
CPU time 23.88 seconds
Started Oct 08 03:53:28 PM PDT 23
Finished Oct 08 03:53:52 PM PDT 23
Peak memory 211768 kb
Host smart-eed3be9e-ba68-402f-8f92-740a3afab8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252089031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4252089031
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3533758765
Short name T228
Test name
Test status
Simulation time 2077762003 ps
CPU time 11.5 seconds
Started Oct 08 03:43:25 PM PDT 23
Finished Oct 08 03:43:37 PM PDT 23
Peak memory 210872 kb
Host smart-3ed41605-1f66-4a4a-873b-494f0550ffaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533758765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3533758765
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2300295554
Short name T316
Test name
Test status
Simulation time 760060859 ps
CPU time 10.44 seconds
Started Oct 08 03:48:24 PM PDT 23
Finished Oct 08 03:48:35 PM PDT 23
Peak memory 212728 kb
Host smart-c7163103-437e-45b7-ad06-794d2221f420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300295554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2300295554
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3274238286
Short name T186
Test name
Test status
Simulation time 6393181614 ps
CPU time 31.16 seconds
Started Oct 08 03:55:58 PM PDT 23
Finished Oct 08 03:56:29 PM PDT 23
Peak memory 216240 kb
Host smart-9f00b6bf-9a53-41b6-9290-f214595498c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274238286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3274238286
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3512808505
Short name T27
Test name
Test status
Simulation time 46534124227 ps
CPU time 1935.55 seconds
Started Oct 08 03:53:29 PM PDT 23
Finished Oct 08 04:25:45 PM PDT 23
Peak memory 235780 kb
Host smart-96242cd5-1399-49bb-a85d-c9da0ff947af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512808505 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3512808505
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1354709777
Short name T43
Test name
Test status
Simulation time 89061638 ps
CPU time 4.49 seconds
Started Oct 08 03:44:15 PM PDT 23
Finished Oct 08 03:44:19 PM PDT 23
Peak memory 211008 kb
Host smart-d086dcfb-5250-4a94-996e-68b6f909bfc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354709777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1354709777
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2062233606
Short name T19
Test name
Test status
Simulation time 5576508643 ps
CPU time 82.98 seconds
Started Oct 08 03:46:32 PM PDT 23
Finished Oct 08 03:47:55 PM PDT 23
Peak memory 237728 kb
Host smart-02f867ca-a9df-4220-a5d1-76ccd4140322
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062233606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2062233606
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.214749233
Short name T399
Test name
Test status
Simulation time 24137470888 ps
CPU time 29.33 seconds
Started Oct 08 03:44:03 PM PDT 23
Finished Oct 08 03:44:33 PM PDT 23
Peak memory 212388 kb
Host smart-bb3b3ccb-36b4-42ab-82ca-218ec71f79d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214749233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.214749233
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1645845576
Short name T174
Test name
Test status
Simulation time 3736141693 ps
CPU time 12.35 seconds
Started Oct 08 03:44:26 PM PDT 23
Finished Oct 08 03:44:39 PM PDT 23
Peak memory 211100 kb
Host smart-cf7ce435-dec7-4f67-8533-3a90ada30ad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645845576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1645845576
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3789795713
Short name T163
Test name
Test status
Simulation time 257845548 ps
CPU time 10.77 seconds
Started Oct 08 03:51:16 PM PDT 23
Finished Oct 08 03:51:27 PM PDT 23
Peak memory 212824 kb
Host smart-949d0260-27d5-4f81-9c24-c4ab87a8700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789795713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3789795713
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.53998544
Short name T357
Test name
Test status
Simulation time 10640932962 ps
CPU time 112.31 seconds
Started Oct 08 03:44:03 PM PDT 23
Finished Oct 08 03:45:56 PM PDT 23
Peak memory 216684 kb
Host smart-e6a58cfe-7f22-491a-8cb3-a9c4ff86626e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53998544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.rom_ctrl_stress_all.53998544
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2820595878
Short name T374
Test name
Test status
Simulation time 31449981455 ps
CPU time 1834.57 seconds
Started Oct 08 03:46:01 PM PDT 23
Finished Oct 08 04:16:36 PM PDT 23
Peak memory 235732 kb
Host smart-0a830bbd-58c8-4433-a601-b9b6e661ac57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820595878 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2820595878
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.808352155
Short name T154
Test name
Test status
Simulation time 4708987290 ps
CPU time 10.01 seconds
Started Oct 08 03:45:30 PM PDT 23
Finished Oct 08 03:45:40 PM PDT 23
Peak memory 211160 kb
Host smart-443b7666-0cbf-4cfa-a5bb-5183dd651080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808352155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.808352155
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.94194880
Short name T20
Test name
Test status
Simulation time 19338683401 ps
CPU time 172.53 seconds
Started Oct 08 03:45:30 PM PDT 23
Finished Oct 08 03:48:23 PM PDT 23
Peak memory 236588 kb
Host smart-61308242-11f7-4aa6-9a9a-ae9292be4353
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94194880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_co
rrupt_sig_fatal_chk.94194880
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2955298419
Short name T270
Test name
Test status
Simulation time 17079239870 ps
CPU time 36.39 seconds
Started Oct 08 03:48:44 PM PDT 23
Finished Oct 08 03:49:21 PM PDT 23
Peak memory 211564 kb
Host smart-f12fe2cc-f313-49f0-918f-5c0ab549697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955298419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2955298419
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2900096287
Short name T318
Test name
Test status
Simulation time 1543570238 ps
CPU time 6.11 seconds
Started Oct 08 03:44:13 PM PDT 23
Finished Oct 08 03:44:20 PM PDT 23
Peak memory 211076 kb
Host smart-84a9b8b7-aa0f-43e5-8a2b-f7059fca27cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900096287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2900096287
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2566690138
Short name T225
Test name
Test status
Simulation time 3460515733 ps
CPU time 34.45 seconds
Started Oct 08 03:45:53 PM PDT 23
Finished Oct 08 03:46:28 PM PDT 23
Peak memory 212728 kb
Host smart-3a48f4bf-020f-4bc5-9518-4a30020d686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566690138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2566690138
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3383459144
Short name T25
Test name
Test status
Simulation time 9284592808 ps
CPU time 77.77 seconds
Started Oct 08 03:43:55 PM PDT 23
Finished Oct 08 03:45:13 PM PDT 23
Peak memory 216512 kb
Host smart-a51a5528-c7e0-4451-953d-003a2466c328
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383459144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3383459144
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3319480654
Short name T191
Test name
Test status
Simulation time 13926388064 ps
CPU time 508.59 seconds
Started Oct 08 03:56:33 PM PDT 23
Finished Oct 08 04:05:02 PM PDT 23
Peak memory 235484 kb
Host smart-8a72b293-b122-4bcf-9d74-ef72faafeb9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319480654 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3319480654
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1415320815
Short name T65
Test name
Test status
Simulation time 1536123059 ps
CPU time 13.77 seconds
Started Oct 08 03:48:43 PM PDT 23
Finished Oct 08 03:48:57 PM PDT 23
Peak memory 211056 kb
Host smart-2769d063-890f-4742-889d-c97a657188dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415320815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1415320815
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.624987542
Short name T247
Test name
Test status
Simulation time 139409106664 ps
CPU time 318.92 seconds
Started Oct 08 03:44:04 PM PDT 23
Finished Oct 08 03:49:24 PM PDT 23
Peak memory 227900 kb
Host smart-b1f94a7d-b6d2-46dc-818a-2a4a06f0f0a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624987542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.624987542
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3413923747
Short name T244
Test name
Test status
Simulation time 17179507452 ps
CPU time 21.78 seconds
Started Oct 08 03:44:37 PM PDT 23
Finished Oct 08 03:44:59 PM PDT 23
Peak memory 211468 kb
Host smart-a852de06-58d5-42a5-b99a-d7dd4eb404cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413923747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3413923747
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2184319212
Short name T330
Test name
Test status
Simulation time 2099331107 ps
CPU time 12.14 seconds
Started Oct 08 03:56:14 PM PDT 23
Finished Oct 08 03:56:26 PM PDT 23
Peak memory 210996 kb
Host smart-388f0edb-0d28-4a60-98f0-f5fbd635b120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184319212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2184319212
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1338267353
Short name T207
Test name
Test status
Simulation time 3304270616 ps
CPU time 23.91 seconds
Started Oct 08 03:46:34 PM PDT 23
Finished Oct 08 03:46:58 PM PDT 23
Peak memory 212120 kb
Host smart-cb81e315-ed77-4a55-b357-a7c22cd3eb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338267353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1338267353
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1386893123
Short name T361
Test name
Test status
Simulation time 17606139879 ps
CPU time 38.55 seconds
Started Oct 08 03:43:36 PM PDT 23
Finished Oct 08 03:44:15 PM PDT 23
Peak memory 213712 kb
Host smart-dfd4954d-5230-4fa6-afd4-4b84638aed81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386893123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1386893123
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2501969784
Short name T403
Test name
Test status
Simulation time 70707973350 ps
CPU time 1117.55 seconds
Started Oct 08 03:48:50 PM PDT 23
Finished Oct 08 04:07:28 PM PDT 23
Peak memory 227612 kb
Host smart-7bbdc154-ebfe-43af-b8d1-6c22057744df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501969784 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2501969784
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.632561637
Short name T378
Test name
Test status
Simulation time 1118418601 ps
CPU time 11.21 seconds
Started Oct 08 03:56:18 PM PDT 23
Finished Oct 08 03:56:29 PM PDT 23
Peak memory 211016 kb
Host smart-a29727d9-8fb0-4f78-a23b-e8f3ce947cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632561637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.632561637
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1496054343
Short name T420
Test name
Test status
Simulation time 37214844792 ps
CPU time 408.75 seconds
Started Oct 08 03:44:05 PM PDT 23
Finished Oct 08 03:50:54 PM PDT 23
Peak memory 237644 kb
Host smart-e4e75915-6696-4f60-82d0-798e574aa31f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496054343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1496054343
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3839719867
Short name T353
Test name
Test status
Simulation time 175455490 ps
CPU time 9.87 seconds
Started Oct 08 03:44:06 PM PDT 23
Finished Oct 08 03:44:16 PM PDT 23
Peak memory 211108 kb
Host smart-b159e8d8-bda6-4ba0-9631-10edfc316998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839719867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3839719867
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3701519726
Short name T341
Test name
Test status
Simulation time 1558864891 ps
CPU time 13.97 seconds
Started Oct 08 03:45:31 PM PDT 23
Finished Oct 08 03:45:45 PM PDT 23
Peak memory 211092 kb
Host smart-200b0240-7482-4b63-b0df-73fb440e410e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701519726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3701519726
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.302148682
Short name T359
Test name
Test status
Simulation time 9427880031 ps
CPU time 40.77 seconds
Started Oct 08 03:46:33 PM PDT 23
Finished Oct 08 03:47:14 PM PDT 23
Peak memory 216312 kb
Host smart-6a7be5d7-a42b-47c8-bb39-29be9844cc7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302148682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.302148682
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2919274068
Short name T259
Test name
Test status
Simulation time 37731947671 ps
CPU time 868.07 seconds
Started Oct 08 03:46:01 PM PDT 23
Finished Oct 08 04:00:30 PM PDT 23
Peak memory 235744 kb
Host smart-b52f7a86-8190-4f22-8725-912074841d59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919274068 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2919274068
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2465692925
Short name T317
Test name
Test status
Simulation time 4097742822 ps
CPU time 15.63 seconds
Started Oct 08 03:43:24 PM PDT 23
Finished Oct 08 03:43:40 PM PDT 23
Peak memory 211164 kb
Host smart-ca41bbde-4bfb-439a-a484-2e720f181a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465692925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2465692925
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2846747936
Short name T196
Test name
Test status
Simulation time 93555851650 ps
CPU time 253.16 seconds
Started Oct 08 03:46:34 PM PDT 23
Finished Oct 08 03:50:47 PM PDT 23
Peak memory 237096 kb
Host smart-4cdf45f0-92e7-46b1-9fb6-74ec504f930d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846747936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2846747936
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2502683720
Short name T149
Test name
Test status
Simulation time 2341748262 ps
CPU time 23.82 seconds
Started Oct 08 03:43:24 PM PDT 23
Finished Oct 08 03:43:48 PM PDT 23
Peak memory 211248 kb
Host smart-b063da97-e7c7-456c-a366-61c523ec2ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502683720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2502683720
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1963192633
Short name T329
Test name
Test status
Simulation time 817855436 ps
CPU time 5.55 seconds
Started Oct 08 03:43:52 PM PDT 23
Finished Oct 08 03:43:57 PM PDT 23
Peak memory 211004 kb
Host smart-3199ff22-a4e5-415b-8a61-34648a06a9d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1963192633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1963192633
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4217889633
Short name T371
Test name
Test status
Simulation time 6466840289 ps
CPU time 33.38 seconds
Started Oct 08 03:45:31 PM PDT 23
Finished Oct 08 03:46:05 PM PDT 23
Peak memory 213784 kb
Host smart-3b1a7718-2e94-4caa-8a0f-cfcd51af06c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217889633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4217889633
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1036431814
Short name T408
Test name
Test status
Simulation time 5704228700 ps
CPU time 55.94 seconds
Started Oct 08 03:46:35 PM PDT 23
Finished Oct 08 03:47:31 PM PDT 23
Peak memory 216220 kb
Host smart-0d06a217-9e97-45bb-a18c-72f5045cd4a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036431814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1036431814
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1573200322
Short name T170
Test name
Test status
Simulation time 135825835572 ps
CPU time 2427.39 seconds
Started Oct 08 03:51:29 PM PDT 23
Finished Oct 08 04:31:58 PM PDT 23
Peak memory 235796 kb
Host smart-4f8dce0c-69e3-45cf-95a0-ca17b341001a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573200322 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1573200322
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3128176808
Short name T248
Test name
Test status
Simulation time 505281012 ps
CPU time 7.69 seconds
Started Oct 08 03:46:01 PM PDT 23
Finished Oct 08 03:46:09 PM PDT 23
Peak memory 211008 kb
Host smart-d13058b3-7211-4ddd-ac36-2f9e6b4008c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128176808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3128176808
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.541628331
Short name T364
Test name
Test status
Simulation time 113807838694 ps
CPU time 319.13 seconds
Started Oct 08 03:43:54 PM PDT 23
Finished Oct 08 03:49:14 PM PDT 23
Peak memory 237604 kb
Host smart-0f3d7e78-5c32-48a5-95fe-dfc52a3733d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541628331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.541628331
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2882823253
Short name T425
Test name
Test status
Simulation time 356175369 ps
CPU time 9.88 seconds
Started Oct 08 03:53:40 PM PDT 23
Finished Oct 08 03:53:51 PM PDT 23
Peak memory 211148 kb
Host smart-f15a8f6b-7a54-401c-afc8-176e35a277ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882823253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2882823253
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.135907569
Short name T164
Test name
Test status
Simulation time 1161563239 ps
CPU time 12.95 seconds
Started Oct 08 03:48:46 PM PDT 23
Finished Oct 08 03:48:59 PM PDT 23
Peak memory 211060 kb
Host smart-a803aff0-834e-467a-8ac2-a4f40e5e55a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135907569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.135907569
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.393870723
Short name T322
Test name
Test status
Simulation time 904209949 ps
CPU time 10.1 seconds
Started Oct 08 03:48:50 PM PDT 23
Finished Oct 08 03:49:00 PM PDT 23
Peak memory 212420 kb
Host smart-9a90f4d0-470b-4d5a-9297-de53e3805ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393870723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.393870723
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3441962824
Short name T303
Test name
Test status
Simulation time 6412332114 ps
CPU time 66.12 seconds
Started Oct 08 03:46:13 PM PDT 23
Finished Oct 08 03:47:20 PM PDT 23
Peak memory 216372 kb
Host smart-9ae04e8d-e0bd-467a-adc7-e1c83304b1cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441962824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3441962824
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.4149666788
Short name T277
Test name
Test status
Simulation time 28730567358 ps
CPU time 2054.83 seconds
Started Oct 08 03:47:50 PM PDT 23
Finished Oct 08 04:22:06 PM PDT 23
Peak memory 234096 kb
Host smart-ea51893c-386a-48a0-ae59-a495febcaba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149666788 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.4149666788
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.490719088
Short name T252
Test name
Test status
Simulation time 11465430930 ps
CPU time 14.56 seconds
Started Oct 08 03:50:54 PM PDT 23
Finished Oct 08 03:51:08 PM PDT 23
Peak memory 211192 kb
Host smart-ba515403-2802-4ac0-bdfb-160ee2c41b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490719088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.490719088
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3091262590
Short name T16
Test name
Test status
Simulation time 30149156301 ps
CPU time 332.82 seconds
Started Oct 08 03:52:42 PM PDT 23
Finished Oct 08 03:58:16 PM PDT 23
Peak memory 233620 kb
Host smart-4f1be37e-255f-46dc-8744-d888a7f7794f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091262590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3091262590
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3015547008
Short name T386
Test name
Test status
Simulation time 11740999850 ps
CPU time 32.26 seconds
Started Oct 08 03:44:53 PM PDT 23
Finished Oct 08 03:45:25 PM PDT 23
Peak memory 211360 kb
Host smart-d013b36d-f593-4bde-8c57-12cf903214e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015547008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3015547008
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.282377651
Short name T238
Test name
Test status
Simulation time 101795689 ps
CPU time 5.62 seconds
Started Oct 08 03:44:37 PM PDT 23
Finished Oct 08 03:44:43 PM PDT 23
Peak memory 209092 kb
Host smart-dd998023-26f2-467f-9db9-f369c995a5e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282377651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.282377651
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.754219478
Short name T41
Test name
Test status
Simulation time 1296160200 ps
CPU time 59.49 seconds
Started Oct 08 03:44:54 PM PDT 23
Finished Oct 08 03:45:54 PM PDT 23
Peak memory 236956 kb
Host smart-b9060188-5e6d-400b-b2fe-08e0b1b3da89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754219478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.754219478
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.749224789
Short name T289
Test name
Test status
Simulation time 424974142 ps
CPU time 13.98 seconds
Started Oct 08 03:44:43 PM PDT 23
Finished Oct 08 03:44:58 PM PDT 23
Peak memory 212836 kb
Host smart-232c3d07-cadf-437b-ba89-7326f277b786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749224789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.749224789
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3182859380
Short name T169
Test name
Test status
Simulation time 3799908758 ps
CPU time 23.03 seconds
Started Oct 08 03:42:45 PM PDT 23
Finished Oct 08 03:43:09 PM PDT 23
Peak memory 213600 kb
Host smart-06732d3f-324d-4dce-bbe7-cac9861f723d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182859380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3182859380
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.81906810
Short name T241
Test name
Test status
Simulation time 77356909412 ps
CPU time 2975.4 seconds
Started Oct 08 03:44:37 PM PDT 23
Finished Oct 08 04:34:14 PM PDT 23
Peak memory 242428 kb
Host smart-9bd6b411-83fc-4291-9c57-3505317ed395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81906810 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.81906810
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.706495753
Short name T227
Test name
Test status
Simulation time 463433996 ps
CPU time 4.48 seconds
Started Oct 08 03:43:37 PM PDT 23
Finished Oct 08 03:43:42 PM PDT 23
Peak memory 211004 kb
Host smart-ba95358e-d37f-4d10-ac9a-d05017464412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706495753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.706495753
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.23807740
Short name T336
Test name
Test status
Simulation time 30580689732 ps
CPU time 148 seconds
Started Oct 08 03:51:36 PM PDT 23
Finished Oct 08 03:54:04 PM PDT 23
Peak memory 238792 kb
Host smart-94f769ef-7f87-41a3-bde2-fa91f00e6154
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23807740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_co
rrupt_sig_fatal_chk.23807740
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.242101746
Short name T221
Test name
Test status
Simulation time 519978443 ps
CPU time 11.44 seconds
Started Oct 08 03:43:53 PM PDT 23
Finished Oct 08 03:44:05 PM PDT 23
Peak memory 211312 kb
Host smart-246d59d0-c2a7-41d8-a6ef-533b4b99282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242101746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.242101746
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2733761313
Short name T376
Test name
Test status
Simulation time 2431626468 ps
CPU time 11.7 seconds
Started Oct 08 03:44:23 PM PDT 23
Finished Oct 08 03:44:35 PM PDT 23
Peak memory 211156 kb
Host smart-0a464fe2-d5ba-4965-b7dd-c7c534a178aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733761313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2733761313
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3289747444
Short name T306
Test name
Test status
Simulation time 9784046583 ps
CPU time 28.05 seconds
Started Oct 08 03:48:44 PM PDT 23
Finished Oct 08 03:49:13 PM PDT 23
Peak memory 213664 kb
Host smart-cbc96da0-cadd-4f4c-bbd8-61f5369180d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289747444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3289747444
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2962496457
Short name T7
Test name
Test status
Simulation time 48858672041 ps
CPU time 69.43 seconds
Started Oct 08 03:43:39 PM PDT 23
Finished Oct 08 03:44:49 PM PDT 23
Peak memory 216152 kb
Host smart-8e757c47-f387-4486-b670-3216f65cae45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962496457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2962496457
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3642245889
Short name T430
Test name
Test status
Simulation time 43556819811 ps
CPU time 6876.05 seconds
Started Oct 08 03:43:36 PM PDT 23
Finished Oct 08 05:38:13 PM PDT 23
Peak memory 236332 kb
Host smart-a097f51e-6a63-4ab2-99c1-7cb35286b070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642245889 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3642245889
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4226291903
Short name T354
Test name
Test status
Simulation time 346767055 ps
CPU time 4.41 seconds
Started Oct 08 03:54:32 PM PDT 23
Finished Oct 08 03:54:36 PM PDT 23
Peak memory 211044 kb
Host smart-f00d238c-6ec0-4db5-8ddc-de058b1c1fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226291903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4226291903
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1728172837
Short name T267
Test name
Test status
Simulation time 59368196834 ps
CPU time 217.26 seconds
Started Oct 08 03:44:08 PM PDT 23
Finished Oct 08 03:47:46 PM PDT 23
Peak memory 211804 kb
Host smart-30b78a0e-7a53-4979-a8d9-b6bacaa9d61d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728172837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1728172837
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2819330600
Short name T190
Test name
Test status
Simulation time 1328250086 ps
CPU time 12.19 seconds
Started Oct 08 03:53:56 PM PDT 23
Finished Oct 08 03:54:09 PM PDT 23
Peak memory 211088 kb
Host smart-d6fa5751-e0b5-4165-be17-b1a673bec519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819330600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2819330600
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.735141065
Short name T370
Test name
Test status
Simulation time 2003497458 ps
CPU time 16.85 seconds
Started Oct 08 03:54:32 PM PDT 23
Finished Oct 08 03:54:49 PM PDT 23
Peak memory 211024 kb
Host smart-a54efeba-7a6b-4727-88c9-750dd9ce7c6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735141065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.735141065
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2494999445
Short name T283
Test name
Test status
Simulation time 28518780163 ps
CPU time 36.25 seconds
Started Oct 08 03:45:28 PM PDT 23
Finished Oct 08 03:46:05 PM PDT 23
Peak memory 213512 kb
Host smart-2a14a937-01ca-45fb-aa5a-994707635033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494999445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2494999445
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2070227762
Short name T265
Test name
Test status
Simulation time 13413194143 ps
CPU time 30.47 seconds
Started Oct 08 03:47:38 PM PDT 23
Finished Oct 08 03:48:09 PM PDT 23
Peak memory 213984 kb
Host smart-d96e9ddd-2405-4816-b7ad-b64ed8ab606d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070227762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2070227762
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.363395791
Short name T250
Test name
Test status
Simulation time 33579553889 ps
CPU time 1525.28 seconds
Started Oct 08 03:47:38 PM PDT 23
Finished Oct 08 04:13:04 PM PDT 23
Peak memory 228612 kb
Host smart-d5cb521f-f1cb-4444-9daa-ac3d4f936ea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363395791 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.363395791
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2723836619
Short name T10
Test name
Test status
Simulation time 2154159888 ps
CPU time 16.43 seconds
Started Oct 08 03:44:57 PM PDT 23
Finished Oct 08 03:45:13 PM PDT 23
Peak memory 211168 kb
Host smart-1b9a600f-89cc-41bf-91ba-61d060802275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723836619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2723836619
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.141956116
Short name T63
Test name
Test status
Simulation time 38910025007 ps
CPU time 218.34 seconds
Started Oct 08 03:56:01 PM PDT 23
Finished Oct 08 03:59:40 PM PDT 23
Peak memory 237684 kb
Host smart-aa759730-bf36-4600-9601-2f838eda9600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141956116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.141956116
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3176195770
Short name T349
Test name
Test status
Simulation time 692333416 ps
CPU time 9.76 seconds
Started Oct 08 03:45:31 PM PDT 23
Finished Oct 08 03:45:41 PM PDT 23
Peak memory 211048 kb
Host smart-9d2aebba-ebc4-4441-964b-791e76724c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176195770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3176195770
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2177240389
Short name T393
Test name
Test status
Simulation time 6245794441 ps
CPU time 14.2 seconds
Started Oct 08 03:43:59 PM PDT 23
Finished Oct 08 03:44:14 PM PDT 23
Peak memory 211208 kb
Host smart-2c6fbc1e-1ceb-4251-b4e9-a9dfc75282c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177240389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2177240389
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1796059840
Short name T291
Test name
Test status
Simulation time 782100033 ps
CPU time 10.83 seconds
Started Oct 08 03:43:59 PM PDT 23
Finished Oct 08 03:44:10 PM PDT 23
Peak memory 212868 kb
Host smart-5c4277de-76da-4d9e-9f94-b078d42dbf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796059840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1796059840
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.683097175
Short name T335
Test name
Test status
Simulation time 6977376773 ps
CPU time 21.73 seconds
Started Oct 08 03:53:00 PM PDT 23
Finished Oct 08 03:53:22 PM PDT 23
Peak memory 211964 kb
Host smart-b82fcd85-d8d5-4fea-b917-77bf031dda98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683097175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.683097175
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2485579695
Short name T66
Test name
Test status
Simulation time 2669728197 ps
CPU time 12.38 seconds
Started Oct 08 03:44:05 PM PDT 23
Finished Oct 08 03:44:17 PM PDT 23
Peak memory 211052 kb
Host smart-d5bfd97a-7290-4d6e-ac93-aaf0f33562c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485579695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2485579695
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3607205801
Short name T22
Test name
Test status
Simulation time 29807167816 ps
CPU time 106.67 seconds
Started Oct 08 03:46:16 PM PDT 23
Finished Oct 08 03:48:03 PM PDT 23
Peak memory 212320 kb
Host smart-c2a1be36-044c-42f9-9957-76b541c148f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607205801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3607205801
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.815609811
Short name T178
Test name
Test status
Simulation time 2180834264 ps
CPU time 23.47 seconds
Started Oct 08 03:47:38 PM PDT 23
Finished Oct 08 03:48:01 PM PDT 23
Peak memory 211212 kb
Host smart-896bcaae-26f1-4619-ab6b-623263ae2ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815609811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.815609811
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1983050806
Short name T55
Test name
Test status
Simulation time 425120348 ps
CPU time 5.64 seconds
Started Oct 08 03:43:51 PM PDT 23
Finished Oct 08 03:43:57 PM PDT 23
Peak memory 211088 kb
Host smart-5f9d5b4e-730b-4316-bb7c-a38287dcef93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983050806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1983050806
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.513473087
Short name T382
Test name
Test status
Simulation time 5155759971 ps
CPU time 42.13 seconds
Started Oct 08 03:44:53 PM PDT 23
Finished Oct 08 03:45:36 PM PDT 23
Peak memory 213124 kb
Host smart-ea431b35-ffb1-4e13-a3f4-9c29e6305fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513473087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.513473087
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3269576333
Short name T379
Test name
Test status
Simulation time 2484589553 ps
CPU time 25.94 seconds
Started Oct 08 03:43:55 PM PDT 23
Finished Oct 08 03:44:21 PM PDT 23
Peak memory 216152 kb
Host smart-466a8d12-f1bb-4399-b2d1-cad823f666d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269576333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3269576333
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2459229984
Short name T365
Test name
Test status
Simulation time 7901604698 ps
CPU time 16.25 seconds
Started Oct 08 03:44:57 PM PDT 23
Finished Oct 08 03:45:13 PM PDT 23
Peak memory 211072 kb
Host smart-ce78017f-0a83-483e-8219-60d7530944f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459229984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2459229984
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2109258529
Short name T64
Test name
Test status
Simulation time 29040083688 ps
CPU time 294.87 seconds
Started Oct 08 03:44:59 PM PDT 23
Finished Oct 08 03:49:54 PM PDT 23
Peak memory 236672 kb
Host smart-5bc07eba-3e40-4fa8-9d64-cfe18c10d938
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109258529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2109258529
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.72906964
Short name T12
Test name
Test status
Simulation time 665428351 ps
CPU time 9.91 seconds
Started Oct 08 03:47:40 PM PDT 23
Finished Oct 08 03:47:50 PM PDT 23
Peak memory 211104 kb
Host smart-91f6301d-dce3-4d69-878a-12fcafc6da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72906964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.72906964
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2949109380
Short name T404
Test name
Test status
Simulation time 9611996756 ps
CPU time 13.16 seconds
Started Oct 08 03:45:18 PM PDT 23
Finished Oct 08 03:45:35 PM PDT 23
Peak memory 211212 kb
Host smart-efccc9ce-7842-49f6-aab4-971fae15963d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949109380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2949109380
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4081052951
Short name T243
Test name
Test status
Simulation time 14796187182 ps
CPU time 37.14 seconds
Started Oct 08 03:48:29 PM PDT 23
Finished Oct 08 03:49:07 PM PDT 23
Peak memory 213488 kb
Host smart-c55746b0-2ee2-406a-8332-206676bfde49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081052951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4081052951
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3694913848
Short name T288
Test name
Test status
Simulation time 264327040 ps
CPU time 9.78 seconds
Started Oct 08 03:54:50 PM PDT 23
Finished Oct 08 03:55:00 PM PDT 23
Peak memory 211452 kb
Host smart-dfa741ba-2e79-4fc1-bcf9-a0ef9ac68d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694913848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3694913848
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.151599897
Short name T28
Test name
Test status
Simulation time 30136692829 ps
CPU time 9265.53 seconds
Started Oct 08 03:45:41 PM PDT 23
Finished Oct 08 06:20:09 PM PDT 23
Peak memory 229528 kb
Host smart-99c06986-ca8d-47cb-bc99-ff5dc5a5b4c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151599897 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.151599897
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1572947912
Short name T321
Test name
Test status
Simulation time 1183835162 ps
CPU time 11.85 seconds
Started Oct 08 03:43:54 PM PDT 23
Finished Oct 08 03:44:06 PM PDT 23
Peak memory 211020 kb
Host smart-3a7d852b-bf17-45f7-8a1e-02165c33754f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572947912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1572947912
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3915378533
Short name T418
Test name
Test status
Simulation time 327649616573 ps
CPU time 545.39 seconds
Started Oct 08 03:48:29 PM PDT 23
Finished Oct 08 03:57:35 PM PDT 23
Peak memory 227676 kb
Host smart-b934e29f-7b43-4694-9bc0-41b68e0cdf0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915378533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3915378533
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1418585414
Short name T422
Test name
Test status
Simulation time 2212313599 ps
CPU time 23.36 seconds
Started Oct 08 03:44:56 PM PDT 23
Finished Oct 08 03:45:20 PM PDT 23
Peak memory 211352 kb
Host smart-ea2db354-e870-4b34-ab50-aeea09a770cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418585414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1418585414
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3300552520
Short name T233
Test name
Test status
Simulation time 4968765737 ps
CPU time 17.21 seconds
Started Oct 08 03:44:46 PM PDT 23
Finished Oct 08 03:45:03 PM PDT 23
Peak memory 211192 kb
Host smart-07267f8a-1549-4ee0-a96d-d80c1a796eb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300552520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3300552520
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2660246903
Short name T355
Test name
Test status
Simulation time 3149951764 ps
CPU time 16.16 seconds
Started Oct 08 03:43:53 PM PDT 23
Finished Oct 08 03:44:09 PM PDT 23
Peak memory 212672 kb
Host smart-6e5bb482-402d-4165-9a6f-62172e2daa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660246903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2660246903
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.889153181
Short name T58
Test name
Test status
Simulation time 2774186228 ps
CPU time 18.35 seconds
Started Oct 08 03:43:59 PM PDT 23
Finished Oct 08 03:44:18 PM PDT 23
Peak memory 211216 kb
Host smart-e53a81f1-4ce5-4ae6-aecc-c2f39bb6eeab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889153181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.889153181
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3461686893
Short name T412
Test name
Test status
Simulation time 6002324210 ps
CPU time 13.41 seconds
Started Oct 08 03:54:51 PM PDT 23
Finished Oct 08 03:55:05 PM PDT 23
Peak memory 211168 kb
Host smart-ae967f0b-0fc1-40ba-89c6-02928563349a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461686893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3461686893
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2387439227
Short name T384
Test name
Test status
Simulation time 90932762775 ps
CPU time 489.98 seconds
Started Oct 08 03:44:57 PM PDT 23
Finished Oct 08 03:53:07 PM PDT 23
Peak memory 224556 kb
Host smart-aa90c956-f046-4955-a88e-12fd1d63c75a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387439227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2387439227
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3982441951
Short name T328
Test name
Test status
Simulation time 8611953160 ps
CPU time 23.51 seconds
Started Oct 08 03:47:42 PM PDT 23
Finished Oct 08 03:48:06 PM PDT 23
Peak memory 211564 kb
Host smart-6f9d42cf-78b1-461c-8cd3-f980ab726a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982441951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3982441951
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1181864602
Short name T297
Test name
Test status
Simulation time 197523363 ps
CPU time 5.99 seconds
Started Oct 08 03:50:11 PM PDT 23
Finished Oct 08 03:50:17 PM PDT 23
Peak memory 211128 kb
Host smart-0deeff54-e73e-4c3f-9ad6-7bb0cb41e36c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1181864602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1181864602
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3023966937
Short name T30
Test name
Test status
Simulation time 2841725698 ps
CPU time 32.96 seconds
Started Oct 08 03:43:55 PM PDT 23
Finished Oct 08 03:44:28 PM PDT 23
Peak memory 213096 kb
Host smart-5c4c4254-8a6f-4e8f-aad2-469eb6dff0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023966937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3023966937
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3106170396
Short name T230
Test name
Test status
Simulation time 8046510108 ps
CPU time 36.38 seconds
Started Oct 08 03:44:58 PM PDT 23
Finished Oct 08 03:45:35 PM PDT 23
Peak memory 216728 kb
Host smart-073b09ce-594c-4116-a14c-e9b5ec579e5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106170396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3106170396
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.960326758
Short name T26
Test name
Test status
Simulation time 163704364253 ps
CPU time 9742.07 seconds
Started Oct 08 03:45:33 PM PDT 23
Finished Oct 08 06:27:57 PM PDT 23
Peak memory 243360 kb
Host smart-75d82895-e9fd-46bb-91c0-029318e2625e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960326758 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.960326758
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3360317843
Short name T302
Test name
Test status
Simulation time 827628224 ps
CPU time 4.5 seconds
Started Oct 08 03:47:38 PM PDT 23
Finished Oct 08 03:47:43 PM PDT 23
Peak memory 211072 kb
Host smart-0458f67a-0ac7-4bbc-b298-6e7e6d10a16c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360317843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3360317843
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.112661882
Short name T59
Test name
Test status
Simulation time 85506605609 ps
CPU time 202.65 seconds
Started Oct 08 03:43:56 PM PDT 23
Finished Oct 08 03:47:19 PM PDT 23
Peak memory 228200 kb
Host smart-e3bbc08c-a208-4e1f-9c8b-2638058f6db0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112661882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.112661882
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4109917864
Short name T257
Test name
Test status
Simulation time 986131535 ps
CPU time 13.34 seconds
Started Oct 08 03:43:57 PM PDT 23
Finished Oct 08 03:44:10 PM PDT 23
Peak memory 211252 kb
Host smart-3221a819-35f9-4770-b979-dc1c9d91e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109917864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4109917864
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.798343647
Short name T383
Test name
Test status
Simulation time 99411074 ps
CPU time 5.61 seconds
Started Oct 08 03:44:22 PM PDT 23
Finished Oct 08 03:44:28 PM PDT 23
Peak memory 211028 kb
Host smart-a31e7473-af61-410d-9422-27fe8b8ac13e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798343647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.798343647
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2690019002
Short name T185
Test name
Test status
Simulation time 11558931838 ps
CPU time 35.04 seconds
Started Oct 08 03:55:38 PM PDT 23
Finished Oct 08 03:56:13 PM PDT 23
Peak memory 213736 kb
Host smart-7407e665-fbdb-4cc1-83d9-1a6556619033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690019002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2690019002
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3536868540
Short name T209
Test name
Test status
Simulation time 2152902257 ps
CPU time 16.63 seconds
Started Oct 08 03:49:15 PM PDT 23
Finished Oct 08 03:49:32 PM PDT 23
Peak memory 213556 kb
Host smart-4800e52a-06a2-474c-814c-9fb09936c3ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536868540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3536868540
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2716986354
Short name T293
Test name
Test status
Simulation time 69897036070 ps
CPU time 4659.5 seconds
Started Oct 08 03:43:57 PM PDT 23
Finished Oct 08 05:01:37 PM PDT 23
Peak memory 236276 kb
Host smart-fd1ed8e8-2e6e-4fb0-bc4d-173df70e55af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716986354 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2716986354
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2700337374
Short name T44
Test name
Test status
Simulation time 1184564496 ps
CPU time 11.82 seconds
Started Oct 08 03:43:59 PM PDT 23
Finished Oct 08 03:44:11 PM PDT 23
Peak memory 211108 kb
Host smart-e078ca5f-f37e-4128-ae10-57dac8384ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700337374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2700337374
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2184327562
Short name T272
Test name
Test status
Simulation time 22703900979 ps
CPU time 178.03 seconds
Started Oct 08 03:53:40 PM PDT 23
Finished Oct 08 03:56:38 PM PDT 23
Peak memory 237596 kb
Host smart-3c878795-f182-45b6-b9a2-762f4cb7b074
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184327562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2184327562
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1892182990
Short name T372
Test name
Test status
Simulation time 2540360557 ps
CPU time 25.02 seconds
Started Oct 08 03:47:39 PM PDT 23
Finished Oct 08 03:48:05 PM PDT 23
Peak memory 211200 kb
Host smart-bb5609b0-129f-49a1-8274-ca168ed2adf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892182990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1892182990
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1280385114
Short name T381
Test name
Test status
Simulation time 346083719 ps
CPU time 5.45 seconds
Started Oct 08 03:44:24 PM PDT 23
Finished Oct 08 03:44:30 PM PDT 23
Peak memory 211056 kb
Host smart-1915e1b1-7d80-4d07-9092-02d9d7539763
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1280385114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1280385114
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1102298346
Short name T394
Test name
Test status
Simulation time 2730251831 ps
CPU time 25.58 seconds
Started Oct 08 03:45:42 PM PDT 23
Finished Oct 08 03:46:07 PM PDT 23
Peak memory 212640 kb
Host smart-d0556ed0-e23d-4cf7-83cd-dacd7018978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102298346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1102298346
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1339938284
Short name T4
Test name
Test status
Simulation time 10744206142 ps
CPU time 90.5 seconds
Started Oct 08 03:43:59 PM PDT 23
Finished Oct 08 03:45:30 PM PDT 23
Peak memory 215280 kb
Host smart-7e2e242e-e9f7-4341-8261-eff45085323c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339938284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1339938284
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.646072047
Short name T105
Test name
Test status
Simulation time 47310505432 ps
CPU time 1777.99 seconds
Started Oct 08 03:45:31 PM PDT 23
Finished Oct 08 04:15:09 PM PDT 23
Peak memory 235820 kb
Host smart-8ae71867-1d60-4a3a-a211-3ae40663a1c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646072047 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.646072047
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2569108238
Short name T222
Test name
Test status
Simulation time 8258755048 ps
CPU time 17.09 seconds
Started Oct 08 03:45:32 PM PDT 23
Finished Oct 08 03:45:49 PM PDT 23
Peak memory 211152 kb
Host smart-877c13fb-6a40-4ac3-8372-f4e2511fd71d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569108238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2569108238
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2238581562
Short name T315
Test name
Test status
Simulation time 34884143489 ps
CPU time 224.8 seconds
Started Oct 08 03:49:04 PM PDT 23
Finished Oct 08 03:52:49 PM PDT 23
Peak memory 227908 kb
Host smart-83a2e826-868e-4663-b019-acadbeffdf39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238581562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2238581562
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2440668114
Short name T161
Test name
Test status
Simulation time 3659869857 ps
CPU time 31.55 seconds
Started Oct 08 03:48:33 PM PDT 23
Finished Oct 08 03:49:05 PM PDT 23
Peak memory 211320 kb
Host smart-c44ba366-462f-4fa7-bc27-1cc5e3554b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440668114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2440668114
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1988039912
Short name T368
Test name
Test status
Simulation time 376785612 ps
CPU time 5.76 seconds
Started Oct 08 03:44:25 PM PDT 23
Finished Oct 08 03:44:31 PM PDT 23
Peak memory 211032 kb
Host smart-509d8182-dce9-47b3-a25a-2f2a12ea446c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988039912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1988039912
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3895156049
Short name T212
Test name
Test status
Simulation time 1361325943 ps
CPU time 14.16 seconds
Started Oct 08 03:44:58 PM PDT 23
Finished Oct 08 03:45:12 PM PDT 23
Peak memory 213116 kb
Host smart-cc3e6373-a3f9-46fd-8a3a-fae3b6bef705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895156049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3895156049
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2880120934
Short name T429
Test name
Test status
Simulation time 16195394092 ps
CPU time 40.73 seconds
Started Oct 08 03:48:27 PM PDT 23
Finished Oct 08 03:49:08 PM PDT 23
Peak memory 215148 kb
Host smart-95da32e6-986b-47ff-be52-62b7915fdb4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880120934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2880120934
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.338806206
Short name T235
Test name
Test status
Simulation time 3939878610 ps
CPU time 15.48 seconds
Started Oct 08 03:51:06 PM PDT 23
Finished Oct 08 03:51:22 PM PDT 23
Peak memory 211096 kb
Host smart-d923ae11-1e6c-4599-b7ba-5840756c61cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338806206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.338806206
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3299289332
Short name T352
Test name
Test status
Simulation time 56149873467 ps
CPU time 555.07 seconds
Started Oct 08 03:46:00 PM PDT 23
Finished Oct 08 03:55:15 PM PDT 23
Peak memory 212600 kb
Host smart-64664ae7-3dc1-494d-a7ac-2e41bd9707a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299289332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3299289332
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3847456077
Short name T398
Test name
Test status
Simulation time 13117414076 ps
CPU time 27.6 seconds
Started Oct 08 03:51:18 PM PDT 23
Finished Oct 08 03:51:46 PM PDT 23
Peak memory 211668 kb
Host smart-3fb86035-5f1c-4d86-ba64-012777999c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847456077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3847456077
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.194480045
Short name T177
Test name
Test status
Simulation time 9779201765 ps
CPU time 10.85 seconds
Started Oct 08 03:51:18 PM PDT 23
Finished Oct 08 03:51:29 PM PDT 23
Peak memory 211160 kb
Host smart-f4627f6e-d467-41e6-96a5-cc3146ccf136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194480045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.194480045
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1215044249
Short name T23
Test name
Test status
Simulation time 568307608 ps
CPU time 57.55 seconds
Started Oct 08 03:44:43 PM PDT 23
Finished Oct 08 03:45:41 PM PDT 23
Peak memory 237296 kb
Host smart-f5e18b74-f197-458b-a734-fffe51d4aa4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215044249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1215044249
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3759069548
Short name T180
Test name
Test status
Simulation time 15806435071 ps
CPU time 39.34 seconds
Started Oct 08 03:42:48 PM PDT 23
Finished Oct 08 03:43:28 PM PDT 23
Peak memory 213788 kb
Host smart-6f3a2bb6-3249-4b74-b406-191bf5a369c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759069548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3759069548
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1517756176
Short name T210
Test name
Test status
Simulation time 8489651031 ps
CPU time 17.47 seconds
Started Oct 08 03:54:22 PM PDT 23
Finished Oct 08 03:54:40 PM PDT 23
Peak memory 211048 kb
Host smart-aa94e174-187b-4235-9b41-7dfa7ff3f78e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517756176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1517756176
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3304437970
Short name T369
Test name
Test status
Simulation time 34926992803 ps
CPU time 2246.61 seconds
Started Oct 08 03:47:16 PM PDT 23
Finished Oct 08 04:24:44 PM PDT 23
Peak memory 235900 kb
Host smart-dff527d6-100d-4249-8a81-d3d26dd7cff4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304437970 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3304437970
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.395504646
Short name T273
Test name
Test status
Simulation time 1380100001 ps
CPU time 4.39 seconds
Started Oct 08 03:52:57 PM PDT 23
Finished Oct 08 03:53:02 PM PDT 23
Peak memory 210980 kb
Host smart-be656814-3eda-414a-a302-f6c55a1d956d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395504646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.395504646
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2581707817
Short name T239
Test name
Test status
Simulation time 51292616079 ps
CPU time 310.38 seconds
Started Oct 08 03:51:13 PM PDT 23
Finished Oct 08 03:56:24 PM PDT 23
Peak memory 233676 kb
Host smart-374e9c06-b13c-47f8-b904-f6b545038d9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581707817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2581707817
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3522607872
Short name T260
Test name
Test status
Simulation time 8617198436 ps
CPU time 20.53 seconds
Started Oct 08 03:45:42 PM PDT 23
Finished Oct 08 03:46:03 PM PDT 23
Peak memory 213512 kb
Host smart-2feb2646-f635-4175-a751-67cd95c5724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522607872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3522607872
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.968304747
Short name T334
Test name
Test status
Simulation time 3283966485 ps
CPU time 14.28 seconds
Started Oct 08 03:51:26 PM PDT 23
Finished Oct 08 03:51:40 PM PDT 23
Peak memory 211052 kb
Host smart-4f8b5283-617d-44b1-82e4-537b0efe5efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968304747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.968304747
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2579726346
Short name T414
Test name
Test status
Simulation time 186239678 ps
CPU time 10.54 seconds
Started Oct 08 03:47:46 PM PDT 23
Finished Oct 08 03:47:56 PM PDT 23
Peak memory 212644 kb
Host smart-df435028-80b2-4d7d-bc80-29d1cd1228a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579726346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2579726346
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.680729186
Short name T311
Test name
Test status
Simulation time 619597051 ps
CPU time 12.21 seconds
Started Oct 08 03:47:30 PM PDT 23
Finished Oct 08 03:47:43 PM PDT 23
Peak memory 213448 kb
Host smart-0ee33f8a-2287-4701-a37f-c311901b9f17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680729186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.680729186
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2601624902
Short name T342
Test name
Test status
Simulation time 47232596263 ps
CPU time 10689.4 seconds
Started Oct 08 03:55:16 PM PDT 23
Finished Oct 08 06:53:28 PM PDT 23
Peak memory 235768 kb
Host smart-c89b461f-370d-4422-a9d9-5188b74df44f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601624902 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2601624902
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1327614382
Short name T305
Test name
Test status
Simulation time 7263105109 ps
CPU time 12.67 seconds
Started Oct 08 03:53:03 PM PDT 23
Finished Oct 08 03:53:16 PM PDT 23
Peak memory 211180 kb
Host smart-7fc2f4d6-bf6e-498a-80c9-9bb81367e621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327614382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1327614382
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2888749228
Short name T67
Test name
Test status
Simulation time 62514965800 ps
CPU time 99.5 seconds
Started Oct 08 03:46:54 PM PDT 23
Finished Oct 08 03:48:36 PM PDT 23
Peak memory 233744 kb
Host smart-81269551-688a-48ad-b416-0af408bf29fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888749228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2888749228
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2917812305
Short name T345
Test name
Test status
Simulation time 13266027740 ps
CPU time 29.24 seconds
Started Oct 08 03:45:12 PM PDT 23
Finished Oct 08 03:45:42 PM PDT 23
Peak memory 211600 kb
Host smart-9af877c0-8562-47c1-b6d7-6192453b000f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917812305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2917812305
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2671802506
Short name T179
Test name
Test status
Simulation time 19226054226 ps
CPU time 14.43 seconds
Started Oct 08 03:44:15 PM PDT 23
Finished Oct 08 03:44:30 PM PDT 23
Peak memory 211040 kb
Host smart-bcf80a8b-4069-484a-9ce8-912ecbbbe7b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671802506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2671802506
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2521176744
Short name T253
Test name
Test status
Simulation time 3224078355 ps
CPU time 20.62 seconds
Started Oct 08 03:45:54 PM PDT 23
Finished Oct 08 03:46:15 PM PDT 23
Peak memory 212976 kb
Host smart-2c780bc4-4d96-4be6-9cb6-30122fdc04e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521176744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2521176744
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1045378563
Short name T152
Test name
Test status
Simulation time 13146631286 ps
CPU time 127.29 seconds
Started Oct 08 03:53:29 PM PDT 23
Finished Oct 08 03:55:37 PM PDT 23
Peak memory 219244 kb
Host smart-f34c09f3-7a41-4ebf-8919-24833cb719c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045378563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1045378563
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2119467482
Short name T9
Test name
Test status
Simulation time 17008423747 ps
CPU time 838.21 seconds
Started Oct 08 03:45:44 PM PDT 23
Finished Oct 08 03:59:42 PM PDT 23
Peak memory 233868 kb
Host smart-51f1264e-2c28-43b5-a5ed-f3597ca141ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119467482 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2119467482
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3282456855
Short name T192
Test name
Test status
Simulation time 663700357 ps
CPU time 8.93 seconds
Started Oct 08 03:52:23 PM PDT 23
Finished Oct 08 03:52:32 PM PDT 23
Peak memory 211024 kb
Host smart-69fdee71-cfbb-461d-b0a6-45aa7c3b17f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282456855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3282456855
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3810939929
Short name T338
Test name
Test status
Simulation time 12353456103 ps
CPU time 27.45 seconds
Started Oct 08 03:45:50 PM PDT 23
Finished Oct 08 03:46:18 PM PDT 23
Peak memory 212032 kb
Host smart-a62bdd08-33ef-486e-b2d4-2e310daf84d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810939929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3810939929
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1921805945
Short name T214
Test name
Test status
Simulation time 5034217422 ps
CPU time 13.06 seconds
Started Oct 08 03:45:52 PM PDT 23
Finished Oct 08 03:46:06 PM PDT 23
Peak memory 211152 kb
Host smart-b31dd209-f828-42c5-8f66-374ee09d55a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921805945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1921805945
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1096260549
Short name T295
Test name
Test status
Simulation time 190624997 ps
CPU time 10.13 seconds
Started Oct 08 03:46:18 PM PDT 23
Finished Oct 08 03:46:29 PM PDT 23
Peak memory 212968 kb
Host smart-20d481ba-dc98-4dad-b0b7-09646688b56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096260549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1096260549
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2079946591
Short name T29
Test name
Test status
Simulation time 2168658431 ps
CPU time 32.07 seconds
Started Oct 08 03:44:59 PM PDT 23
Finished Oct 08 03:45:31 PM PDT 23
Peak memory 215980 kb
Host smart-c1589495-5034-43dd-b35f-8ad98960d6dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079946591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2079946591
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3854198916
Short name T360
Test name
Test status
Simulation time 4085043467 ps
CPU time 7.31 seconds
Started Oct 08 03:47:21 PM PDT 23
Finished Oct 08 03:47:28 PM PDT 23
Peak memory 211168 kb
Host smart-eb58101b-2a30-46e1-8b1f-142c6e5b3a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854198916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3854198916
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1894716144
Short name T377
Test name
Test status
Simulation time 36921228074 ps
CPU time 391.21 seconds
Started Oct 08 03:52:20 PM PDT 23
Finished Oct 08 03:58:52 PM PDT 23
Peak memory 233844 kb
Host smart-edc36b94-2ba1-4ff9-bce6-1dbc3e7f76a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894716144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1894716144
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1080553591
Short name T287
Test name
Test status
Simulation time 2880379029 ps
CPU time 26.49 seconds
Started Oct 08 03:55:33 PM PDT 23
Finished Oct 08 03:56:00 PM PDT 23
Peak memory 211324 kb
Host smart-18bc5d80-6e54-4971-9500-429064781670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080553591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1080553591
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1069824428
Short name T410
Test name
Test status
Simulation time 1897713429 ps
CPU time 15.77 seconds
Started Oct 08 03:44:10 PM PDT 23
Finished Oct 08 03:44:26 PM PDT 23
Peak memory 210964 kb
Host smart-ab7ad455-e475-4793-9b6d-260c19391a9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069824428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1069824428
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2812740425
Short name T261
Test name
Test status
Simulation time 13658981782 ps
CPU time 34.83 seconds
Started Oct 08 03:55:15 PM PDT 23
Finished Oct 08 03:55:50 PM PDT 23
Peak memory 213324 kb
Host smart-63b3d144-9041-4bf9-819b-1474fd8e581e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812740425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2812740425
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1145326615
Short name T304
Test name
Test status
Simulation time 1450728980 ps
CPU time 17.57 seconds
Started Oct 08 03:49:29 PM PDT 23
Finished Oct 08 03:49:47 PM PDT 23
Peak memory 211320 kb
Host smart-a2fab5e2-3d92-4a4a-91ae-cc77105393e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145326615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1145326615
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3378332392
Short name T237
Test name
Test status
Simulation time 1805750181 ps
CPU time 9.94 seconds
Started Oct 08 03:47:06 PM PDT 23
Finished Oct 08 03:47:16 PM PDT 23
Peak memory 211016 kb
Host smart-0b90312a-9d66-49bd-a554-fa90dcc68a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378332392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3378332392
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.339155297
Short name T254
Test name
Test status
Simulation time 28551135282 ps
CPU time 23.29 seconds
Started Oct 08 03:53:48 PM PDT 23
Finished Oct 08 03:54:11 PM PDT 23
Peak memory 211964 kb
Host smart-5227b443-5045-4dcb-a7ef-af65e5a6e16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339155297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.339155297
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3190729685
Short name T240
Test name
Test status
Simulation time 1237157850 ps
CPU time 12.6 seconds
Started Oct 08 03:44:05 PM PDT 23
Finished Oct 08 03:44:18 PM PDT 23
Peak memory 210808 kb
Host smart-68c58825-eb5d-4c40-9318-8fbece8ca113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190729685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3190729685
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1724953730
Short name T290
Test name
Test status
Simulation time 12184084313 ps
CPU time 29.82 seconds
Started Oct 08 03:53:33 PM PDT 23
Finished Oct 08 03:54:03 PM PDT 23
Peak memory 213664 kb
Host smart-affd0488-5129-40b8-a4fe-defffe6dadf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724953730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1724953730
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.21902976
Short name T3
Test name
Test status
Simulation time 417675073 ps
CPU time 21.79 seconds
Started Oct 08 03:53:30 PM PDT 23
Finished Oct 08 03:53:52 PM PDT 23
Peak memory 215788 kb
Host smart-58747065-4d3f-44b0-8163-72fa18e626ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21902976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.rom_ctrl_stress_all.21902976
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3201912426
Short name T351
Test name
Test status
Simulation time 53689943878 ps
CPU time 5054.46 seconds
Started Oct 08 03:44:29 PM PDT 23
Finished Oct 08 05:08:45 PM PDT 23
Peak memory 234648 kb
Host smart-c33ba4a2-17db-4d56-8721-64e43fb70335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201912426 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3201912426
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3259524467
Short name T236
Test name
Test status
Simulation time 102463834 ps
CPU time 4.4 seconds
Started Oct 08 03:44:30 PM PDT 23
Finished Oct 08 03:44:35 PM PDT 23
Peak memory 211020 kb
Host smart-6fc40c5b-b744-4675-b884-f35db12972a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259524467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3259524467
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3649844223
Short name T392
Test name
Test status
Simulation time 4750108231 ps
CPU time 158.13 seconds
Started Oct 08 03:46:13 PM PDT 23
Finished Oct 08 03:48:51 PM PDT 23
Peak memory 224444 kb
Host smart-47e935ea-3da3-4929-a0c7-617f986dd193
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649844223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3649844223
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1858445710
Short name T8
Test name
Test status
Simulation time 14456171651 ps
CPU time 31.19 seconds
Started Oct 08 03:44:36 PM PDT 23
Finished Oct 08 03:45:08 PM PDT 23
Peak memory 211436 kb
Host smart-5198dd7a-8c3d-470f-a2e5-09ea3cac89e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858445710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1858445710
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2886498798
Short name T313
Test name
Test status
Simulation time 2197056095 ps
CPU time 13.81 seconds
Started Oct 08 03:54:45 PM PDT 23
Finished Oct 08 03:54:59 PM PDT 23
Peak memory 211080 kb
Host smart-c61c90f3-95fc-4dac-a639-fa0415dbcd43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886498798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2886498798
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2582413297
Short name T203
Test name
Test status
Simulation time 17189589442 ps
CPU time 38.61 seconds
Started Oct 08 03:45:17 PM PDT 23
Finished Oct 08 03:45:56 PM PDT 23
Peak memory 213212 kb
Host smart-34ed5acc-5caa-433b-beb5-0b36a808b8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582413297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2582413297
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2715413426
Short name T176
Test name
Test status
Simulation time 486685021 ps
CPU time 26.05 seconds
Started Oct 08 03:53:07 PM PDT 23
Finished Oct 08 03:53:34 PM PDT 23
Peak memory 214564 kb
Host smart-9c41c4e8-587e-424c-9a05-fc6f1472ddec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715413426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2715413426
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2286282985
Short name T215
Test name
Test status
Simulation time 169222286329 ps
CPU time 5530.92 seconds
Started Oct 08 03:46:11 PM PDT 23
Finished Oct 08 05:18:23 PM PDT 23
Peak memory 239468 kb
Host smart-09056457-b8d9-47aa-9f0d-50682062b5de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286282985 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2286282985
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3016995708
Short name T301
Test name
Test status
Simulation time 1174655246 ps
CPU time 12.04 seconds
Started Oct 08 03:52:57 PM PDT 23
Finished Oct 08 03:53:09 PM PDT 23
Peak memory 211016 kb
Host smart-893b5e65-87a2-429c-8c29-7c978a16881a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016995708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3016995708
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2966761501
Short name T256
Test name
Test status
Simulation time 2359078311 ps
CPU time 161.92 seconds
Started Oct 08 03:50:51 PM PDT 23
Finished Oct 08 03:53:34 PM PDT 23
Peak memory 237652 kb
Host smart-2bc69360-9284-4566-a641-93724f90f0bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966761501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2966761501
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.459431670
Short name T18
Test name
Test status
Simulation time 4182494155 ps
CPU time 22.72 seconds
Started Oct 08 03:44:29 PM PDT 23
Finished Oct 08 03:44:52 PM PDT 23
Peak memory 211400 kb
Host smart-c7090013-af0c-4aff-8e43-4437b676b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459431670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.459431670
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3568688557
Short name T153
Test name
Test status
Simulation time 692294079 ps
CPU time 7.14 seconds
Started Oct 08 03:46:29 PM PDT 23
Finished Oct 08 03:46:36 PM PDT 23
Peak memory 211128 kb
Host smart-0b39e47e-4043-413c-b8bf-5390135c49c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3568688557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3568688557
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1950062766
Short name T397
Test name
Test status
Simulation time 4591760154 ps
CPU time 19.32 seconds
Started Oct 08 03:54:21 PM PDT 23
Finished Oct 08 03:54:41 PM PDT 23
Peak memory 213220 kb
Host smart-c8c30663-bf12-4d20-a913-a609df4099a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950062766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1950062766
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4042462192
Short name T245
Test name
Test status
Simulation time 1254347476 ps
CPU time 17.15 seconds
Started Oct 08 03:56:32 PM PDT 23
Finished Oct 08 03:56:49 PM PDT 23
Peak memory 212816 kb
Host smart-e8080a36-e5cd-4ddb-9efa-e2f902e3fec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042462192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4042462192
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4156440791
Short name T309
Test name
Test status
Simulation time 54979018839 ps
CPU time 6901.15 seconds
Started Oct 08 03:52:58 PM PDT 23
Finished Oct 08 05:48:01 PM PDT 23
Peak memory 234652 kb
Host smart-c3cf221e-1aa6-4988-8f1d-03694b6df684
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156440791 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.4156440791
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1582185384
Short name T337
Test name
Test status
Simulation time 1617174076 ps
CPU time 9.76 seconds
Started Oct 08 03:52:58 PM PDT 23
Finished Oct 08 03:53:08 PM PDT 23
Peak memory 211056 kb
Host smart-1757f8dd-302d-4fca-ae7e-b704816a91ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582185384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1582185384
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3456399812
Short name T183
Test name
Test status
Simulation time 102338778729 ps
CPU time 321.2 seconds
Started Oct 08 03:44:26 PM PDT 23
Finished Oct 08 03:49:47 PM PDT 23
Peak memory 234828 kb
Host smart-3ce6a51f-d90f-4fcf-bee2-b977e21e9681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456399812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3456399812
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1615691485
Short name T232
Test name
Test status
Simulation time 2806030884 ps
CPU time 25.77 seconds
Started Oct 08 03:49:04 PM PDT 23
Finished Oct 08 03:49:30 PM PDT 23
Peak memory 211372 kb
Host smart-cbb746aa-35bb-42c7-b7d6-f65fb121bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615691485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1615691485
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3056522509
Short name T193
Test name
Test status
Simulation time 96416129 ps
CPU time 5.92 seconds
Started Oct 08 03:50:33 PM PDT 23
Finished Oct 08 03:50:39 PM PDT 23
Peak memory 211044 kb
Host smart-262d28b9-89d1-4df2-af17-5d44e4ccb0a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3056522509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3056522509
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1866470582
Short name T204
Test name
Test status
Simulation time 744364163 ps
CPU time 10.48 seconds
Started Oct 08 03:45:41 PM PDT 23
Finished Oct 08 03:45:52 PM PDT 23
Peak memory 212364 kb
Host smart-3a5d3012-09e8-4625-8134-fa5e3fa6ec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866470582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1866470582
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.9305237
Short name T269
Test name
Test status
Simulation time 1425513602 ps
CPU time 21.05 seconds
Started Oct 08 03:44:26 PM PDT 23
Finished Oct 08 03:44:47 PM PDT 23
Peak memory 214532 kb
Host smart-37eb5752-5a99-4042-8287-040b6d12a74b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9305237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.rom_ctrl_stress_all.9305237
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.602296671
Short name T200
Test name
Test status
Simulation time 3354392801 ps
CPU time 9.83 seconds
Started Oct 08 03:51:53 PM PDT 23
Finished Oct 08 03:52:03 PM PDT 23
Peak memory 211196 kb
Host smart-5e11c1e9-c42d-4b02-a1ee-bea80b169b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602296671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.602296671
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1167953611
Short name T413
Test name
Test status
Simulation time 14138661557 ps
CPU time 106.99 seconds
Started Oct 08 03:54:17 PM PDT 23
Finished Oct 08 03:56:05 PM PDT 23
Peak memory 231340 kb
Host smart-e8e616bd-95cf-4876-81aa-74c951d1f09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167953611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1167953611
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3910777487
Short name T307
Test name
Test status
Simulation time 1236235364 ps
CPU time 17.38 seconds
Started Oct 08 03:47:08 PM PDT 23
Finished Oct 08 03:47:26 PM PDT 23
Peak memory 211236 kb
Host smart-8f73a861-6ab9-4985-bbae-6462fd1427ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910777487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3910777487
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3890314
Short name T405
Test name
Test status
Simulation time 995056158 ps
CPU time 11.03 seconds
Started Oct 08 03:45:10 PM PDT 23
Finished Oct 08 03:45:22 PM PDT 23
Peak memory 211008 kb
Host smart-a0762064-792d-4c11-b937-af8578cee96c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3890314
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3922661426
Short name T279
Test name
Test status
Simulation time 5666644196 ps
CPU time 27.59 seconds
Started Oct 08 03:52:27 PM PDT 23
Finished Oct 08 03:52:54 PM PDT 23
Peak memory 212812 kb
Host smart-3535b82c-8207-45c9-bec8-9048df5be408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922661426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3922661426
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1994022700
Short name T218
Test name
Test status
Simulation time 407221916 ps
CPU time 22.89 seconds
Started Oct 08 03:45:34 PM PDT 23
Finished Oct 08 03:45:57 PM PDT 23
Peak memory 214896 kb
Host smart-9b5463ed-cf8e-403f-839d-bac1e26c0c66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994022700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1994022700
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.904763193
Short name T409
Test name
Test status
Simulation time 1550777859 ps
CPU time 7.11 seconds
Started Oct 08 03:55:25 PM PDT 23
Finished Oct 08 03:55:33 PM PDT 23
Peak memory 210992 kb
Host smart-cb52d0ec-012d-422e-a3c8-31287f2ca4f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904763193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.904763193
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3534490267
Short name T343
Test name
Test status
Simulation time 67893488173 ps
CPU time 202.76 seconds
Started Oct 08 03:54:53 PM PDT 23
Finished Oct 08 03:58:16 PM PDT 23
Peak memory 237724 kb
Host smart-61eb6079-9082-438f-aabc-12a5d7ff90d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534490267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3534490267
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.223997762
Short name T226
Test name
Test status
Simulation time 12280372498 ps
CPU time 27.21 seconds
Started Oct 08 03:48:35 PM PDT 23
Finished Oct 08 03:49:02 PM PDT 23
Peak memory 211568 kb
Host smart-fe41b6e9-d8e9-42f5-b1e9-9e63588d06eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223997762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.223997762
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3376882864
Short name T223
Test name
Test status
Simulation time 1590154364 ps
CPU time 14.07 seconds
Started Oct 08 03:47:31 PM PDT 23
Finished Oct 08 03:47:46 PM PDT 23
Peak memory 210964 kb
Host smart-f9985245-ec83-4c4e-b302-886164f0eb11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3376882864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3376882864
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2194205227
Short name T182
Test name
Test status
Simulation time 355800894 ps
CPU time 9.65 seconds
Started Oct 08 03:55:23 PM PDT 23
Finished Oct 08 03:55:33 PM PDT 23
Peak memory 212780 kb
Host smart-b6a0a4f5-a359-4805-ae1a-e0979ae3c71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194205227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2194205227
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1463888876
Short name T380
Test name
Test status
Simulation time 3197157770 ps
CPU time 17.4 seconds
Started Oct 08 03:51:53 PM PDT 23
Finished Oct 08 03:52:11 PM PDT 23
Peak memory 211080 kb
Host smart-a9582b4f-f9f9-4385-83a5-5562979dc006
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463888876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1463888876
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.4199296042
Short name T400
Test name
Test status
Simulation time 25164354391 ps
CPU time 939 seconds
Started Oct 08 03:46:46 PM PDT 23
Finished Oct 08 04:02:29 PM PDT 23
Peak memory 227604 kb
Host smart-635ec43e-a443-499c-a2fa-096bdba06592
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199296042 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.4199296042
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1258405486
Short name T155
Test name
Test status
Simulation time 1834414160 ps
CPU time 15.03 seconds
Started Oct 08 03:54:24 PM PDT 23
Finished Oct 08 03:54:41 PM PDT 23
Peak memory 211076 kb
Host smart-e8596a95-4329-4644-a3f8-dcca08ec4d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258405486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1258405486
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2399851649
Short name T231
Test name
Test status
Simulation time 126680291898 ps
CPU time 283.43 seconds
Started Oct 08 03:45:06 PM PDT 23
Finished Oct 08 03:49:49 PM PDT 23
Peak memory 237780 kb
Host smart-61e0febe-1713-49bf-82fb-302869390a89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399851649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2399851649
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1063835474
Short name T11
Test name
Test status
Simulation time 17022533082 ps
CPU time 34.26 seconds
Started Oct 08 03:42:54 PM PDT 23
Finished Oct 08 03:43:28 PM PDT 23
Peak memory 211476 kb
Host smart-0e2617ae-6118-4d62-a91f-9c16480e4020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063835474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1063835474
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4261258364
Short name T229
Test name
Test status
Simulation time 3620681168 ps
CPU time 16.08 seconds
Started Oct 08 03:54:40 PM PDT 23
Finished Oct 08 03:54:57 PM PDT 23
Peak memory 211180 kb
Host smart-b9d9bf9f-7e03-425b-8689-9f1205618c8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4261258364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4261258364
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2610553725
Short name T51
Test name
Test status
Simulation time 342023038 ps
CPU time 111.95 seconds
Started Oct 08 03:46:35 PM PDT 23
Finished Oct 08 03:48:27 PM PDT 23
Peak memory 236528 kb
Host smart-ce8eb030-bcc2-471a-9edd-0b047a15aeba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610553725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2610553725
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.262652289
Short name T251
Test name
Test status
Simulation time 1328942099 ps
CPU time 17.91 seconds
Started Oct 08 03:52:46 PM PDT 23
Finished Oct 08 03:53:04 PM PDT 23
Peak memory 212704 kb
Host smart-42626929-09de-4413-8f9c-56b229208287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262652289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.262652289
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1268421346
Short name T158
Test name
Test status
Simulation time 604616491 ps
CPU time 34.25 seconds
Started Oct 08 03:44:35 PM PDT 23
Finished Oct 08 03:45:09 PM PDT 23
Peak memory 215932 kb
Host smart-5d35f4be-c2a1-423b-9452-76d6fdbd64c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268421346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1268421346
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3066736157
Short name T333
Test name
Test status
Simulation time 41206205737 ps
CPU time 1482.58 seconds
Started Oct 08 03:50:44 PM PDT 23
Finished Oct 08 04:15:27 PM PDT 23
Peak memory 232316 kb
Host smart-61c61c9a-7cc1-4432-8b4a-cc96e742b97d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066736157 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3066736157
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3992601131
Short name T347
Test name
Test status
Simulation time 1492104767 ps
CPU time 13.44 seconds
Started Oct 08 03:45:32 PM PDT 23
Finished Oct 08 03:45:45 PM PDT 23
Peak memory 210976 kb
Host smart-2194a336-4e30-43eb-9e22-d161a53cde92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992601131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3992601131
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.906436702
Short name T281
Test name
Test status
Simulation time 78710029740 ps
CPU time 225.19 seconds
Started Oct 08 03:49:51 PM PDT 23
Finished Oct 08 03:53:37 PM PDT 23
Peak memory 236704 kb
Host smart-5c24d2b5-2fcf-4141-bc54-1ff5c411662d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906436702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.906436702
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3377968263
Short name T348
Test name
Test status
Simulation time 9550911488 ps
CPU time 23.7 seconds
Started Oct 08 03:53:20 PM PDT 23
Finished Oct 08 03:53:44 PM PDT 23
Peak memory 211524 kb
Host smart-3b5c2be1-23c1-4eef-b8fc-04aebb943771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377968263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3377968263
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.240964207
Short name T284
Test name
Test status
Simulation time 1819103544 ps
CPU time 15.25 seconds
Started Oct 08 03:54:54 PM PDT 23
Finished Oct 08 03:55:09 PM PDT 23
Peak memory 211068 kb
Host smart-417deec6-258c-4626-a2cb-cc22b652661c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=240964207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.240964207
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1149237959
Short name T388
Test name
Test status
Simulation time 5379587806 ps
CPU time 27.02 seconds
Started Oct 08 03:47:52 PM PDT 23
Finished Oct 08 03:48:20 PM PDT 23
Peak memory 213156 kb
Host smart-de4b671d-2961-4cfb-a6f7-2708b535724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149237959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1149237959
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2691492911
Short name T363
Test name
Test status
Simulation time 107812263 ps
CPU time 9.12 seconds
Started Oct 08 03:46:28 PM PDT 23
Finished Oct 08 03:46:37 PM PDT 23
Peak memory 210924 kb
Host smart-e912e4c0-c50c-40f2-92fc-ab6b54d3095b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691492911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2691492911
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.602853031
Short name T274
Test name
Test status
Simulation time 1133007769 ps
CPU time 11.14 seconds
Started Oct 08 03:49:20 PM PDT 23
Finished Oct 08 03:49:31 PM PDT 23
Peak memory 211084 kb
Host smart-f613fe1e-0bf6-40ad-b00f-09b4d8661491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602853031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.602853031
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.124000253
Short name T325
Test name
Test status
Simulation time 184069523345 ps
CPU time 493.51 seconds
Started Oct 08 03:47:51 PM PDT 23
Finished Oct 08 03:56:05 PM PDT 23
Peak memory 236936 kb
Host smart-987e0002-0e35-4ae7-a300-81fa77e90ba6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124000253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.124000253
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.322180987
Short name T195
Test name
Test status
Simulation time 3495438395 ps
CPU time 28.98 seconds
Started Oct 08 03:55:35 PM PDT 23
Finished Oct 08 03:56:05 PM PDT 23
Peak memory 211288 kb
Host smart-53999e97-f099-4b1c-b774-9115338f4f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322180987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.322180987
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1576888300
Short name T319
Test name
Test status
Simulation time 102241141 ps
CPU time 6.06 seconds
Started Oct 08 03:51:42 PM PDT 23
Finished Oct 08 03:51:48 PM PDT 23
Peak memory 210888 kb
Host smart-0cd14fb3-3bf7-4066-a634-f5210e77286a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1576888300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1576888300
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3826895528
Short name T292
Test name
Test status
Simulation time 17150711364 ps
CPU time 37.81 seconds
Started Oct 08 03:47:08 PM PDT 23
Finished Oct 08 03:47:46 PM PDT 23
Peak memory 213176 kb
Host smart-6deb40c5-4fdb-4e90-b1db-a8cffe6be1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826895528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3826895528
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3772556419
Short name T100
Test name
Test status
Simulation time 24187021019 ps
CPU time 57.25 seconds
Started Oct 08 03:48:51 PM PDT 23
Finished Oct 08 03:49:49 PM PDT 23
Peak memory 216868 kb
Host smart-c75aed49-54a8-4672-8297-9ec4f80ffef4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772556419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3772556419
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2111387031
Short name T396
Test name
Test status
Simulation time 64252977765 ps
CPU time 419.7 seconds
Started Oct 08 03:51:09 PM PDT 23
Finished Oct 08 03:58:09 PM PDT 23
Peak memory 233756 kb
Host smart-ad3a1ab8-0ac8-4717-aeb6-b221115c0197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111387031 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2111387031
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3642873575
Short name T216
Test name
Test status
Simulation time 7226263204 ps
CPU time 15.46 seconds
Started Oct 08 03:48:47 PM PDT 23
Finished Oct 08 03:49:03 PM PDT 23
Peak memory 211200 kb
Host smart-51aa5e78-0071-4a21-b86a-97aa7c3ec918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642873575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3642873575
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1922819171
Short name T294
Test name
Test status
Simulation time 43691701768 ps
CPU time 431.01 seconds
Started Oct 08 03:51:54 PM PDT 23
Finished Oct 08 03:59:05 PM PDT 23
Peak memory 234780 kb
Host smart-f9c3298b-1356-4eea-bd52-e0f3b1962d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922819171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1922819171
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1419563291
Short name T423
Test name
Test status
Simulation time 7872081607 ps
CPU time 30.94 seconds
Started Oct 08 03:48:03 PM PDT 23
Finished Oct 08 03:48:34 PM PDT 23
Peak memory 211516 kb
Host smart-b5f021ec-b31e-47c7-bbf9-210d817fc92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419563291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1419563291
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2827043609
Short name T171
Test name
Test status
Simulation time 26494393748 ps
CPU time 17.97 seconds
Started Oct 08 03:47:52 PM PDT 23
Finished Oct 08 03:48:11 PM PDT 23
Peak memory 211252 kb
Host smart-5a718e32-de0b-45f0-b89e-fa43f12aa7b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827043609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2827043609
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2520922497
Short name T331
Test name
Test status
Simulation time 3967934357 ps
CPU time 27.48 seconds
Started Oct 08 03:45:43 PM PDT 23
Finished Oct 08 03:46:10 PM PDT 23
Peak memory 213412 kb
Host smart-ff264d99-8e6c-4f97-9099-0d07423ff85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520922497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2520922497
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2005727573
Short name T205
Test name
Test status
Simulation time 24202232513 ps
CPU time 59.42 seconds
Started Oct 08 03:47:43 PM PDT 23
Finished Oct 08 03:48:43 PM PDT 23
Peak memory 216620 kb
Host smart-539933cc-28b6-488f-b85c-fdaa379a0e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005727573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2005727573
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2496459093
Short name T340
Test name
Test status
Simulation time 141634233265 ps
CPU time 1142.12 seconds
Started Oct 08 03:49:20 PM PDT 23
Finished Oct 08 04:08:22 PM PDT 23
Peak memory 235700 kb
Host smart-dc49f262-b354-47f3-ac3d-6a1a1591b390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496459093 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2496459093
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1421570069
Short name T385
Test name
Test status
Simulation time 991016143 ps
CPU time 10.54 seconds
Started Oct 08 03:50:26 PM PDT 23
Finished Oct 08 03:50:37 PM PDT 23
Peak memory 211068 kb
Host smart-29ef1e4e-ab3f-434c-a7d7-16c39024ef7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421570069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1421570069
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2196821375
Short name T282
Test name
Test status
Simulation time 47407784300 ps
CPU time 271.94 seconds
Started Oct 08 03:49:18 PM PDT 23
Finished Oct 08 03:53:51 PM PDT 23
Peak memory 237724 kb
Host smart-4bcc7c3b-4b03-4b94-9f4c-e63ab79e2a74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196821375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2196821375
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3971035952
Short name T407
Test name
Test status
Simulation time 255373526 ps
CPU time 11.52 seconds
Started Oct 08 03:54:17 PM PDT 23
Finished Oct 08 03:54:29 PM PDT 23
Peak memory 211124 kb
Host smart-7980456f-d552-4219-ba5b-630fbaf70219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971035952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3971035952
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1999394290
Short name T168
Test name
Test status
Simulation time 1927951721 ps
CPU time 8.89 seconds
Started Oct 08 03:49:55 PM PDT 23
Finished Oct 08 03:50:04 PM PDT 23
Peak memory 211004 kb
Host smart-d7a5862c-237d-4476-9749-e3f9f7ce8cb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1999394290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1999394290
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3233536629
Short name T417
Test name
Test status
Simulation time 26905562178 ps
CPU time 30.87 seconds
Started Oct 08 03:45:34 PM PDT 23
Finished Oct 08 03:46:05 PM PDT 23
Peak memory 213716 kb
Host smart-7e646ae1-2653-437d-b4b6-6ce515e6bf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233536629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3233536629
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2361443533
Short name T220
Test name
Test status
Simulation time 3426091815 ps
CPU time 36.43 seconds
Started Oct 08 03:49:19 PM PDT 23
Finished Oct 08 03:49:56 PM PDT 23
Peak memory 213896 kb
Host smart-911e4bed-45e6-4798-9fd2-ec04c0dce1a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361443533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2361443533
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1958443063
Short name T194
Test name
Test status
Simulation time 23896458606 ps
CPU time 1137.44 seconds
Started Oct 08 03:45:44 PM PDT 23
Finished Oct 08 04:04:42 PM PDT 23
Peak memory 235752 kb
Host smart-2a596f71-4c3f-4314-a612-cdb2ecad5284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958443063 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1958443063
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3001774101
Short name T151
Test name
Test status
Simulation time 1572817365 ps
CPU time 7.12 seconds
Started Oct 08 03:50:27 PM PDT 23
Finished Oct 08 03:50:34 PM PDT 23
Peak memory 211044 kb
Host smart-3a53ccf8-b6ac-4c06-b47d-ad12bbab014d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001774101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3001774101
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2145367823
Short name T426
Test name
Test status
Simulation time 41797539510 ps
CPU time 423.56 seconds
Started Oct 08 03:45:13 PM PDT 23
Finished Oct 08 03:52:16 PM PDT 23
Peak memory 237696 kb
Host smart-ddfe57be-f1be-4ed9-8ce7-5c01c12492aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145367823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2145367823
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.670777771
Short name T326
Test name
Test status
Simulation time 538765078 ps
CPU time 9.38 seconds
Started Oct 08 03:54:04 PM PDT 23
Finished Oct 08 03:54:14 PM PDT 23
Peak memory 210464 kb
Host smart-0893d106-0236-4175-8066-5e931d65608d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670777771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.670777771
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.483414622
Short name T197
Test name
Test status
Simulation time 6875449815 ps
CPU time 16.02 seconds
Started Oct 08 03:46:54 PM PDT 23
Finished Oct 08 03:47:12 PM PDT 23
Peak memory 211012 kb
Host smart-fb4fb2ec-8f50-473d-96fe-41ad3c5b7456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483414622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.483414622
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2272179921
Short name T165
Test name
Test status
Simulation time 13847503952 ps
CPU time 31.08 seconds
Started Oct 08 03:52:09 PM PDT 23
Finished Oct 08 03:52:40 PM PDT 23
Peak memory 213764 kb
Host smart-4aa41ce1-36e2-4ba9-9321-ab9695f05deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272179921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2272179921
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1085542165
Short name T258
Test name
Test status
Simulation time 222743581 ps
CPU time 5.73 seconds
Started Oct 08 03:46:18 PM PDT 23
Finished Oct 08 03:46:24 PM PDT 23
Peak memory 211056 kb
Host smart-fdad6e57-942d-4ec3-90fc-60d254097b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085542165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1085542165
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.295367776
Short name T246
Test name
Test status
Simulation time 55839108790 ps
CPU time 4822.35 seconds
Started Oct 08 03:49:53 PM PDT 23
Finished Oct 08 05:10:16 PM PDT 23
Peak memory 230788 kb
Host smart-37e76436-3705-4c06-8be9-1f22ab457e20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295367776 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.295367776
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2680943221
Short name T234
Test name
Test status
Simulation time 1148948164 ps
CPU time 10.81 seconds
Started Oct 08 03:46:14 PM PDT 23
Finished Oct 08 03:46:25 PM PDT 23
Peak memory 210952 kb
Host smart-66ac448c-ca51-4455-8a7c-22e57fe30ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680943221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2680943221
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2143437386
Short name T286
Test name
Test status
Simulation time 114946417890 ps
CPU time 292.08 seconds
Started Oct 08 03:50:26 PM PDT 23
Finished Oct 08 03:55:18 PM PDT 23
Peak memory 237744 kb
Host smart-da0553e0-4ae0-46bf-a323-18bbdb7973ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143437386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2143437386
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2047717825
Short name T188
Test name
Test status
Simulation time 2634247748 ps
CPU time 25.97 seconds
Started Oct 08 03:50:34 PM PDT 23
Finished Oct 08 03:51:00 PM PDT 23
Peak memory 211396 kb
Host smart-58d45006-c702-4730-92f9-09706e57cb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047717825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2047717825
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.81219101
Short name T344
Test name
Test status
Simulation time 192808601 ps
CPU time 5.78 seconds
Started Oct 08 03:50:28 PM PDT 23
Finished Oct 08 03:50:34 PM PDT 23
Peak memory 211028 kb
Host smart-517aec5b-f1fe-446b-96bf-36bb75853688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81219101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.81219101
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.587793903
Short name T300
Test name
Test status
Simulation time 6604577161 ps
CPU time 28.96 seconds
Started Oct 08 03:46:06 PM PDT 23
Finished Oct 08 03:46:36 PM PDT 23
Peak memory 214188 kb
Host smart-b4c180b5-0761-428a-9ef2-fedf75c2ab46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587793903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.587793903
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1710657083
Short name T199
Test name
Test status
Simulation time 23707405225 ps
CPU time 103.49 seconds
Started Oct 08 03:46:14 PM PDT 23
Finished Oct 08 03:47:58 PM PDT 23
Peak memory 219272 kb
Host smart-afe8a14b-95e8-41d3-a1df-642f09915c0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710657083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1710657083
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.839353943
Short name T395
Test name
Test status
Simulation time 1675912556 ps
CPU time 14.48 seconds
Started Oct 08 03:45:43 PM PDT 23
Finished Oct 08 03:45:58 PM PDT 23
Peak memory 210916 kb
Host smart-e7f1e657-b5f4-4fd6-9b21-c1879e94c103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839353943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.839353943
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3667690556
Short name T62
Test name
Test status
Simulation time 8790780825 ps
CPU time 149.59 seconds
Started Oct 08 03:54:04 PM PDT 23
Finished Oct 08 03:56:34 PM PDT 23
Peak memory 226836 kb
Host smart-ece93eb8-b253-4cb6-b65d-e477291db90f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667690556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3667690556
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2693671925
Short name T162
Test name
Test status
Simulation time 4023951756 ps
CPU time 32.32 seconds
Started Oct 08 03:45:45 PM PDT 23
Finished Oct 08 03:46:18 PM PDT 23
Peak memory 211364 kb
Host smart-57c58c0c-902d-485e-9da3-078810473ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693671925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2693671925
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.502895339
Short name T373
Test name
Test status
Simulation time 895945069 ps
CPU time 10.46 seconds
Started Oct 08 03:46:48 PM PDT 23
Finished Oct 08 03:47:01 PM PDT 23
Peak memory 210936 kb
Host smart-d2ed7347-7169-4b7a-9d4b-4eac105da15a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502895339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.502895339
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2466523745
Short name T53
Test name
Test status
Simulation time 1010432867 ps
CPU time 11.85 seconds
Started Oct 08 03:47:56 PM PDT 23
Finished Oct 08 03:48:09 PM PDT 23
Peak memory 212788 kb
Host smart-ccb3b7fe-ba1f-46cc-b2b1-85bbc3b69b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466523745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2466523745
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2489243185
Short name T339
Test name
Test status
Simulation time 1515607554 ps
CPU time 16.71 seconds
Started Oct 08 03:55:40 PM PDT 23
Finished Oct 08 03:55:59 PM PDT 23
Peak memory 211060 kb
Host smart-12846180-9cd2-4426-b2c9-711d3dae0979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489243185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2489243185
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1881258765
Short name T167
Test name
Test status
Simulation time 2289319473 ps
CPU time 16.19 seconds
Started Oct 08 03:47:03 PM PDT 23
Finished Oct 08 03:47:19 PM PDT 23
Peak memory 211144 kb
Host smart-2c63527f-cbb7-48da-87a9-07b39e9521be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881258765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1881258765
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1276144967
Short name T424
Test name
Test status
Simulation time 64909359176 ps
CPU time 332.24 seconds
Started Oct 08 03:48:06 PM PDT 23
Finished Oct 08 03:53:39 PM PDT 23
Peak memory 236640 kb
Host smart-37f1d460-2662-4aab-adb8-9ac9e86c08e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276144967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1276144967
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2579180994
Short name T13
Test name
Test status
Simulation time 504757283 ps
CPU time 9.81 seconds
Started Oct 08 03:47:01 PM PDT 23
Finished Oct 08 03:47:11 PM PDT 23
Peak memory 211216 kb
Host smart-b6e21d38-66d2-40d2-bdac-20ac2e482446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579180994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2579180994
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3483622764
Short name T299
Test name
Test status
Simulation time 3261260443 ps
CPU time 16.57 seconds
Started Oct 08 03:47:02 PM PDT 23
Finished Oct 08 03:47:19 PM PDT 23
Peak memory 211188 kb
Host smart-f70bb247-60a9-4db8-963e-e923efe0d5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483622764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3483622764
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1715910175
Short name T160
Test name
Test status
Simulation time 4379109733 ps
CPU time 43.7 seconds
Started Oct 08 03:54:55 PM PDT 23
Finished Oct 08 03:55:39 PM PDT 23
Peak memory 212580 kb
Host smart-ea8cea15-fbaf-4d74-a78b-879eaa7ba18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715910175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1715910175
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1046192900
Short name T411
Test name
Test status
Simulation time 6893680032 ps
CPU time 73.82 seconds
Started Oct 08 03:54:58 PM PDT 23
Finished Oct 08 03:56:12 PM PDT 23
Peak memory 216888 kb
Host smart-cb1a25d3-fcbd-41f2-aad6-16f715db56c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046192900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1046192900
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2733147438
Short name T427
Test name
Test status
Simulation time 80229074966 ps
CPU time 3192.15 seconds
Started Oct 08 03:47:01 PM PDT 23
Finished Oct 08 04:40:14 PM PDT 23
Peak memory 252124 kb
Host smart-50c79097-d705-43d3-a7c0-b85ced61fdfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733147438 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2733147438
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1486841212
Short name T14
Test name
Test status
Simulation time 9362723274 ps
CPU time 16.15 seconds
Started Oct 08 03:46:29 PM PDT 23
Finished Oct 08 03:46:45 PM PDT 23
Peak memory 211024 kb
Host smart-83ba497a-45e1-4faa-9ac7-879d548f8501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486841212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1486841212
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3670086992
Short name T276
Test name
Test status
Simulation time 33789061587 ps
CPU time 320.39 seconds
Started Oct 08 03:52:41 PM PDT 23
Finished Oct 08 03:58:02 PM PDT 23
Peak memory 224568 kb
Host smart-532556fe-55fe-41fc-a04d-b6a3055035c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670086992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3670086992
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1556957451
Short name T172
Test name
Test status
Simulation time 3004526948 ps
CPU time 14.46 seconds
Started Oct 08 03:46:42 PM PDT 23
Finished Oct 08 03:46:56 PM PDT 23
Peak memory 211100 kb
Host smart-7df9a323-5761-4804-837d-62297169a578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556957451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1556957451
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2689399159
Short name T157
Test name
Test status
Simulation time 3950475588 ps
CPU time 16.96 seconds
Started Oct 08 03:44:36 PM PDT 23
Finished Oct 08 03:44:53 PM PDT 23
Peak memory 211064 kb
Host smart-1ffbfa74-2ab2-4996-9bb7-acf77c301935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2689399159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2689399159
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.347757476
Short name T173
Test name
Test status
Simulation time 8516960521 ps
CPU time 36.33 seconds
Started Oct 08 03:50:40 PM PDT 23
Finished Oct 08 03:51:16 PM PDT 23
Peak memory 214112 kb
Host smart-fdd60c42-ef75-4320-8cb2-0a5c624addfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347757476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.347757476
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2939522404
Short name T275
Test name
Test status
Simulation time 663527108 ps
CPU time 12.7 seconds
Started Oct 08 03:55:51 PM PDT 23
Finished Oct 08 03:56:04 PM PDT 23
Peak memory 211584 kb
Host smart-1a722bee-571d-4935-82e0-89569af85e5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939522404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2939522404
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.10804815
Short name T362
Test name
Test status
Simulation time 1839376120 ps
CPU time 15.39 seconds
Started Oct 08 03:44:38 PM PDT 23
Finished Oct 08 03:44:53 PM PDT 23
Peak memory 210976 kb
Host smart-89f7fac1-5d7f-4b98-8f01-bf00bfac7371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10804815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.10804815
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.909121636
Short name T60
Test name
Test status
Simulation time 8595302926 ps
CPU time 123.99 seconds
Started Oct 08 03:55:12 PM PDT 23
Finished Oct 08 03:57:17 PM PDT 23
Peak memory 237004 kb
Host smart-9e83a7f7-47f0-4fac-9c96-a95d95ebe95f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909121636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.909121636
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4111909400
Short name T390
Test name
Test status
Simulation time 13927613847 ps
CPU time 32.07 seconds
Started Oct 08 03:49:54 PM PDT 23
Finished Oct 08 03:50:26 PM PDT 23
Peak memory 211620 kb
Host smart-19ee9e1a-5e53-44f7-8bdc-8047330f59a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111909400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4111909400
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1987998664
Short name T419
Test name
Test status
Simulation time 5951968646 ps
CPU time 14.15 seconds
Started Oct 08 03:53:34 PM PDT 23
Finished Oct 08 03:53:49 PM PDT 23
Peak memory 211188 kb
Host smart-9019ddf5-c829-4dba-a520-6c4d6bc2492d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987998664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1987998664
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.224640903
Short name T406
Test name
Test status
Simulation time 17147045567 ps
CPU time 36.21 seconds
Started Oct 08 03:55:58 PM PDT 23
Finished Oct 08 03:56:34 PM PDT 23
Peak memory 213192 kb
Host smart-8905c198-06bd-4f56-8a45-dfbbd8f776b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224640903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.224640903
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3111683498
Short name T428
Test name
Test status
Simulation time 23435741087 ps
CPU time 51.89 seconds
Started Oct 08 03:54:56 PM PDT 23
Finished Oct 08 03:55:48 PM PDT 23
Peak memory 216504 kb
Host smart-040be2b2-9566-4e84-8e45-f415ef5fb9f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111683498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3111683498
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1743831342
Short name T401
Test name
Test status
Simulation time 8653373110 ps
CPU time 15.84 seconds
Started Oct 08 03:49:56 PM PDT 23
Finished Oct 08 03:50:12 PM PDT 23
Peak memory 211128 kb
Host smart-40b1d778-3c12-4b26-acc6-c9f345eb9496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743831342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1743831342
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1366123444
Short name T271
Test name
Test status
Simulation time 220673035245 ps
CPU time 476.23 seconds
Started Oct 08 03:43:52 PM PDT 23
Finished Oct 08 03:51:48 PM PDT 23
Peak memory 212364 kb
Host smart-6deef171-4227-404c-a38e-0e25254d195b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366123444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1366123444
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.897168301
Short name T181
Test name
Test status
Simulation time 1017367627 ps
CPU time 16.29 seconds
Started Oct 08 03:42:54 PM PDT 23
Finished Oct 08 03:43:11 PM PDT 23
Peak memory 211088 kb
Host smart-b5678026-449b-494e-bd44-67c65734e956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897168301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.897168301
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1870334243
Short name T415
Test name
Test status
Simulation time 466875385 ps
CPU time 5.7 seconds
Started Oct 08 03:44:45 PM PDT 23
Finished Oct 08 03:44:51 PM PDT 23
Peak memory 211012 kb
Host smart-4a5d3263-9633-48c6-9a42-e3d1b7629d56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870334243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1870334243
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1798113868
Short name T206
Test name
Test status
Simulation time 748283257 ps
CPU time 10.42 seconds
Started Oct 08 03:51:40 PM PDT 23
Finished Oct 08 03:51:50 PM PDT 23
Peak memory 212628 kb
Host smart-86316186-43d5-4b2e-af43-7c2fa95dd8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798113868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1798113868
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4009826670
Short name T296
Test name
Test status
Simulation time 119173105 ps
CPU time 7.99 seconds
Started Oct 08 03:52:56 PM PDT 23
Finished Oct 08 03:53:05 PM PDT 23
Peak memory 211352 kb
Host smart-ed30fd7d-6ff0-45db-8aa5-b1f234bc5f7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009826670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4009826670
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2987937004
Short name T184
Test name
Test status
Simulation time 6603534973 ps
CPU time 13.43 seconds
Started Oct 08 03:51:49 PM PDT 23
Finished Oct 08 03:52:03 PM PDT 23
Peak memory 211200 kb
Host smart-266023ee-b2d6-4a68-940f-5a4a031a45ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987937004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2987937004
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2971364211
Short name T262
Test name
Test status
Simulation time 231480808178 ps
CPU time 510.97 seconds
Started Oct 08 03:53:59 PM PDT 23
Finished Oct 08 04:02:31 PM PDT 23
Peak memory 224496 kb
Host smart-873be612-8be5-4507-a696-aed165fb3bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971364211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2971364211
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2714709837
Short name T350
Test name
Test status
Simulation time 7347079378 ps
CPU time 30.76 seconds
Started Oct 08 03:54:04 PM PDT 23
Finished Oct 08 03:54:35 PM PDT 23
Peak memory 212804 kb
Host smart-d96dfa84-db4f-4487-a17e-3124f1604412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714709837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2714709837
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1867952399
Short name T416
Test name
Test status
Simulation time 2188640567 ps
CPU time 9.19 seconds
Started Oct 08 03:53:59 PM PDT 23
Finished Oct 08 03:54:09 PM PDT 23
Peak memory 211140 kb
Host smart-a74c529f-f181-46f2-a545-194d2c6acf5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867952399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1867952399
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3832176412
Short name T6
Test name
Test status
Simulation time 184829386 ps
CPU time 10.57 seconds
Started Oct 08 03:46:37 PM PDT 23
Finished Oct 08 03:46:48 PM PDT 23
Peak memory 212624 kb
Host smart-b29e3903-04ec-4153-ae80-dc588257f548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832176412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3832176412
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3386251373
Short name T217
Test name
Test status
Simulation time 237884845 ps
CPU time 7.81 seconds
Started Oct 08 03:42:55 PM PDT 23
Finished Oct 08 03:43:03 PM PDT 23
Peak memory 211684 kb
Host smart-9ef9e358-f913-4efc-9746-613b741b1338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386251373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3386251373
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3744527666
Short name T323
Test name
Test status
Simulation time 44963380732 ps
CPU time 1059.46 seconds
Started Oct 08 03:44:58 PM PDT 23
Finished Oct 08 04:02:38 PM PDT 23
Peak memory 227752 kb
Host smart-f0e849af-6068-4381-b9d4-707ad5af9f8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744527666 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3744527666
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1318533757
Short name T54
Test name
Test status
Simulation time 8186814688 ps
CPU time 16.46 seconds
Started Oct 08 03:44:01 PM PDT 23
Finished Oct 08 03:44:17 PM PDT 23
Peak memory 211168 kb
Host smart-02112cfd-a7fb-4513-b672-e81e219710ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318533757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1318533757
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.455312454
Short name T402
Test name
Test status
Simulation time 72537823529 ps
CPU time 272.02 seconds
Started Oct 08 03:54:04 PM PDT 23
Finished Oct 08 03:58:36 PM PDT 23
Peak memory 234188 kb
Host smart-8af03045-e44b-4f8a-9bc2-7843b38402d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455312454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.455312454
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1167796057
Short name T356
Test name
Test status
Simulation time 7855414393 ps
CPU time 23.46 seconds
Started Oct 08 03:42:57 PM PDT 23
Finished Oct 08 03:43:21 PM PDT 23
Peak memory 211776 kb
Host smart-39cdf67f-f11e-45ec-bc87-8a424a6ac60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167796057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1167796057
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.952553837
Short name T320
Test name
Test status
Simulation time 6345730079 ps
CPU time 10.73 seconds
Started Oct 08 03:42:59 PM PDT 23
Finished Oct 08 03:43:10 PM PDT 23
Peak memory 211184 kb
Host smart-36a85359-7509-40ce-b46f-848842b128bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952553837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.952553837
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1273017233
Short name T90
Test name
Test status
Simulation time 4333778464 ps
CPU time 38.36 seconds
Started Oct 08 03:46:50 PM PDT 23
Finished Oct 08 03:47:29 PM PDT 23
Peak memory 213440 kb
Host smart-b2d75a94-d1f2-494f-928e-f0b37cbb9ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273017233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1273017233
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2640413925
Short name T198
Test name
Test status
Simulation time 5985772080 ps
CPU time 22.34 seconds
Started Oct 08 03:46:51 PM PDT 23
Finished Oct 08 03:47:14 PM PDT 23
Peak memory 216364 kb
Host smart-169b0c8c-b016-4e09-b29f-971cb36a0127
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640413925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2640413925
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2391844003
Short name T366
Test name
Test status
Simulation time 2974366781 ps
CPU time 9.15 seconds
Started Oct 08 03:46:43 PM PDT 23
Finished Oct 08 03:46:52 PM PDT 23
Peak memory 211216 kb
Host smart-71369adf-5133-4c92-b38e-6ecda1a77412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391844003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2391844003
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1224633246
Short name T431
Test name
Test status
Simulation time 13063269603 ps
CPU time 147.69 seconds
Started Oct 08 03:47:47 PM PDT 23
Finished Oct 08 03:50:15 PM PDT 23
Peak memory 237680 kb
Host smart-30fce895-feca-4e52-8641-4e133a4bfa51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224633246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1224633246
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.294247023
Short name T308
Test name
Test status
Simulation time 438071238 ps
CPU time 9.7 seconds
Started Oct 08 03:44:00 PM PDT 23
Finished Oct 08 03:44:10 PM PDT 23
Peak memory 211232 kb
Host smart-3e844018-d1dd-4aa8-95bb-83c18f3b556d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294247023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.294247023
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1185178819
Short name T187
Test name
Test status
Simulation time 1190900984 ps
CPU time 11.86 seconds
Started Oct 08 03:47:04 PM PDT 23
Finished Oct 08 03:47:16 PM PDT 23
Peak memory 210964 kb
Host smart-9e2cb3ac-c14e-4f61-9d19-76271cfc669b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185178819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1185178819
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2546423777
Short name T175
Test name
Test status
Simulation time 5917526443 ps
CPU time 31.43 seconds
Started Oct 08 03:43:49 PM PDT 23
Finished Oct 08 03:44:21 PM PDT 23
Peak memory 213496 kb
Host smart-76b83539-2b30-4ec7-909b-e08a6785f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546423777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2546423777
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.109571521
Short name T156
Test name
Test status
Simulation time 42652173481 ps
CPU time 84.81 seconds
Started Oct 08 03:47:04 PM PDT 23
Finished Oct 08 03:48:29 PM PDT 23
Peak memory 219308 kb
Host smart-e7326649-2699-42d0-acbd-5c25a1825786
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109571521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.109571521
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3897032909
Short name T255
Test name
Test status
Simulation time 58568415892 ps
CPU time 1720.32 seconds
Started Oct 08 03:53:41 PM PDT 23
Finished Oct 08 04:22:22 PM PDT 23
Peak memory 233808 kb
Host smart-ae29df8d-02de-4aea-9c26-368981d37030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897032909 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3897032909
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1309850955
Short name T266
Test name
Test status
Simulation time 1401137385 ps
CPU time 12.67 seconds
Started Oct 08 03:45:06 PM PDT 23
Finished Oct 08 03:45:19 PM PDT 23
Peak memory 211044 kb
Host smart-a49c5e5e-bf93-4b7a-b720-3ae969f2e301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309850955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1309850955
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1454564005
Short name T61
Test name
Test status
Simulation time 111724864450 ps
CPU time 335.93 seconds
Started Oct 08 03:44:24 PM PDT 23
Finished Oct 08 03:50:00 PM PDT 23
Peak memory 237684 kb
Host smart-79bfd8dd-b098-46da-8d18-184887c4cadf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454564005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1454564005
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1849047309
Short name T421
Test name
Test status
Simulation time 173933538 ps
CPU time 9.87 seconds
Started Oct 08 03:43:40 PM PDT 23
Finished Oct 08 03:43:50 PM PDT 23
Peak memory 211212 kb
Host smart-09782dd1-67bd-428a-a0ce-6d1ddb63bcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849047309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1849047309
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1649127690
Short name T312
Test name
Test status
Simulation time 1918406742 ps
CPU time 8.29 seconds
Started Oct 08 03:50:22 PM PDT 23
Finished Oct 08 03:50:30 PM PDT 23
Peak memory 211092 kb
Host smart-cbc8bd2b-92f3-4b29-938d-edeb82fb3d69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649127690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1649127690
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1199948336
Short name T358
Test name
Test status
Simulation time 193903742 ps
CPU time 10.69 seconds
Started Oct 08 03:44:01 PM PDT 23
Finished Oct 08 03:44:12 PM PDT 23
Peak memory 212600 kb
Host smart-d19d611e-25da-48d1-bf94-fc9387a90d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199948336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1199948336
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4122917690
Short name T189
Test name
Test status
Simulation time 1544926086 ps
CPU time 7.76 seconds
Started Oct 08 03:46:44 PM PDT 23
Finished Oct 08 03:46:52 PM PDT 23
Peak memory 210856 kb
Host smart-5d125529-2a93-4541-b1ee-3a1cf0647ec0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122917690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4122917690
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3662327002
Short name T219
Test name
Test status
Simulation time 308820598683 ps
CPU time 3621.25 seconds
Started Oct 08 03:43:01 PM PDT 23
Finished Oct 08 04:43:23 PM PDT 23
Peak memory 237008 kb
Host smart-16b444de-04a5-4f03-8df9-bb3cb54ab83b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662327002 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3662327002
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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