Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 230045 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2374916 1 T21 250 T28 162 T29 103



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 647229 1 T21 34 T28 62 T29 24
values[0x0] 906548 1 T21 105 T28 75 T29 43
values[0x1] 1051184 1 T21 111 T28 99 T29 41



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 100839 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2504122 1 T21 250 T28 189 T29 104



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 10352 1 T28 2 T32 1 T34 3
valid_sources[0x01] 10348 1 T28 1 T29 2 T32 1
valid_sources[0x02] 10034 1 T32 3 T34 2 T36 1
valid_sources[0x03] 9562 1 T28 3 T29 1 T34 2
valid_sources[0x04] 9874 1 T32 1 T34 5 T35 1
valid_sources[0x05] 10231 1 T29 3 T33 10 T35 2
valid_sources[0x06] 10564 1 T21 4 T28 1 T34 4
valid_sources[0x07] 9902 1 T32 4 T34 3 T36 2
valid_sources[0x08] 9954 1 T29 1 T34 2 T51 1
valid_sources[0x09] 9556 1 T32 2 T34 2 T58 3
valid_sources[0x0a] 9816 1 T28 2 T29 1 T32 1
valid_sources[0x0b] 9536 1 T34 1 T35 2 T40 4
valid_sources[0x0c] 9637 1 T28 1 T32 3 T34 1
valid_sources[0x0d] 9926 1 T21 3 T28 1 T40 2
valid_sources[0x0e] 11099 1 T28 2 T34 2 T35 2
valid_sources[0x0f] 10679 1 T21 4 T34 3 T40 1
valid_sources[0x10] 10627 1 T29 1 T36 1 T40 1
valid_sources[0x11] 10283 1 T34 3 T40 6 T58 1
valid_sources[0x12] 9919 1 T28 1 T34 1 T40 1
valid_sources[0x13] 10374 1 T28 4 T29 1 T32 1
valid_sources[0x14] 9680 1 T32 2 T34 1 T40 3
valid_sources[0x15] 10260 1 T28 1 T32 2 T34 1
valid_sources[0x16] 10486 1 T21 1 T29 1 T36 1
valid_sources[0x17] 9416 1 T21 2 T34 6 T54 2
valid_sources[0x18] 11417 1 T21 3 T28 1 T34 1
valid_sources[0x19] 9756 1 T21 1 T34 2 T40 2
valid_sources[0x1a] 10816 1 T28 2 T29 2 T32 1
valid_sources[0x1b] 10362 1 T29 1 T32 3 T34 1
valid_sources[0x1c] 10331 1 T29 1 T32 2 T40 1
valid_sources[0x1d] 10779 1 T29 1 T34 2 T40 4
valid_sources[0x1e] 9904 1 T28 5 T33 10 T34 1
valid_sources[0x1f] 10051 1 T28 9 T32 2 T34 1
valid_sources[0x20] 10682 1 T28 7 T32 3 T40 4
valid_sources[0x21] 9670 1 T35 1 T65 1 T54 1
valid_sources[0x22] 10888 1 T21 3 T32 3 T34 1
valid_sources[0x23] 9294 1 T32 2 T34 2 T40 6
valid_sources[0x24] 10567 1 T28 1 T34 2 T40 2
valid_sources[0x25] 9920 1 T21 2 T29 1 T32 1
valid_sources[0x26] 10069 1 T21 1 T34 2 T40 6
valid_sources[0x27] 10257 1 T21 1 T28 1 T29 3
valid_sources[0x28] 9735 1 T28 2 T36 1 T40 2
valid_sources[0x29] 10367 1 T28 1 T32 2 T36 2
valid_sources[0x2a] 10180 1 T29 1 T32 2 T34 1
valid_sources[0x2b] 11225 1 T32 9 T36 6 T40 3
valid_sources[0x2c] 10000 1 T34 3 T40 3 T58 1
valid_sources[0x2d] 10309 1 T32 2 T33 10 T34 3
valid_sources[0x2e] 9135 1 T28 4 T29 1 T32 4
valid_sources[0x2f] 9613 1 T28 1 T29 1 T32 1
valid_sources[0x30] 9841 1 T21 8 T28 4 T32 5
valid_sources[0x31] 10195 1 T32 1 T33 18 T34 3
valid_sources[0x32] 10135 1 T28 3 T32 1 T34 5
valid_sources[0x33] 9880 1 T21 1 T29 1 T32 1
valid_sources[0x34] 10812 1 T21 4 T28 1 T34 1
valid_sources[0x35] 10566 1 T28 2 T32 1 T34 1
valid_sources[0x36] 10140 1 T21 1 T29 1 T33 31
valid_sources[0x37] 9996 1 T21 8 T32 5 T34 1
valid_sources[0x38] 10172 1 T21 1 T28 2 T32 1
valid_sources[0x39] 10636 1 T32 1 T34 1 T36 1
valid_sources[0x3a] 10020 1 T28 1 T34 3 T35 2
valid_sources[0x3b] 10303 1 T21 2 T28 1 T29 1
valid_sources[0x3c] 9984 1 T32 1 T34 2 T35 1
valid_sources[0x3d] 10621 1 T28 1 T32 2 T34 1
valid_sources[0x3e] 10455 1 T32 8 T34 3 T35 1
valid_sources[0x3f] 9577 1 T28 1 T33 7 T34 3
valid_sources[0x40] 9646 1 T33 10 T34 2 T40 1
valid_sources[0x41] 10701 1 T21 2 T32 1 T34 1
valid_sources[0x42] 10001 1 T29 1 T40 3 T68 1
valid_sources[0x43] 9938 1 T32 3 T36 1 T40 2
valid_sources[0x44] 9796 1 T28 2 T32 3 T34 2
valid_sources[0x45] 9703 1 T21 1 T55 1 T67 1
valid_sources[0x46] 10736 1 T21 1 T34 2 T40 1
valid_sources[0x47] 10096 1 T21 4 T28 3 T34 4
valid_sources[0x48] 10271 1 T21 2 T28 5 T32 2
valid_sources[0x49] 10109 1 T34 2 T40 2 T65 1
valid_sources[0x4a] 9602 1 T28 2 T35 1 T40 1
valid_sources[0x4b] 10514 1 T28 1 T32 1 T34 2
valid_sources[0x4c] 11498 1 T21 1 T32 3 T34 5
valid_sources[0x4d] 10227 1 T28 2 T34 3 T40 2
valid_sources[0x4e] 10820 1 T28 4 T29 1 T32 1
valid_sources[0x4f] 9769 1 T32 5 T34 1 T36 1
valid_sources[0x50] 10068 1 T32 2 T34 1 T35 2
valid_sources[0x51] 9127 1 T32 1 T68 2 T57 3
valid_sources[0x52] 10784 1 T21 1 T29 1 T32 3
valid_sources[0x53] 10187 1 T29 2 T32 2 T40 2
valid_sources[0x54] 10212 1 T21 1 T28 1 T29 1
valid_sources[0x55] 10305 1 T32 3 T34 3 T58 3
valid_sources[0x56] 9447 1 T28 1 T34 1 T65 1
valid_sources[0x57] 9948 1 T28 1 T32 1 T40 2
valid_sources[0x58] 9841 1 T32 2 T34 3 T40 2
valid_sources[0x59] 10293 1 T32 1 T33 10 T36 2
valid_sources[0x5a] 10240 1 T28 1 T32 9 T34 1
valid_sources[0x5b] 9138 1 T21 3 T28 1 T29 3
valid_sources[0x5c] 9758 1 T21 4 T32 8 T34 4
valid_sources[0x5d] 10175 1 T21 9 T29 1 T32 2
valid_sources[0x5e] 10115 1 T29 1 T32 2 T34 2
valid_sources[0x5f] 10034 1 T34 2 T40 1 T54 1
valid_sources[0x60] 9437 1 T21 1 T29 1 T34 2
valid_sources[0x61] 9926 1 T21 1 T28 3 T29 2
valid_sources[0x62] 10639 1 T21 5 T28 1 T34 2
valid_sources[0x63] 10168 1 T21 4 T28 1 T32 4
valid_sources[0x64] 10261 1 T28 3 T33 10 T40 3
valid_sources[0x65] 10203 1 T21 1 T32 7 T34 2
valid_sources[0x66] 10280 1 T28 4 T29 1 T32 1
valid_sources[0x67] 10119 1 T28 2 T32 4 T34 2
valid_sources[0x68] 10361 1 T21 2 T32 3 T34 2
valid_sources[0x69] 9967 1 T21 3 T28 3 T32 2
valid_sources[0x6a] 10401 1 T29 1 T32 1 T34 3
valid_sources[0x6b] 10990 1 T21 3 T29 4 T32 1
valid_sources[0x6c] 10987 1 T34 1 T35 2 T40 5
valid_sources[0x6d] 9599 1 T32 1 T34 1 T36 2
valid_sources[0x6e] 9855 1 T28 1 T29 1 T34 1
valid_sources[0x6f] 10082 1 T32 7 T34 1 T36 8
valid_sources[0x70] 10029 1 T28 2 T29 1 T33 8
valid_sources[0x71] 11261 1 T21 2 T29 1 T32 3
valid_sources[0x72] 10478 1 T21 1 T29 2 T32 3
valid_sources[0x73] 9704 1 T21 1 T32 3 T34 1
valid_sources[0x74] 10592 1 T21 4 T32 1 T33 10
valid_sources[0x75] 10691 1 T28 1 T32 1 T34 3
valid_sources[0x76] 10245 1 T28 1 T29 1 T34 1
valid_sources[0x77] 9368 1 T29 1 T34 1 T40 4
valid_sources[0x78] 10507 1 T28 2 T32 1 T34 1
valid_sources[0x79] 10313 1 T34 2 T40 4 T54 3
valid_sources[0x7a] 9700 1 T29 2 T32 6 T34 1
valid_sources[0x7b] 10091 1 T29 3 T33 12 T34 1
valid_sources[0x7c] 10340 1 T33 20 T34 1 T35 2
valid_sources[0x7d] 9984 1 T21 2 T29 2 T32 8
valid_sources[0x7e] 9457 1 T28 2 T34 2 T35 1
valid_sources[0x7f] 10237 1 T21 1 T28 3 T29 1
valid_sources[0x80] 9605 1 T21 2 T28 1 T29 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 599497 1 T21 34 T28 5 T29 21
values[0x0] all_enables biggest_size 888342 1 T21 105 T28 68 T29 43
values[0x1] all_enables biggest_size 887077 1 T21 111 T28 89 T29 39


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 528643 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2346970 1 T29 14 T32 40 T33 40



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 639447 1 T28 4 T29 4 T32 40
values[0x0] 923163 1 T29 7 T36 77 T40 2
values[0x1] 1313003 1 T28 4 T29 11 T36 92



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 199843 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2675770 1 T28 6 T29 17 T32 40



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 10446 1 T57 5 T78 1 T118 2
valid_sources[0x01] 10256 1 T57 7 T118 2 T119 5
valid_sources[0x02] 11511 1 T61 1 T57 3 T118 1
valid_sources[0x03] 11192 1 T61 2 T75 1 T57 2
valid_sources[0x04] 12511 1 T33 2 T57 3 T62 1
valid_sources[0x05] 11277 1 T57 4 T77 25 T78 2
valid_sources[0x06] 12501 1 T54 1 T68 1 T57 4
valid_sources[0x07] 12203 1 T61 1 T57 4 T78 2
valid_sources[0x08] 12053 1 T29 1 T57 6 T109 1
valid_sources[0x09] 11614 1 T32 4 T57 7 T77 12
valid_sources[0x0a] 11557 1 T34 2 T61 1 T57 8
valid_sources[0x0b] 11328 1 T53 1 T54 3 T57 5
valid_sources[0x0c] 11178 1 T28 8 T68 2 T57 5
valid_sources[0x0d] 8849 1 T57 3 T62 1 T76 1
valid_sources[0x0e] 9400 1 T59 1 T68 2 T57 5
valid_sources[0x0f] 10398 1 T61 1 T57 5 T77 1
valid_sources[0x10] 9565 1 T57 4 T118 4 T120 9
valid_sources[0x11] 9239 1 T68 1 T57 4 T76 3
valid_sources[0x12] 10914 1 T61 1 T57 4 T62 1
valid_sources[0x13] 11167 1 T57 3 T62 1 T78 1
valid_sources[0x14] 10077 1 T53 1 T59 1 T57 1
valid_sources[0x15] 9925 1 T68 1 T57 1 T62 1
valid_sources[0x16] 10495 1 T59 2 T57 3 T77 14
valid_sources[0x17] 12216 1 T68 1 T57 5 T62 2
valid_sources[0x18] 12013 1 T29 1 T54 1 T61 1
valid_sources[0x19] 10919 1 T57 1 T78 1 T118 4
valid_sources[0x1a] 12062 1 T118 1 T121 2 T120 6
valid_sources[0x1b] 12078 1 T57 5 T62 1 T76 2
valid_sources[0x1c] 11581 1 T57 4 T78 1 T109 2
valid_sources[0x1d] 9306 1 T54 3 T68 1 T75 1
valid_sources[0x1e] 13874 1 T29 1 T53 1 T56 1
valid_sources[0x1f] 11956 1 T56 1 T57 2 T118 3
valid_sources[0x20] 11974 1 T33 5 T68 1 T57 4
valid_sources[0x21] 10669 1 T36 101 T57 8 T63 1
valid_sources[0x22] 11612 1 T57 2 T62 1 T118 1
valid_sources[0x23] 11725 1 T52 8 T57 6 T118 1
valid_sources[0x24] 10819 1 T57 5 T78 1 T121 1
valid_sources[0x25] 11693 1 T55 1 T59 1 T57 5
valid_sources[0x26] 12514 1 T33 4 T56 1 T57 5
valid_sources[0x27] 9057 1 T34 2 T61 2 T57 4
valid_sources[0x28] 10551 1 T54 1 T57 2 T62 3
valid_sources[0x29] 13499 1 T29 1 T53 2 T75 1
valid_sources[0x2a] 12156 1 T68 1 T57 3 T76 2
valid_sources[0x2b] 12342 1 T33 3 T57 1 T62 1
valid_sources[0x2c] 12550 1 T29 1 T68 1 T57 6
valid_sources[0x2d] 11068 1 T57 1 T62 1 T118 1
valid_sources[0x2e] 12138 1 T57 2 T62 2 T121 2
valid_sources[0x2f] 10044 1 T32 3 T57 5 T78 1
valid_sources[0x30] 11577 1 T59 1 T75 2 T57 4
valid_sources[0x31] 10914 1 T29 1 T54 1 T57 2
valid_sources[0x32] 11396 1 T59 1 T57 2 T78 1
valid_sources[0x33] 15603 1 T40 18 T75 1 T57 2
valid_sources[0x34] 13767 1 T34 1 T75 1 T57 4
valid_sources[0x35] 11097 1 T33 2 T75 1 T57 1
valid_sources[0x36] 12834 1 T57 1 T62 1 T78 2
valid_sources[0x37] 11660 1 T36 121 T55 2 T57 5
valid_sources[0x38] 11433 1 T29 1 T32 15 T53 1
valid_sources[0x39] 10615 1 T33 3 T56 1 T57 4
valid_sources[0x3a] 9531 1 T54 4 T57 3 T77 19
valid_sources[0x3b] 10650 1 T61 1 T57 4 T78 1
valid_sources[0x3c] 11511 1 T33 1 T75 1 T57 2
valid_sources[0x3d] 10855 1 T32 2 T56 1 T57 5
valid_sources[0x3e] 10610 1 T57 2 T78 1 T118 1
valid_sources[0x3f] 9915 1 T34 5 T57 7 T62 2
valid_sources[0x40] 10760 1 T57 2 T62 1 T118 1
valid_sources[0x41] 9784 1 T34 4 T59 1 T57 3
valid_sources[0x42] 9173 1 T34 1 T54 2 T57 6
valid_sources[0x43] 10724 1 T33 1 T34 2 T57 5
valid_sources[0x44] 14515 1 T29 1 T75 1 T57 2
valid_sources[0x45] 10709 1 T29 1 T57 5 T62 1
valid_sources[0x46] 11131 1 T57 4 T62 1 T118 1
valid_sources[0x47] 13217 1 T59 1 T57 4 T109 3
valid_sources[0x48] 11483 1 T57 7 T62 2 T118 4
valid_sources[0x49] 11371 1 T57 2 T62 1 T118 1
valid_sources[0x4a] 11980 1 T33 1 T57 2 T109 1
valid_sources[0x4b] 10556 1 T54 2 T61 1 T57 2
valid_sources[0x4c] 12096 1 T57 5 T118 2 T121 2
valid_sources[0x4d] 10955 1 T68 1 T57 2 T118 1
valid_sources[0x4e] 10916 1 T54 1 T57 2 T62 1
valid_sources[0x4f] 11608 1 T55 2 T68 1 T57 4
valid_sources[0x50] 11167 1 T68 1 T57 4 T118 1
valid_sources[0x51] 13490 1 T57 4 T109 2 T119 5
valid_sources[0x52] 12060 1 T57 5 T62 1 T78 1
valid_sources[0x53] 10345 1 T34 1 T54 3 T57 5
valid_sources[0x54] 10833 1 T75 1 T57 3 T78 1
valid_sources[0x55] 11773 1 T59 1 T61 1 T57 4
valid_sources[0x56] 10243 1 T29 1 T59 1 T75 1
valid_sources[0x57] 12623 1 T34 6 T61 1 T57 2
valid_sources[0x58] 10390 1 T61 1 T57 5 T63 1
valid_sources[0x59] 9815 1 T68 2 T57 4 T118 3
valid_sources[0x5a] 9929 1 T53 1 T57 1 T77 2
valid_sources[0x5b] 13108 1 T57 3 T118 1 T121 1
valid_sources[0x5c] 9730 1 T29 1 T57 4 T78 1
valid_sources[0x5d] 12264 1 T57 2 T118 5 T121 1
valid_sources[0x5e] 12701 1 T54 2 T56 1 T59 1
valid_sources[0x5f] 11182 1 T57 3 T118 1 T109 1
valid_sources[0x60] 9887 1 T57 4 T118 1 T121 2
valid_sources[0x61] 11810 1 T56 2 T57 4 T118 2
valid_sources[0x62] 9513 1 T57 4 T62 1 T121 2
valid_sources[0x63] 11906 1 T57 1 T118 1 T120 9
valid_sources[0x64] 10485 1 T57 3 T78 1 T118 1
valid_sources[0x65] 11762 1 T57 4 T78 1 T109 6
valid_sources[0x66] 12309 1 T59 1 T57 8 T62 2
valid_sources[0x67] 12542 1 T57 7 T121 1 T109 2
valid_sources[0x68] 10301 1 T29 1 T56 1 T59 1
valid_sources[0x69] 10820 1 T57 4 T78 1 T118 1
valid_sources[0x6a] 11005 1 T57 5 T118 1 T119 3
valid_sources[0x6b] 11147 1 T59 2 T68 1 T57 1
valid_sources[0x6c] 11242 1 T57 3 T78 2 T118 4
valid_sources[0x6d] 11302 1 T59 1 T57 4 T62 2
valid_sources[0x6e] 8904 1 T56 1 T57 4 T118 3
valid_sources[0x6f] 12191 1 T59 1 T61 1 T57 4
valid_sources[0x70] 12154 1 T34 3 T54 1 T68 1
valid_sources[0x71] 11146 1 T59 1 T57 3 T121 3
valid_sources[0x72] 10920 1 T59 1 T57 4 T77 3
valid_sources[0x73] 10820 1 T56 1 T61 1 T57 5
valid_sources[0x74] 12761 1 T56 1 T57 4 T62 1
valid_sources[0x75] 12174 1 T54 1 T57 6 T62 1
valid_sources[0x76] 10957 1 T57 4 T121 2 T109 1
valid_sources[0x77] 11438 1 T68 2 T57 2 T62 1
valid_sources[0x78] 9538 1 T57 4 T78 1 T121 1
valid_sources[0x79] 9503 1 T51 195 T68 1 T57 5
valid_sources[0x7a] 11696 1 T29 1 T57 3 T118 1
valid_sources[0x7b] 11050 1 T29 1 T57 6 T62 1
valid_sources[0x7c] 10700 1 T59 1 T75 1 T57 4
valid_sources[0x7d] 8737 1 T57 7 T121 2 T109 7
valid_sources[0x7e] 9897 1 T59 1 T57 3 T62 2
valid_sources[0x7f] 11331 1 T54 1 T57 6 T62 2
valid_sources[0x80] 12309 1 T59 2 T57 4 T78 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 591352 1 T29 4 T32 40 T33 40
values[0x0] all_enables biggest_size 877832 1 T29 5 T36 74 T51 208
values[0x1] all_enables biggest_size 877786 1 T29 5 T36 60 T40 1

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