SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rom_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rom_ctrl_rom_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 7637208 | 0 | T21 | 250 | T28 | 236 | T29 | 108 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 7637016 | 1 | T21 | 250 | T28 | 229 | T29 | 108 | ||||
values[1] | 20 | 1 | T52 | 1 | T63 | 2 | T64 | 2 | ||||
values[2] | 3 | 1 | T111 | 1 | T112 | 1 | T113 | 1 | ||||
values[3] | 92 | 1 | T28 | 6 | T40 | 8 | T52 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 7637011 | 1 | T21 | 250 | T28 | 231 | T29 | 108 | ||||
values[1] | 24 | 1 | T28 | 1 | T40 | 2 | T55 | 2 | ||||
values[2] | 8 | 1 | T64 | 2 | T76 | 1 | T111 | 1 | ||||
values[3] | 90 | 1 | T28 | 2 | T40 | 6 | T52 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 7636928 | 1 | T21 | 250 | T28 | 226 | T29 | 108 | ||||
auto[TlIntgErrCmd] | 83 | 1 | T28 | 5 | T40 | 6 | T52 | 2 | ||||
auto[TlIntgErrData] | 88 | 1 | T28 | 3 | T40 | 4 | T52 | 4 | ||||
auto[TlIntgErrBoth] | 109 | 1 | T28 | 2 | T40 | 10 | T52 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 9343423 | 0 | T28 | 10 | T29 | 125 | T32 | 40 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 9343238 | 1 | T28 | 1 | T29 | 125 | T32 | 40 | ||||
values[1] | 16 | 1 | T28 | 1 | T40 | 2 | T63 | 2 | ||||
values[2] | 1 | 1 | T114 | 1 | - | - | - | - | ||||
values[3] | 105 | 1 | T28 | 3 | T40 | 8 | T52 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 9343236 | 1 | T28 | 5 | T29 | 125 | T32 | 40 | ||||
values[1] | 18 | 1 | T40 | 2 | T52 | 1 | T63 | 3 | ||||
values[2] | 6 | 1 | T64 | 1 | T114 | 1 | T115 | 1 | ||||
values[3] | 94 | 1 | T28 | 2 | T40 | 6 | T52 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 9343143 | 1 | T29 | 125 | T32 | 40 | T33 | 40 | ||||
auto[TlIntgErrCmd] | 93 | 1 | T28 | 5 | T40 | 7 | T52 | 2 | ||||
auto[TlIntgErrData] | 95 | 1 | T28 | 1 | T40 | 6 | T52 | 4 | ||||
auto[TlIntgErrBoth] | 92 | 1 | T28 | 4 | T40 | 7 | T52 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |