Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6531101

1

T28

10

T29

101

T36

561

full_word

2812322

1

T29

24

T32

40

T33

40

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	9343143	1			T29	125		T32	40		T33	40
auto[TlIntgErrCmd]	93	1			T28	5		T40	7		T52	2
auto[TlIntgErrData]	95	1			T28	1		T40	6		T52	4
auto[TlIntgErrBoth]	92	1			T28	4		T40	7		T52	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115615

1

T28

4

T29

19

T32

40

auto[1]

8227808

1

T28

6

T29

106

T36

717

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	467244	1			T29	14		T36	29		T51	37
auto[TlIntgErrNone]	partial	auto[1]	6063604	1			T29	87		T36	532		T51	988
auto[TlIntgErrNone]	full_word	auto[0]	648249	1			T29	5		T32	40		T33	40
auto[TlIntgErrNone]	full_word	auto[1]	2164046	1			T29	19		T36	185		T51	458
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T28	1		T40	3		T52	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T28	4		T40	4		T55	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T63	1		T64	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T52	1		T64	2		T76	1
auto[TlIntgErrData]	partial	auto[0]	31	1			T28	1		T40	2		T52	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T40	4		T52	3		T55	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T64	1		T112	1		T115	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T64	1		T76	1		T111	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T28	2		T40	3		T52	2
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T28	2		T40	2		T52	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T40	1		T63	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T40	1		T64	1		T114	1