Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
277515972 |
277331607 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
277515972 |
277331607 |
0 |
0 |
T1 |
9223 |
9169 |
0 |
0 |
T2 |
151149 |
151082 |
0 |
0 |
T3 |
185350 |
185338 |
0 |
0 |
T4 |
609395 |
608988 |
0 |
0 |
T5 |
184171 |
184093 |
0 |
0 |
T6 |
278015 |
277869 |
0 |
0 |
T7 |
662332 |
661891 |
0 |
0 |
T8 |
209703 |
207100 |
0 |
0 |
T9 |
374714 |
374685 |
0 |
0 |
T10 |
129491 |
127192 |
0 |
0 |