Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 153080 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1550554 1 T22 71 T23 19 T24 338



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 427085 1 T22 72 T23 2 T24 47
values[0x0] 590531 1 T22 21 T23 9 T24 173
values[0x1] 686018 1 T22 15 T23 9 T24 178



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 68793 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1634841 1 T22 75 T23 19 T24 355



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 6448 1 T29 1 T79 4 T91 2
valid_sources[0x01] 6771 1 T26 4 T29 6 T30 3
valid_sources[0x02] 6728 1 T24 4 T69 2 T72 1
valid_sources[0x03] 6510 1 T25 3 T29 1 T30 1
valid_sources[0x04] 7547 1 T24 1 T29 1 T79 1
valid_sources[0x05] 7076 1 T28 1 T29 4 T30 7
valid_sources[0x06] 7225 1 T24 1 T29 3 T79 4
valid_sources[0x07] 5873 1 T24 1 T30 1 T43 2
valid_sources[0x08] 7122 1 T24 11 T26 6 T28 1
valid_sources[0x09] 6041 1 T26 3 T29 1 T43 2
valid_sources[0x0a] 5983 1 T22 2 T26 7 T29 1
valid_sources[0x0b] 6558 1 T29 2 T30 4 T43 2
valid_sources[0x0c] 7081 1 T26 1 T28 2 T29 1
valid_sources[0x0d] 6445 1 T29 2 T43 1 T91 1
valid_sources[0x0e] 5899 1 T26 4 T30 1 T31 1
valid_sources[0x0f] 6445 1 T29 1 T30 11 T67 1
valid_sources[0x10] 5913 1 T24 9 T26 1 T29 1
valid_sources[0x11] 7273 1 T28 1 T30 3 T43 1
valid_sources[0x12] 7114 1 T24 13 T29 1 T91 1
valid_sources[0x13] 6630 1 T23 3 T24 4 T25 2
valid_sources[0x14] 7723 1 T24 1 T29 1 T43 2
valid_sources[0x15] 6512 1 T24 4 T26 3 T29 1
valid_sources[0x16] 6421 1 T25 1 T29 1 T66 1
valid_sources[0x17] 7132 1 T29 1 T43 1 T68 68
valid_sources[0x18] 6932 1 T25 10 T28 6 T29 1
valid_sources[0x19] 6537 1 T26 7 T90 1 T91 1
valid_sources[0x1a] 6140 1 T24 10 T29 1 T79 1
valid_sources[0x1b] 6251 1 T25 3 T26 1 T29 1
valid_sources[0x1c] 6994 1 T24 1 T26 3 T29 2
valid_sources[0x1d] 6680 1 T25 8 T26 1 T29 1
valid_sources[0x1e] 6564 1 T22 1 T23 3 T24 1
valid_sources[0x1f] 6999 1 T26 3 T29 2 T66 1
valid_sources[0x20] 6647 1 T29 2 T30 1 T79 5
valid_sources[0x21] 6154 1 T26 1 T66 1 T43 1
valid_sources[0x22] 6370 1 T22 1 T29 2 T30 5
valid_sources[0x23] 6978 1 T29 1 T31 2 T66 1
valid_sources[0x24] 6395 1 T43 1 T69 4 T84 5
valid_sources[0x25] 6803 1 T29 1 T31 1 T66 1
valid_sources[0x26] 6822 1 T22 1 T29 2 T30 3
valid_sources[0x27] 6561 1 T22 1 T66 1 T43 2
valid_sources[0x28] 5874 1 T29 1 T31 1 T90 3
valid_sources[0x29] 6394 1 T26 3 T29 2 T43 1
valid_sources[0x2a] 6487 1 T24 2 T31 1 T66 1
valid_sources[0x2b] 5968 1 T24 1 T25 12 T26 2
valid_sources[0x2c] 7047 1 T24 1 T26 2 T29 1
valid_sources[0x2d] 6770 1 T24 4 T66 1 T74 10
valid_sources[0x2e] 7229 1 T31 1 T90 1 T67 1
valid_sources[0x2f] 6834 1 T24 2 T26 3 T29 2
valid_sources[0x30] 6771 1 T22 1 T29 2 T69 1
valid_sources[0x31] 7044 1 T29 2 T66 1 T43 2
valid_sources[0x32] 6802 1 T29 1 T31 1 T66 1
valid_sources[0x33] 6665 1 T66 1 T79 1 T69 1
valid_sources[0x34] 6922 1 T25 1 T29 1 T30 7
valid_sources[0x35] 6656 1 T29 1 T92 1 T69 1
valid_sources[0x36] 6039 1 T22 1 T24 19 T25 8
valid_sources[0x37] 7019 1 T25 14 T30 5 T43 2
valid_sources[0x38] 5804 1 T24 8 T26 1 T30 2
valid_sources[0x39] 6544 1 T24 1 T43 2 T68 40
valid_sources[0x3a] 6733 1 T29 3 T43 2 T71 2
valid_sources[0x3b] 6083 1 T24 5 T26 4 T79 2
valid_sources[0x3c] 6121 1 T24 1 T29 1 T92 1
valid_sources[0x3d] 7524 1 T26 7 T28 2 T29 2
valid_sources[0x3e] 7016 1 T22 1 T24 11 T26 2
valid_sources[0x3f] 7281 1 T24 1 T43 1 T90 3
valid_sources[0x40] 6356 1 T26 2 T29 1 T90 3
valid_sources[0x41] 6433 1 T29 1 T76 1 T77 1
valid_sources[0x42] 6645 1 T29 1 T79 2 T69 2
valid_sources[0x43] 6527 1 T24 2 T79 4 T69 3
valid_sources[0x44] 6191 1 T25 3 T26 1 T29 1
valid_sources[0x45] 6243 1 T29 2 T31 2 T43 2
valid_sources[0x46] 6014 1 T22 1 T24 1 T26 2
valid_sources[0x47] 7017 1 T22 1 T25 6 T26 1
valid_sources[0x48] 6975 1 T30 1 T31 1 T66 2
valid_sources[0x49] 6655 1 T24 1 T31 1 T69 2
valid_sources[0x4a] 6318 1 T24 6 T69 1 T70 1
valid_sources[0x4b] 6401 1 T24 13 T29 1 T43 2
valid_sources[0x4c] 8164 1 T25 3 T26 2 T43 1
valid_sources[0x4d] 6505 1 T24 7 T28 1 T29 1
valid_sources[0x4e] 6730 1 T22 1 T43 1 T91 1
valid_sources[0x4f] 6483 1 T25 1 T26 1 T29 1
valid_sources[0x50] 7142 1 T66 1 T43 1 T79 4
valid_sources[0x51] 7391 1 T26 1 T29 3 T30 4
valid_sources[0x52] 6982 1 T22 1 T24 6 T66 1
valid_sources[0x53] 7017 1 T31 1 T79 3 T67 1
valid_sources[0x54] 6515 1 T24 1 T26 2 T29 1
valid_sources[0x55] 6825 1 T24 7 T43 2 T79 2
valid_sources[0x56] 6768 1 T22 1 T24 1 T25 4
valid_sources[0x57] 6299 1 T22 1 T24 4 T29 1
valid_sources[0x58] 6884 1 T26 1 T29 2 T79 3
valid_sources[0x59] 6173 1 T29 1 T31 1 T66 1
valid_sources[0x5a] 8014 1 T24 1 T25 8 T30 1
valid_sources[0x5b] 6451 1 T26 3 T29 1 T31 2
valid_sources[0x5c] 6534 1 T24 2 T30 3 T43 1
valid_sources[0x5d] 5951 1 T24 11 T25 1 T29 1
valid_sources[0x5e] 6807 1 T24 16 T29 1 T70 1
valid_sources[0x5f] 7009 1 T26 2 T28 2 T29 1
valid_sources[0x60] 6659 1 T22 1 T29 2 T30 1
valid_sources[0x61] 6990 1 T29 1 T31 2 T69 1
valid_sources[0x62] 6365 1 T27 10 T43 1 T70 1
valid_sources[0x63] 7312 1 T24 5 T43 2 T69 2
valid_sources[0x64] 7187 1 T24 6 T26 2 T66 1
valid_sources[0x65] 6598 1 T26 1 T29 2 T66 1
valid_sources[0x66] 7651 1 T28 2 T29 2 T66 1
valid_sources[0x67] 6232 1 T26 3 T29 2 T30 5
valid_sources[0x68] 5685 1 T43 1 T91 2 T69 2
valid_sources[0x69] 6356 1 T31 1 T92 1 T69 1
valid_sources[0x6a] 6774 1 T28 3 T91 2 T69 2
valid_sources[0x6b] 6497 1 T22 1 T29 1 T43 1
valid_sources[0x6c] 6956 1 T26 4 T66 4 T43 1
valid_sources[0x6d] 6321 1 T24 10 T25 1 T26 1
valid_sources[0x6e] 7338 1 T24 4 T26 3 T29 3
valid_sources[0x6f] 6394 1 T29 3 T66 1 T43 5
valid_sources[0x70] 6252 1 T24 4 T25 3 T29 1
valid_sources[0x71] 6619 1 T29 1 T79 4 T69 2
valid_sources[0x72] 6590 1 T22 1 T29 2 T70 3
valid_sources[0x73] 6210 1 T22 1 T43 2 T91 1
valid_sources[0x74] 6445 1 T30 1 T43 1 T92 1
valid_sources[0x75] 6489 1 T24 1 T26 5 T29 1
valid_sources[0x76] 6542 1 T26 2 T29 1 T90 8
valid_sources[0x77] 6755 1 T23 5 T26 2 T29 2
valid_sources[0x78] 7219 1 T24 2 T26 1 T29 2
valid_sources[0x79] 5909 1 T91 1 T69 2 T70 5
valid_sources[0x7a] 7237 1 T26 3 T29 1 T30 1
valid_sources[0x7b] 6703 1 T25 6 T30 2 T92 1
valid_sources[0x7c] 7086 1 T22 1 T29 2 T30 4
valid_sources[0x7d] 6656 1 T26 1 T29 1 T68 5
valid_sources[0x7e] 6921 1 T24 4 T29 1 T43 1
valid_sources[0x7f] 6717 1 T26 6 T30 5 T43 2
valid_sources[0x80] 6963 1 T26 1 T29 2 T66 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 392434 1 T22 38 T23 2 T24 12
values[0x0] all_enables biggest_size 578524 1 T22 20 T23 8 T24 160
values[0x1] all_enables biggest_size 579596 1 T22 13 T23 9 T24 166


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 356895 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1498918 1 T24 40 T25 20 T29 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 422565 1 T24 40 T25 20 T26 3
values[0x0] 590046 1 T26 3 T29 4 T31 4
values[0x1] 843202 1 T26 1 T29 4 T31 9



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 136247 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1719566 1 T24 40 T25 20 T26 2



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 7970 1 T77 1 T82 1 T112 4
valid_sources[0x01] 7251 1 T79 20 T70 1 T75 1
valid_sources[0x02] 7763 1 T76 2 T77 1 T120 1
valid_sources[0x03] 6800 1 T89 1 T121 2 T122 2
valid_sources[0x04] 6853 1 T85 1 T76 5 T77 3
valid_sources[0x05] 6928 1 T66 1 T77 2 T112 1
valid_sources[0x06] 6856 1 T70 2 T76 3 T112 1
valid_sources[0x07] 7059 1 T66 2 T69 3 T75 2
valid_sources[0x08] 7812 1 T25 1 T76 1 T77 1
valid_sources[0x09] 6646 1 T75 1 T76 1 T82 2
valid_sources[0x0a] 6910 1 T31 3 T66 1 T82 1
valid_sources[0x0b] 7601 1 T67 1 T70 3 T75 4
valid_sources[0x0c] 7937 1 T25 3 T66 1 T67 1
valid_sources[0x0d] 6929 1 T76 1 T82 1 T112 1
valid_sources[0x0e] 6825 1 T70 4 T76 1 T120 1
valid_sources[0x0f] 7956 1 T76 1 T77 1 T112 6
valid_sources[0x10] 7087 1 T66 3 T67 1 T75 2
valid_sources[0x11] 7448 1 T67 1 T76 2 T77 3
valid_sources[0x12] 7327 1 T68 1 T76 3 T82 1
valid_sources[0x13] 6674 1 T82 2 T112 7 T95 1
valid_sources[0x14] 7217 1 T31 1 T82 1 T112 2
valid_sources[0x15] 6448 1 T66 2 T76 2 T80 1
valid_sources[0x16] 7023 1 T75 1 T85 1 T76 2
valid_sources[0x17] 8809 1 T66 1 T67 1 T76 2
valid_sources[0x18] 6829 1 T80 1 T77 1 T82 1
valid_sources[0x19] 6887 1 T66 1 T67 1 T75 1
valid_sources[0x1a] 7456 1 T25 3 T76 3 T77 1
valid_sources[0x1b] 6514 1 T66 1 T70 2 T76 1
valid_sources[0x1c] 7298 1 T66 1 T85 1 T76 1
valid_sources[0x1d] 7299 1 T75 7 T76 1 T77 1
valid_sources[0x1e] 7170 1 T66 2 T80 1 T77 1
valid_sources[0x1f] 6827 1 T67 1 T75 1 T76 1
valid_sources[0x20] 7183 1 T66 2 T70 10 T85 1
valid_sources[0x21] 8111 1 T66 1 T76 1 T77 2
valid_sources[0x22] 6913 1 T69 9 T76 1 T77 4
valid_sources[0x23] 7140 1 T66 1 T67 1 T76 1
valid_sources[0x24] 9261 1 T67 2 T82 2 T112 3
valid_sources[0x25] 6834 1 T25 1 T66 1 T67 1
valid_sources[0x26] 8043 1 T76 2 T77 2 T82 3
valid_sources[0x27] 7121 1 T66 5 T76 1 T77 2
valid_sources[0x28] 7103 1 T75 2 T77 2 T82 2
valid_sources[0x29] 7813 1 T70 4 T77 1 T112 1
valid_sources[0x2a] 7705 1 T77 1 T82 1 T121 3
valid_sources[0x2b] 7613 1 T76 2 T77 1 T121 1
valid_sources[0x2c] 7448 1 T66 4 T70 1 T77 1
valid_sources[0x2d] 7285 1 T70 1 T76 2 T77 2
valid_sources[0x2e] 6836 1 T66 2 T89 1 T123 1
valid_sources[0x2f] 7124 1 T66 2 T68 1 T70 2
valid_sources[0x30] 6792 1 T66 2 T89 2 T123 2
valid_sources[0x31] 7422 1 T76 3 T77 3 T112 4
valid_sources[0x32] 8165 1 T72 1 T80 1 T77 1
valid_sources[0x33] 6770 1 T25 2 T29 4 T77 1
valid_sources[0x34] 7553 1 T66 1 T70 1 T76 1
valid_sources[0x35] 7543 1 T70 1 T112 5 T121 1
valid_sources[0x36] 6847 1 T76 3 T77 1 T120 1
valid_sources[0x37] 7501 1 T66 1 T72 1 T76 2
valid_sources[0x38] 8500 1 T70 5 T76 2 T82 2
valid_sources[0x39] 8005 1 T75 4 T76 2 T77 1
valid_sources[0x3a] 6884 1 T66 4 T76 3 T77 3
valid_sources[0x3b] 7464 1 T68 1 T76 2 T77 1
valid_sources[0x3c] 7581 1 T31 2 T76 1 T112 4
valid_sources[0x3d] 7311 1 T68 1 T76 1 T77 5
valid_sources[0x3e] 7168 1 T66 1 T70 2 T76 1
valid_sources[0x3f] 7041 1 T66 1 T67 2 T76 4
valid_sources[0x40] 6526 1 T24 5 T66 2 T76 1
valid_sources[0x41] 8440 1 T75 1 T76 1 T82 1
valid_sources[0x42] 6988 1 T71 16 T77 2 T112 5
valid_sources[0x43] 7177 1 T75 1 T76 1 T77 1
valid_sources[0x44] 6266 1 T66 1 T76 1 T77 1
valid_sources[0x45] 6802 1 T76 2 T77 3 T82 5
valid_sources[0x46] 7874 1 T76 2 T77 1 T82 2
valid_sources[0x47] 7641 1 T66 4 T75 1 T76 3
valid_sources[0x48] 8397 1 T70 1 T77 5 T82 1
valid_sources[0x49] 6805 1 T25 1 T66 1 T75 1
valid_sources[0x4a] 6963 1 T24 1 T76 2 T80 2
valid_sources[0x4b] 6755 1 T66 1 T76 2 T77 2
valid_sources[0x4c] 8653 1 T75 1 T76 3 T82 2
valid_sources[0x4d] 6909 1 T66 2 T75 1 T76 2
valid_sources[0x4e] 6742 1 T66 1 T75 1 T76 1
valid_sources[0x4f] 7290 1 T24 4 T66 3 T76 4
valid_sources[0x50] 7344 1 T66 5 T67 1 T75 1
valid_sources[0x51] 6595 1 T66 5 T76 1 T82 2
valid_sources[0x52] 7398 1 T66 3 T76 1 T77 1
valid_sources[0x53] 7271 1 T66 3 T76 1 T77 1
valid_sources[0x54] 7431 1 T67 1 T76 2 T77 1
valid_sources[0x55] 6198 1 T66 1 T67 1 T76 2
valid_sources[0x56] 8420 1 T75 2 T76 1 T77 5
valid_sources[0x57] 6956 1 T112 2 T124 2 T125 1
valid_sources[0x58] 7111 1 T70 6 T85 1 T76 1
valid_sources[0x59] 6794 1 T75 1 T76 1 T77 2
valid_sources[0x5a] 6651 1 T70 3 T76 4 T80 1
valid_sources[0x5b] 7455 1 T66 2 T70 1 T80 1
valid_sources[0x5c] 6772 1 T75 1 T76 4 T82 1
valid_sources[0x5d] 7070 1 T66 1 T76 2 T77 1
valid_sources[0x5e] 7096 1 T66 2 T75 7 T85 1
valid_sources[0x5f] 6999 1 T67 2 T70 1 T80 1
valid_sources[0x60] 8062 1 T24 7 T66 7 T70 2
valid_sources[0x61] 7029 1 T66 1 T67 2 T80 1
valid_sources[0x62] 6529 1 T66 1 T75 2 T112 3
valid_sources[0x63] 7187 1 T66 1 T67 1 T70 6
valid_sources[0x64] 7934 1 T66 1 T76 2 T80 2
valid_sources[0x65] 7833 1 T76 1 T77 1 T82 1
valid_sources[0x66] 7084 1 T82 1 T112 4 T114 1
valid_sources[0x67] 6593 1 T70 3 T76 2 T77 2
valid_sources[0x68] 7492 1 T76 2 T82 1 T112 9
valid_sources[0x69] 7692 1 T24 5 T66 1 T76 2
valid_sources[0x6a] 7769 1 T67 1 T85 1 T76 1
valid_sources[0x6b] 7393 1 T77 1 T82 1 T112 1
valid_sources[0x6c] 6553 1 T76 2 T77 2 T112 1
valid_sources[0x6d] 6498 1 T68 1 T124 1 T125 3
valid_sources[0x6e] 7847 1 T76 3 T77 1 T87 6
valid_sources[0x6f] 7602 1 T76 2 T77 1 T82 2
valid_sources[0x70] 7269 1 T76 2 T82 1 T112 1
valid_sources[0x71] 7459 1 T26 7 T66 2 T84 20
valid_sources[0x72] 6296 1 T31 3 T66 2 T76 1
valid_sources[0x73] 6650 1 T66 3 T76 1 T77 1
valid_sources[0x74] 6767 1 T76 1 T77 3 T112 2
valid_sources[0x75] 7379 1 T76 1 T77 1 T82 1
valid_sources[0x76] 7618 1 T31 1 T66 3 T85 1
valid_sources[0x77] 7780 1 T31 1 T66 1 T67 1
valid_sources[0x78] 6982 1 T66 2 T77 1 T82 1
valid_sources[0x79] 6697 1 T70 1 T76 1 T82 1
valid_sources[0x7a] 6994 1 T66 2 T77 2 T112 1
valid_sources[0x7b] 7197 1 T66 1 T126 1 T124 1
valid_sources[0x7c] 6940 1 T76 5 T77 1 T82 1
valid_sources[0x7d] 6817 1 T66 1 T67 1 T75 1
valid_sources[0x7e] 7596 1 T66 1 T43 20 T70 3
valid_sources[0x7f] 7097 1 T77 2 T89 1 T121 2
valid_sources[0x80] 6508 1 T66 2 T76 3 T80 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 378156 1 T24 40 T25 20 T31 7
values[0x0] all_enables biggest_size 560534 1 T29 2 T31 4 T66 69
values[0x1] all_enables biggest_size 560228 1 T31 4 T66 85 T68 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%