Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4268187

1

T26

10

T29

8

T31

55

full_word

1802863

1

T24

40

T25

20

T29

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6070760	1			T24	40		T25	20		T31	72
auto[TlIntgErrCmd]	100	1			T26	4		T29	6		T68	5
auto[TlIntgErrData]	88	1			T26	1		T29	3		T68	5
auto[TlIntgErrBoth]	102	1			T26	5		T29	1		T68	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

732569

1

T24

40

T25

20

T26

4

auto[1]

5338481

1

T26

6

T29

9

T31

61

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	317287	1			T31	4		T66	56		T70	18
auto[TlIntgErrNone]	partial	auto[1]	3950630	1			T31	51		T66	350		T67	77
auto[TlIntgErrNone]	full_word	auto[0]	415152	1			T24	40		T25	20		T31	7
auto[TlIntgErrNone]	full_word	auto[1]	1387691	1			T31	10		T66	197		T67	34
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T26	2		T68	1		T69	4
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T26	2		T29	5		T68	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T115	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T29	1		T68	2		T69	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T68	1		T69	1		T71	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T26	1		T29	2		T68	3
auto[TlIntgErrData]	full_word	auto[1]	6	1			T29	1		T68	1		T78	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T26	2		T29	1		T68	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T26	3		T68	7		T69	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T71	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T116	1		T117	2		T118	1