SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
rom_ctrl_kmac_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 7 | 0 | 7 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_kmac_done | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
cp_kmac_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
kmac_first | 473 | 1 | T25 | 11 | T26 | 1 | T43 | 1 | ||||
same_cycle | 14 | 1 | T20 | 1 | T35 | 1 | T36 | 1 | ||||
rom_first | 1564 | 1 | T22 | 1 | T23 | 1 | T24 | 21 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
stall_repeat | 93249710 | 1 | T22 | 67911 | T23 | 56508 | T24 | 42814 | ||||
stall_long | 9848035 | 1 | T22 | 7088 | T23 | 6162 | T26 | 7531 | ||||
stall_1 | 1107523 | 1 | T22 | 203 | T23 | 405 | T24 | 85928 | ||||
zero_delay_5 | 2851206 | 1 | T24 | 10656 | T25 | 89980 | T28 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |