Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
239648369 |
239459890 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239648369 |
239459890 |
0 |
0 |
T1 |
378267 |
378118 |
0 |
0 |
T2 |
270838 |
270675 |
0 |
0 |
T3 |
53948 |
53895 |
0 |
0 |
T4 |
283757 |
283654 |
0 |
0 |
T5 |
128419 |
127880 |
0 |
0 |
T6 |
123362 |
123192 |
0 |
0 |
T7 |
311866 |
311744 |
0 |
0 |
T8 |
157388 |
157203 |
0 |
0 |
T9 |
9625 |
9557 |
0 |
0 |
T10 |
157311 |
157193 |
0 |
0 |