Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.81	86.13	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	85.40	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	86.86	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.40	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	20	114	85.07
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	20	109	84.50	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.86	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	18	116	86.57
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	18	111	86.05	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10305	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33420

1

T17

509

T18

345

T19

341

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14320	1			T17	156		T18	136		T19	47
values[0x0]	14040	1			T17	183		T18	165		T19	168
values[0x1]	15365	1			T17	191		T18	197		T19	182

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7825	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35900

1

T17

519

T18

395

T19

358

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	20	109	84.50

User Defined Bins for cp_source

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
valid_sources[0x03]	0	1	1
valid_sources[0x07]	0	1	1
valid_sources[0x08]	0	1	1
valid_sources[0x10]	0	1	1
valid_sources[0x17]	0	1	1
valid_sources[0x1d]	0	1	1
valid_sources[0x21]	0	1	1
valid_sources[0x24]	0	1	1
valid_sources[0x2d]	0	1	1
valid_sources[0x2e]	0	1	1
valid_sources[0x2f]	0	1	1
valid_sources[0x32]	0	1	1
valid_sources[0x39]	0	1	1
valid_sources[0x47]	0	1	1
valid_sources[0x4e]	0	1	1
valid_sources[0x4f]	0	1	1
valid_sources[0x64]	0	1	1
valid_sources[0x7b]	0	1	1
valid_sources[0x7c]	0	1	1
valid_sources[0x7e]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	100	1			T18	5		T25	5		T46	5
valid_sources[0x01]	115	1			T18	4		T25	4		T46	4
valid_sources[0x02]	60	1			T17	3		T22	3		T47	3
valid_sources[0x04]	15	1			T59	2		T76	2		T68	1
valid_sources[0x05]	315	1			T17	13		T22	13		T47	13
valid_sources[0x06]	380	1			T17	10		T18	9		T22	10
valid_sources[0x09]	280	1			T18	14		T25	14		T46	14
valid_sources[0x0a]	45	1			T17	2		T22	2		T47	2
valid_sources[0x0b]	245	1			T17	12		T22	12		T47	12
valid_sources[0x0c]	110	1			T17	1		T19	3		T21	6
valid_sources[0x0d]	480	1			T18	10		T19	14		T24	14
valid_sources[0x0e]	200	1			T17	1		T19	8		T22	1
valid_sources[0x0f]	160	1			T18	6		T25	6		T57	2
valid_sources[0x11]	320	1			T19	16		T24	16		T30	16
valid_sources[0x12]	200	1			T18	2		T19	8		T24	8
valid_sources[0x13]	40	1			T18	2		T25	2		T46	2
valid_sources[0x14]	135	1			T59	27		T76	27		T85	27
valid_sources[0x15]	260	1			T20	13		T56	13		T86	13
valid_sources[0x16]	40	1			T17	2		T22	2		T47	2
valid_sources[0x18]	500	1			T17	2		T19	16		T22	2
valid_sources[0x19]	20	1			T17	1		T22	1		T47	1
valid_sources[0x1a]	1260	1			T17	10		T18	52		T22	10
valid_sources[0x1b]	180	1			T17	8		T20	1		T22	8
valid_sources[0x1c]	40	1			T57	2		T58	2		T70	2
valid_sources[0x1e]	165	1			T17	8		T22	8		T47	8
valid_sources[0x1f]	50	1			T20	2		T59	2		T76	2
valid_sources[0x20]	500	1			T17	2		T18	6		T22	2
valid_sources[0x22]	50	1			T19	2		T24	2		T30	2
valid_sources[0x23]	120	1			T18	6		T25	6		T46	6
valid_sources[0x25]	140	1			T59	28		T76	28		T85	28
valid_sources[0x26]	50	1			T59	10		T76	10		T85	10
valid_sources[0x27]	20	1			T23	1		T26	1		T87	1
valid_sources[0x28]	80	1			T17	3		T22	3		T47	3
valid_sources[0x29]	15	1			T59	3		T76	3		T85	3
valid_sources[0x2a]	530	1			T17	3		T18	19		T19	3
valid_sources[0x2b]	340	1			T23	2		T26	2		T87	2
valid_sources[0x2c]	250	1			T17	11		T18	1		T22	11
valid_sources[0x30]	60	1			T19	3		T24	3		T30	3
valid_sources[0x31]	190	1			T17	7		T19	2		T22	7
valid_sources[0x33]	40	1			T17	2		T22	2		T47	2
valid_sources[0x34]	80	1			T17	4		T22	4		T47	4
valid_sources[0x35]	5	1			T68	1		T88	1		T89	1
valid_sources[0x36]	200	1			T57	10		T58	10		T70	10
valid_sources[0x37]	220	1			T20	4		T23	7		T26	7
valid_sources[0x38]	60	1			T18	3		T25	3		T46	3
valid_sources[0x3a]	95	1			T17	2		T22	2		T47	2
valid_sources[0x3b]	315	1			T68	3		T88	3		T4	6
valid_sources[0x3c]	40	1			T17	2		T22	2		T47	2
valid_sources[0x3d]	160	1			T17	2		T19	6		T22	2
valid_sources[0x3e]	175	1			T17	5		T22	5		T47	5
valid_sources[0x3f]	600	1			T17	23		T19	3		T22	23
valid_sources[0x40]	300	1			T19	15		T24	15		T30	15
valid_sources[0x41]	100	1			T17	2		T22	2		T47	2
valid_sources[0x42]	240	1			T17	7		T19	5		T22	7
valid_sources[0x43]	180	1			T17	1		T18	8		T22	1
valid_sources[0x44]	1320	1			T17	2		T18	5		T22	2
valid_sources[0x45]	140	1			T17	4		T18	3		T22	4
valid_sources[0x46]	120	1			T17	6		T22	6		T47	6
valid_sources[0x48]	290	1			T18	14		T21	1		T25	14
valid_sources[0x49]	85	1			T17	3		T22	3		T47	3
valid_sources[0x4a]	540	1			T17	9		T18	17		T21	4
valid_sources[0x4b]	200	1			T17	6		T22	6		T47	6
valid_sources[0x4c]	145	1			T17	7		T22	7		T47	7
valid_sources[0x4d]	40	1			T18	2		T25	2		T46	2
valid_sources[0x50]	320	1			T18	16		T25	16		T46	16
valid_sources[0x51]	60	1			T57	3		T58	3		T70	3
valid_sources[0x52]	80	1			T18	4		T25	4		T46	4
valid_sources[0x53]	150	1			T5	3		T12	3		T73	3
valid_sources[0x54]	55	1			T21	10		T78	10		T68	1
valid_sources[0x55]	80	1			T18	1		T19	3		T24	3
valid_sources[0x56]	360	1			T17	5		T18	8		T22	5
valid_sources[0x57]	5	1			T59	1		T76	1		T85	1
valid_sources[0x58]	315	1			T19	10		T24	10		T30	10
valid_sources[0x59]	160	1			T17	8		T22	8		T47	8
valid_sources[0x5a]	210	1			T18	10		T25	10		T46	10
valid_sources[0x5b]	220	1			T19	10		T24	10		T30	10
valid_sources[0x5c]	470	1			T17	22		T22	22		T47	22
valid_sources[0x5d]	210	1			T19	10		T24	10		T30	10
valid_sources[0x5e]	180	1			T17	1		T18	8		T22	1
valid_sources[0x5f]	40	1			T57	2		T58	2		T70	2
valid_sources[0x60]	20	1			T19	1		T24	1		T30	1
valid_sources[0x61]	160	1			T17	1		T22	1		T47	1
valid_sources[0x62]	180	1			T17	9		T22	9		T47	9
valid_sources[0x63]	165	1			T17	2		T18	1		T19	5
valid_sources[0x65]	260	1			T17	1		T18	12		T22	1
valid_sources[0x66]	20	1			T57	1		T58	1		T70	1
valid_sources[0x67]	720	1			T17	6		T22	6		T47	6
valid_sources[0x68]	360	1			T17	12		T18	5		T22	12
valid_sources[0x69]	620	1			T17	9		T18	2		T19	18
valid_sources[0x6a]	60	1			T57	3		T58	3		T70	3
valid_sources[0x6b]	305	1			T17	1		T18	6		T19	5
valid_sources[0x6c]	135	1			T57	4		T58	4		T59	11
valid_sources[0x6d]	300	1			T18	15		T25	15		T46	15
valid_sources[0x6e]	265	1			T17	2		T18	9		T22	2
valid_sources[0x6f]	240	1			T17	1		T19	5		T22	1
valid_sources[0x70]	225	1			T19	4		T24	4		T30	4
valid_sources[0x71]	280	1			T20	4		T23	10		T26	10
valid_sources[0x72]	160	1			T17	3		T22	3		T47	3
valid_sources[0x73]	5	1			T68	1		T88	1		T89	1
valid_sources[0x74]	120	1			T57	6		T58	6		T70	6
valid_sources[0x75]	20	1			T59	4		T76	4		T85	4
valid_sources[0x76]	240	1			T17	11		T18	1		T22	11
valid_sources[0x77]	20	1			T18	1		T25	1		T46	1
valid_sources[0x78]	300	1			T18	6		T19	9		T24	9
valid_sources[0x79]	185	1			T19	5		T24	5		T30	5
valid_sources[0x7a]	260	1			T17	5		T19	3		T20	5
valid_sources[0x7d]	100	1			T19	5		T24	5		T30	5
valid_sources[0x7f]	120	1			T18	3		T19	2		T24	2
valid_sources[0x80]	60	1			T17	3		T22	3		T47	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7305

1

T17

152

T18

11

T19

11

values[0x0]

all_enables

biggest_size

12740

1

T17

180

T18

151

T19

162

values[0x1]

all_enables

biggest_size

13375

1

T17

177

T18

183

T19

168

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19940	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14570

1

T17

583

T18

1

T19

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	22450	1			T17	149		T18	9		T19	40
values[0x0]	4680	1			T17	223		T18	3		T20	8
values[0x1]	7380	1			T17	357		T18	5		T20	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26860

1

T17

679

T18

10

T19

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	18	111	86.05

User Defined Bins for cp_source

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
valid_sources[0x03]	0	1	1
valid_sources[0x0c]	0	1	1
valid_sources[0x13]	0	1	1
valid_sources[0x1c]	0	1	1
valid_sources[0x21]	0	1	1
valid_sources[0x25]	0	1	1
valid_sources[0x2c]	0	1	1
valid_sources[0x3e]	0	1	1
valid_sources[0x49]	0	1	1
valid_sources[0x4a]	0	1	1
valid_sources[0x4c]	0	1	1
valid_sources[0x53]	0	1	1
valid_sources[0x5e]	0	1	1
valid_sources[0x6a]	0	1	1
valid_sources[0x6b]	0	1	1
valid_sources[0x74]	0	1	1
valid_sources[0x79]	0	1	1
valid_sources[0x7c]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	60	1			T17	3		T22	3		T47	3
valid_sources[0x01]	90	1			T17	2		T22	2		T47	2
valid_sources[0x02]	410	1			T17	3		T22	3		T47	3
valid_sources[0x04]	40	1			T17	2		T22	2		T47	2
valid_sources[0x05]	20	1			T17	1		T22	1		T47	1
valid_sources[0x06]	60	1			T17	3		T22	3		T47	3
valid_sources[0x07]	140	1			T17	2		T22	2		T47	2
valid_sources[0x08]	80	1			T17	4		T22	4		T47	4
valid_sources[0x09]	80	1			T17	1		T20	3		T22	1
valid_sources[0x0a]	100	1			T17	5		T22	5		T47	5
valid_sources[0x0b]	60	1			T17	3		T22	3		T47	3
valid_sources[0x0d]	760	1			T17	3		T22	3		T47	3
valid_sources[0x0e]	60	1			T17	3		T22	3		T47	3
valid_sources[0x0f]	100	1			T17	5		T22	5		T47	5
valid_sources[0x10]	290	1			T17	7		T22	7		T47	7
valid_sources[0x11]	50	1			T5	1		T12	1		T73	1
valid_sources[0x12]	150	1			T2	3		T72	3		T80	3
valid_sources[0x14]	150	1			T17	5		T22	5		T47	5
valid_sources[0x15]	40	1			T17	2		T22	2		T47	2
valid_sources[0x16]	110	1			T17	3		T22	3		T47	3
valid_sources[0x17]	20	1			T17	1		T22	1		T47	1
valid_sources[0x18]	150	1			T17	5		T22	5		T47	5
valid_sources[0x19]	70	1			T17	1		T22	1		T47	1
valid_sources[0x1a]	20	1			T17	1		T22	1		T47	1
valid_sources[0x1b]	40	1			T17	2		T22	2		T47	2
valid_sources[0x1d]	40	1			T17	2		T22	2		T47	2
valid_sources[0x1e]	140	1			T17	7		T22	7		T47	7
valid_sources[0x1f]	20	1			T17	1		T22	1		T47	1
valid_sources[0x20]	20	1			T17	1		T22	1		T47	1
valid_sources[0x22]	780	1			T17	9		T22	9		T47	9
valid_sources[0x23]	340	1			T17	2		T22	2		T47	2
valid_sources[0x24]	100	1			T17	1		T19	4		T22	1
valid_sources[0x26]	340	1			T17	1		T20	1		T22	1
valid_sources[0x27]	40	1			T17	2		T22	2		T47	2
valid_sources[0x28]	80	1			T17	4		T22	4		T47	4
valid_sources[0x29]	20	1			T17	1		T22	1		T47	1
valid_sources[0x2a]	180	1			T17	8		T20	1		T22	8
valid_sources[0x2b]	250	1			T17	4		T20	1		T22	4
valid_sources[0x2d]	40	1			T17	2		T22	2		T47	2
valid_sources[0x2e]	40	1			T17	2		T22	2		T47	2
valid_sources[0x2f]	120	1			T17	6		T22	6		T47	6
valid_sources[0x30]	80	1			T17	4		T22	4		T47	4
valid_sources[0x31]	20	1			T17	1		T22	1		T47	1
valid_sources[0x32]	160	1			T19	3		T24	3		T30	3
valid_sources[0x33]	60	1			T17	3		T22	3		T47	3
valid_sources[0x34]	60	1			T17	3		T22	3		T47	3
valid_sources[0x35]	60	1			T17	3		T22	3		T47	3
valid_sources[0x36]	270	1			T17	1		T22	1		T47	1
valid_sources[0x37]	440	1			T17	7		T22	7		T47	7
valid_sources[0x38]	60	1			T17	3		T22	3		T47	3
valid_sources[0x39]	410	1			T17	3		T22	3		T47	3
valid_sources[0x3a]	1050	1			T17	2		T18	3		T19	2
valid_sources[0x3b]	50	1			T6	1		T7	1		T13	1
valid_sources[0x3c]	120	1			T17	6		T22	6		T47	6
valid_sources[0x3d]	100	1			T17	5		T22	5		T47	5
valid_sources[0x3f]	80	1			T17	4		T22	4		T47	4
valid_sources[0x40]	20	1			T17	1		T22	1		T47	1
valid_sources[0x41]	80	1			T17	4		T22	4		T47	4
valid_sources[0x42]	170	1			T17	6		T22	6		T47	6
valid_sources[0x43]	20	1			T17	1		T22	1		T47	1
valid_sources[0x44]	50	1			T5	1		T12	1		T73	1
valid_sources[0x45]	100	1			T17	5		T22	5		T47	5
valid_sources[0x46]	160	1			T17	3		T22	3		T47	3
valid_sources[0x47]	120	1			T17	6		T22	6		T47	6
valid_sources[0x48]	40	1			T17	2		T22	2		T47	2
valid_sources[0x4b]	770	1			T17	6		T22	6		T47	6
valid_sources[0x4d]	140	1			T17	2		T22	2		T47	2
valid_sources[0x4e]	440	1			T17	7		T22	7		T47	7
valid_sources[0x4f]	220	1			T17	1		T22	1		T47	1
valid_sources[0x50]	200	1			T17	5		T19	5		T22	5
valid_sources[0x51]	70	1			T17	1		T22	1		T47	1
valid_sources[0x52]	100	1			T17	5		T22	5		T47	5
valid_sources[0x54]	20	1			T17	1		T22	1		T47	1
valid_sources[0x55]	60	1			T17	3		T22	3		T47	3
valid_sources[0x56]	20	1			T17	1		T22	1		T47	1
valid_sources[0x57]	180	1			T17	9		T22	9		T47	9
valid_sources[0x58]	40	1			T17	2		T22	2		T47	2
valid_sources[0x59]	40	1			T17	2		T22	2		T47	2
valid_sources[0x5a]	20	1			T17	1		T22	1		T47	1
valid_sources[0x5b]	20	1			T17	1		T22	1		T47	1
valid_sources[0x5c]	60	1			T17	3		T22	3		T47	3
valid_sources[0x5d]	380	1			T17	19		T22	19		T47	19
valid_sources[0x5f]	20	1			T17	1		T22	1		T47	1
valid_sources[0x60]	160	1			T17	4		T19	4		T22	4
valid_sources[0x61]	60	1			T17	3		T22	3		T47	3
valid_sources[0x62]	60	1			T17	3		T22	3		T47	3
valid_sources[0x63]	100	1			T17	5		T22	5		T47	5
valid_sources[0x64]	20	1			T17	1		T22	1		T47	1
valid_sources[0x65]	160	1			T17	8		T22	8		T47	8
valid_sources[0x66]	140	1			T17	7		T22	7		T47	7
valid_sources[0x67]	300	1			T17	5		T22	5		T47	5
valid_sources[0x68]	810	1			T17	3		T22	3		T47	3
valid_sources[0x69]	40	1			T17	2		T22	2		T47	2
valid_sources[0x6c]	200	1			T17	10		T22	10		T47	10
valid_sources[0x6d]	80	1			T17	4		T22	4		T47	4
valid_sources[0x6e]	140	1			T17	2		T22	2		T47	2
valid_sources[0x6f]	110	1			T17	3		T22	3		T47	3
valid_sources[0x70]	40	1			T17	2		T22	2		T47	2
valid_sources[0x71]	250	1			T17	10		T22	10		T47	10
valid_sources[0x72]	20	1			T17	1		T22	1		T47	1
valid_sources[0x73]	80	1			T17	2		T18	2		T22	2
valid_sources[0x75]	40	1			T17	2		T22	2		T47	2
valid_sources[0x76]	40	1			T17	2		T22	2		T47	2
valid_sources[0x77]	110	1			T17	3		T22	3		T47	3
valid_sources[0x78]	90	1			T17	2		T22	2		T47	2
valid_sources[0x7a]	20	1			T17	1		T22	1		T47	1
valid_sources[0x7b]	440	1			T17	2		T22	2		T47	2
valid_sources[0x7d]	100	1			T17	5		T22	5		T47	5
valid_sources[0x7e]	560	1			T17	9		T19	14		T22	9
valid_sources[0x7f]	460	1			T17	3		T22	3		T47	3
valid_sources[0x80]	40	1			T17	2		T22	2		T47	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5690

1

T17

149

T18

1

T19

40

values[0x0]

all_enables

biggest_size

4340

1

T17

211

T20

6

T22

211

values[0x1]

all_enables

biggest_size

4540

1

T17

223

T20

4

T22

223