SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_chk | 88.79 | 88.79 | |||||
tb.dut.u_reg_regs.u_chk.u_chk | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
88.79 | 88.79 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
88.79 | 88.79 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_cmd_intg_check.u_cmd_intg_chk |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_chk |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 4 | 4 | 100.00 |
Total Bits | 232 | 232 | 100.00 |
Total Bits 0->1 | 116 | 116 | 100.00 |
Total Bits 1->0 | 116 | 116 | 100.00 |
Ports | 4 | 4 | 100.00 |
Port Bits | 232 | 232 | 100.00 |
Port Bits 0->1 | 116 | 116 | 100.00 |
Port Bits 1->0 | 116 | 116 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] | Yes | Yes | T17,T18,*T19 | Yes | T17,T18,T19 | INPUT |
data_i[56:43] | Unreachable | Unreachable | Unreachable | INPUT | ||
data_i[63:57] | Yes | Yes | T17,T18,T19 | Yes | T17,T18,T19 | INPUT |
data_o[56:0] | Yes | Yes | T17,T18,T19 | Yes | T17,T18,T19 | OUTPUT |
syndrome_o[6:0] | Yes | Yes | T17,T18,T19 | Yes | T17,T18,T19 | OUTPUT |
err_o[1:0] | Yes | Yes | T17,T18,T19 | Yes | T17,T18,T19 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 4 | 2 | 50.00 |
Total Bits | 232 | 206 | 88.79 |
Total Bits 0->1 | 116 | 103 | 88.79 |
Total Bits 1->0 | 116 | 103 | 88.79 |
Ports | 4 | 2 | 50.00 |
Port Bits | 232 | 206 | 88.79 |
Port Bits 0->1 | 116 | 103 | 88.79 |
Port Bits 1->0 | 116 | 103 | 88.79 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] | Yes | Yes | T17,*T18,T20 | Yes | T17,T18,T20 | INPUT |
data_i[56:43] | Unreachable | Unreachable | Unreachable | INPUT | ||
data_i[63:57] | Yes | Yes | T17,T18,T19 | Yes | T17,T18,T19 | INPUT |
data_o[42:0] | Yes | Yes | T17,*T18,T20 | Yes | T17,T18,T20 | OUTPUT |
data_o[45:43] | No | No | No | OUTPUT | ||
data_o[46] | Yes | Yes | *T18,*T25,*T46 | Yes | T18,T25,T46 | OUTPUT |
data_o[54:47] | No | No | No | OUTPUT | ||
data_o[55] | Yes | Yes | *T18,*T25,*T46 | Yes | T18,T25,T46 | OUTPUT |
data_o[56] | No | No | No | OUTPUT | ||
syndrome_o[6:0] | Yes | Yes | T18,T25,T46 | Yes | T18,T25,T46 | OUTPUT |
err_o[0] | Yes | Yes | *T18,*T25,*T46 | Yes | T18,T25,T46 | OUTPUT |
err_o[1] | No | No | No | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 4 | 4 | 100.00 |
Total Bits | 232 | 232 | 100.00 |
Total Bits 0->1 | 116 | 116 | 100.00 |
Total Bits 1->0 | 116 | 116 | 100.00 |
Ports | 4 | 4 | 100.00 |
Port Bits | 232 | 232 | 100.00 |
Port Bits 0->1 | 116 | 116 | 100.00 |
Port Bits 1->0 | 116 | 116 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] | Yes | Yes | T17,T18,*T19 | Yes | T17,T18,T19 | INPUT |
data_i[56:43] | Unreachable | Unreachable | Unreachable | INPUT | ||
data_i[63:57] | Yes | Yes | T17,T18,T19 | Yes | T17,T18,T19 | INPUT |
data_o[56:0] | Yes | Yes | T17,T18,T19 | Yes | T17,T18,T19 | OUTPUT |
syndrome_o[6:0] | Yes | Yes | T17,T18,T19 | Yes | T17,T18,T19 | OUTPUT |
err_o[1:0] | Yes | Yes | T17,T18,T19 | Yes | T17,T18,T19 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |