Module Definition
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Module : rom_ctrl_rom_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_rom_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_rom_top 100.00 100.00 100.00



Module Instance : tb.dut.u_rom_top

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 98.28 97.33 100.00 79.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_rsp_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rom_ctrl_rom_reg_top
Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS3633100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6500
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_rom_reg_top.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_rom_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
36 1 1
37 1 1
39 1 1
59 1 1
60 1 1
65 unreachable


Branch Coverage for Module : rom_ctrl_rom_reg_top
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 36 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_rom_reg_top.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_rom_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 36 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T17,T18,T19
0 Covered T17,T18,T19

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%