Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.81	86.13	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	85.40	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	86.86	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.40	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	20	114	85.07
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	20	109	84.50	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.86	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	18	116	86.57
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	18	111	86.05	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10305	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33420

1

T19

34

T20

33

T21

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14320	1			T19	4		T20	4		T21	4
values[0x0]	14040	1			T19	18		T20	17		T21	17
values[0x1]	15365	1			T19	17		T20	18		T21	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7825	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35900

1

T19

34

T20

36

T21

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	20	109	84.50

User Defined Bins for cp_source

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
valid_sources[0x03]	0	1	1
valid_sources[0x07]	0	1	1
valid_sources[0x08]	0	1	1
valid_sources[0x10]	0	1	1
valid_sources[0x17]	0	1	1
valid_sources[0x1d]	0	1	1
valid_sources[0x21]	0	1	1
valid_sources[0x24]	0	1	1
valid_sources[0x2d]	0	1	1
valid_sources[0x2e]	0	1	1
valid_sources[0x2f]	0	1	1
valid_sources[0x32]	0	1	1
valid_sources[0x39]	0	1	1
valid_sources[0x47]	0	1	1
valid_sources[0x4e]	0	1	1
valid_sources[0x4f]	0	1	1
valid_sources[0x64]	0	1	1
valid_sources[0x7b]	0	1	1
valid_sources[0x7c]	0	1	1
valid_sources[0x7e]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	100	1			T26	5		T27	5		T44	5
valid_sources[0x01]	115	1			T26	4		T27	4		T44	4
valid_sources[0x02]	60	1			T31	3		T32	3		T45	3
valid_sources[0x04]	15	1			T58	1		T82	1		T83	2
valid_sources[0x05]	315	1			T58	11		T31	13		T32	13
valid_sources[0x06]	380	1			T26	9		T27	9		T44	9
valid_sources[0x09]	280	1			T26	14		T27	14		T44	14
valid_sources[0x0a]	45	1			T58	1		T31	2		T32	2
valid_sources[0x0b]	245	1			T58	1		T31	12		T32	12
valid_sources[0x0c]	110	1			T19	6		T23	3		T33	3
valid_sources[0x0d]	480	1			T23	14		T26	10		T27	10
valid_sources[0x0e]	200	1			T23	8		T33	8		T50	1
valid_sources[0x0f]	160	1			T26	6		T27	6		T50	2
valid_sources[0x11]	320	1			T23	16		T33	16		T34	16
valid_sources[0x12]	200	1			T23	8		T26	2		T27	2
valid_sources[0x13]	40	1			T26	2		T27	2		T44	2
valid_sources[0x14]	135	1			T83	27		T84	27		T85	27
valid_sources[0x15]	260	1			T24	13		T49	13		T56	13
valid_sources[0x16]	40	1			T31	2		T32	2		T45	2
valid_sources[0x18]	500	1			T20	7		T21	7		T22	7
valid_sources[0x19]	20	1			T31	1		T32	1		T45	1
valid_sources[0x1a]	1260	1			T26	52		T27	52		T50	1
valid_sources[0x1b]	180	1			T24	1		T31	8		T32	8
valid_sources[0x1c]	40	1			T50	2		T73	2		T74	2
valid_sources[0x1e]	165	1			T58	1		T31	8		T32	8
valid_sources[0x1f]	50	1			T24	2		T49	2		T56	2
valid_sources[0x20]	500	1			T26	6		T27	6		T44	6
valid_sources[0x22]	50	1			T23	2		T33	2		T34	2
valid_sources[0x23]	120	1			T26	6		T27	6		T44	6
valid_sources[0x25]	140	1			T83	28		T84	28		T85	28
valid_sources[0x26]	50	1			T83	10		T84	10		T85	10
valid_sources[0x27]	20	1			T20	1		T21	1		T22	1
valid_sources[0x28]	80	1			T50	1		T73	1		T74	1
valid_sources[0x29]	15	1			T83	3		T84	3		T85	3
valid_sources[0x2a]	530	1			T19	6		T23	3		T26	19
valid_sources[0x2b]	340	1			T20	2		T21	2		T22	2
valid_sources[0x2c]	250	1			T26	1		T27	1		T44	1
valid_sources[0x30]	60	1			T23	3		T33	3		T34	3
valid_sources[0x31]	190	1			T23	2		T33	2		T34	2
valid_sources[0x33]	40	1			T31	2		T32	2		T45	2
valid_sources[0x34]	80	1			T31	4		T32	4		T45	4
valid_sources[0x35]	5	1			T58	1		T82	1		T86	1
valid_sources[0x36]	200	1			T50	10		T73	10		T74	10
valid_sources[0x37]	220	1			T20	7		T21	7		T22	7
valid_sources[0x38]	60	1			T26	3		T27	3		T44	3
valid_sources[0x3a]	95	1			T31	2		T32	2		T45	2
valid_sources[0x3b]	315	1			T58	3		T82	3		T5	6
valid_sources[0x3c]	40	1			T31	2		T32	2		T45	2
valid_sources[0x3d]	160	1			T23	6		T33	6		T34	6
valid_sources[0x3e]	175	1			T31	5		T32	5		T45	5
valid_sources[0x3f]	600	1			T23	3		T33	3		T50	4
valid_sources[0x40]	300	1			T23	15		T33	15		T34	15
valid_sources[0x41]	100	1			T50	3		T73	3		T74	3
valid_sources[0x42]	240	1			T23	5		T33	5		T34	5
valid_sources[0x43]	180	1			T26	8		T27	8		T44	8
valid_sources[0x44]	1320	1			T26	5		T27	5		T50	14
valid_sources[0x45]	140	1			T26	3		T27	3		T44	3
valid_sources[0x46]	120	1			T31	6		T32	6		T45	6
valid_sources[0x48]	290	1			T19	1		T26	14		T27	14
valid_sources[0x49]	85	1			T31	3		T32	3		T45	3
valid_sources[0x4a]	540	1			T19	4		T26	17		T27	17
valid_sources[0x4b]	200	1			T50	4		T73	4		T74	4
valid_sources[0x4c]	145	1			T58	1		T31	7		T32	7
valid_sources[0x4d]	40	1			T26	2		T27	2		T44	2
valid_sources[0x50]	320	1			T26	16		T27	16		T44	16
valid_sources[0x51]	60	1			T50	3		T73	3		T74	3
valid_sources[0x52]	80	1			T26	4		T27	4		T44	4
valid_sources[0x53]	150	1			T2	3		T6	3		T15	3
valid_sources[0x54]	55	1			T19	10		T58	1		T87	10
valid_sources[0x55]	80	1			T23	3		T26	1		T27	1
valid_sources[0x56]	360	1			T26	8		T27	8		T50	5
valid_sources[0x57]	5	1			T83	1		T84	1		T85	1
valid_sources[0x58]	315	1			T23	10		T33	10		T34	10
valid_sources[0x59]	160	1			T31	8		T32	8		T45	8
valid_sources[0x5a]	210	1			T26	10		T27	10		T44	10
valid_sources[0x5b]	220	1			T23	10		T33	10		T50	1
valid_sources[0x5c]	470	1			T58	6		T31	22		T32	22
valid_sources[0x5d]	210	1			T23	10		T33	10		T34	10
valid_sources[0x5e]	180	1			T26	8		T27	8		T44	8
valid_sources[0x5f]	40	1			T50	2		T73	2		T74	2
valid_sources[0x60]	20	1			T23	1		T33	1		T34	1
valid_sources[0x61]	160	1			T50	7		T73	7		T74	7
valid_sources[0x62]	180	1			T31	9		T32	9		T45	9
valid_sources[0x63]	165	1			T23	5		T26	1		T27	1
valid_sources[0x65]	260	1			T26	12		T27	12		T44	12
valid_sources[0x66]	20	1			T50	1		T73	1		T74	1
valid_sources[0x67]	720	1			T50	30		T73	30		T74	30
valid_sources[0x68]	360	1			T26	5		T27	5		T50	1
valid_sources[0x69]	620	1			T23	18		T26	2		T27	2
valid_sources[0x6a]	60	1			T50	3		T73	3		T74	3
valid_sources[0x6b]	305	1			T23	5		T26	6		T27	6
valid_sources[0x6c]	135	1			T50	4		T73	4		T74	4
valid_sources[0x6d]	300	1			T26	15		T27	15		T44	15
valid_sources[0x6e]	265	1			T20	2		T21	2		T22	2
valid_sources[0x6f]	240	1			T23	5		T33	5		T34	5
valid_sources[0x70]	225	1			T23	4		T33	4		T34	4
valid_sources[0x71]	280	1			T20	10		T21	10		T22	10
valid_sources[0x72]	160	1			T50	5		T73	5		T74	5
valid_sources[0x73]	5	1			T58	1		T82	1		T86	1
valid_sources[0x74]	120	1			T50	6		T73	6		T74	6
valid_sources[0x75]	20	1			T83	4		T84	4		T85	4
valid_sources[0x76]	240	1			T26	1		T27	1		T44	1
valid_sources[0x77]	20	1			T26	1		T27	1		T44	1
valid_sources[0x78]	300	1			T23	9		T26	6		T27	6
valid_sources[0x79]	185	1			T23	5		T33	5		T50	4
valid_sources[0x7a]	260	1			T23	3		T24	5		T33	3
valid_sources[0x7d]	100	1			T23	5		T33	5		T34	5
valid_sources[0x7f]	120	1			T23	2		T26	3		T27	3
valid_sources[0x80]	60	1			T31	3		T32	3		T45	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7305

1

T19

2

T20

1

T21

1

values[0x0]

all_enables

biggest_size

12740

1

T19

16

T20

17

T21

17

values[0x1]

all_enables

biggest_size

13375

1

T19

16

T20

15

T21

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19940	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14570

1

T23

40

T24

12

T26

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	22450	1			T23	40		T24	2		T26	9
values[0x0]	4680	1			T24	8		T26	3		T27	3
values[0x1]	7380	1			T24	7		T26	5		T27	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26860

1

T23

40

T24

14

T26

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	18	111	86.05

User Defined Bins for cp_source

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
valid_sources[0x03]	0	1	1
valid_sources[0x0c]	0	1	1
valid_sources[0x13]	0	1	1
valid_sources[0x1c]	0	1	1
valid_sources[0x21]	0	1	1
valid_sources[0x25]	0	1	1
valid_sources[0x2c]	0	1	1
valid_sources[0x3e]	0	1	1
valid_sources[0x49]	0	1	1
valid_sources[0x4a]	0	1	1
valid_sources[0x4c]	0	1	1
valid_sources[0x53]	0	1	1
valid_sources[0x5e]	0	1	1
valid_sources[0x6a]	0	1	1
valid_sources[0x6b]	0	1	1
valid_sources[0x74]	0	1	1
valid_sources[0x79]	0	1	1
valid_sources[0x7c]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	60	1			T31	3		T32	3		T45	3
valid_sources[0x01]	90	1			T31	2		T32	2		T45	2
valid_sources[0x02]	410	1			T31	3		T32	3		T45	3
valid_sources[0x04]	40	1			T31	2		T32	2		T45	2
valid_sources[0x05]	20	1			T31	1		T32	1		T45	1
valid_sources[0x06]	60	1			T31	3		T32	3		T45	3
valid_sources[0x07]	140	1			T31	2		T32	2		T45	2
valid_sources[0x08]	80	1			T31	4		T32	4		T45	4
valid_sources[0x09]	80	1			T24	3		T31	1		T32	1
valid_sources[0x0a]	100	1			T31	5		T32	5		T45	5
valid_sources[0x0b]	60	1			T31	3		T32	3		T45	3
valid_sources[0x0d]	760	1			T31	3		T32	3		T45	3
valid_sources[0x0e]	60	1			T31	3		T32	3		T45	3
valid_sources[0x0f]	100	1			T31	5		T32	5		T45	5
valid_sources[0x10]	290	1			T31	7		T32	7		T45	7
valid_sources[0x11]	50	1			T2	1		T6	1		T15	1
valid_sources[0x12]	150	1			T11	3		T12	3		T14	3
valid_sources[0x14]	150	1			T31	5		T32	5		T45	5
valid_sources[0x15]	40	1			T31	2		T32	2		T45	2
valid_sources[0x16]	110	1			T31	3		T32	3		T45	3
valid_sources[0x17]	20	1			T31	1		T32	1		T45	1
valid_sources[0x18]	150	1			T31	5		T32	5		T45	5
valid_sources[0x19]	70	1			T31	1		T32	1		T45	1
valid_sources[0x1a]	20	1			T31	1		T32	1		T45	1
valid_sources[0x1b]	40	1			T31	2		T32	2		T45	2
valid_sources[0x1d]	40	1			T31	2		T32	2		T45	2
valid_sources[0x1e]	140	1			T31	7		T32	7		T45	7
valid_sources[0x1f]	20	1			T31	1		T32	1		T45	1
valid_sources[0x20]	20	1			T31	1		T32	1		T45	1
valid_sources[0x22]	780	1			T31	9		T32	9		T45	9
valid_sources[0x23]	340	1			T31	2		T32	2		T45	2
valid_sources[0x24]	100	1			T23	4		T33	4		T34	4
valid_sources[0x26]	340	1			T24	1		T31	1		T32	1
valid_sources[0x27]	40	1			T31	2		T32	2		T45	2
valid_sources[0x28]	80	1			T31	4		T32	4		T45	4
valid_sources[0x29]	20	1			T31	1		T32	1		T45	1
valid_sources[0x2a]	180	1			T24	1		T31	8		T32	8
valid_sources[0x2b]	250	1			T24	1		T31	4		T32	4
valid_sources[0x2d]	40	1			T31	2		T32	2		T45	2
valid_sources[0x2e]	40	1			T31	2		T32	2		T45	2
valid_sources[0x2f]	120	1			T31	6		T32	6		T45	6
valid_sources[0x30]	80	1			T31	4		T32	4		T45	4
valid_sources[0x31]	20	1			T31	1		T32	1		T45	1
valid_sources[0x32]	160	1			T23	3		T33	3		T34	3
valid_sources[0x33]	60	1			T31	3		T32	3		T45	3
valid_sources[0x34]	60	1			T31	3		T32	3		T45	3
valid_sources[0x35]	60	1			T31	3		T32	3		T45	3
valid_sources[0x36]	270	1			T31	1		T32	1		T45	1
valid_sources[0x37]	440	1			T31	7		T32	7		T45	7
valid_sources[0x38]	60	1			T31	3		T32	3		T45	3
valid_sources[0x39]	410	1			T31	3		T32	3		T45	3
valid_sources[0x3a]	1050	1			T23	2		T24	3		T26	3
valid_sources[0x3b]	50	1			T4	1		T13	1		T37	1
valid_sources[0x3c]	120	1			T31	6		T32	6		T45	6
valid_sources[0x3d]	100	1			T31	5		T32	5		T45	5
valid_sources[0x3f]	80	1			T31	4		T32	4		T45	4
valid_sources[0x40]	20	1			T31	1		T32	1		T45	1
valid_sources[0x41]	80	1			T31	4		T32	4		T45	4
valid_sources[0x42]	170	1			T31	6		T32	6		T45	6
valid_sources[0x43]	20	1			T31	1		T32	1		T45	1
valid_sources[0x44]	50	1			T2	1		T6	1		T15	1
valid_sources[0x45]	100	1			T31	5		T32	5		T45	5
valid_sources[0x46]	160	1			T31	3		T32	3		T45	3
valid_sources[0x47]	120	1			T31	6		T32	6		T45	6
valid_sources[0x48]	40	1			T31	2		T32	2		T45	2
valid_sources[0x4b]	770	1			T31	6		T32	6		T45	6
valid_sources[0x4d]	140	1			T31	2		T32	2		T45	2
valid_sources[0x4e]	440	1			T31	7		T32	7		T45	7
valid_sources[0x4f]	220	1			T31	1		T32	1		T45	1
valid_sources[0x50]	200	1			T23	5		T33	5		T34	5
valid_sources[0x51]	70	1			T31	1		T32	1		T45	1
valid_sources[0x52]	100	1			T31	5		T32	5		T45	5
valid_sources[0x54]	20	1			T31	1		T32	1		T45	1
valid_sources[0x55]	60	1			T31	3		T32	3		T45	3
valid_sources[0x56]	20	1			T31	1		T32	1		T45	1
valid_sources[0x57]	180	1			T31	9		T32	9		T45	9
valid_sources[0x58]	40	1			T31	2		T32	2		T45	2
valid_sources[0x59]	40	1			T31	2		T32	2		T45	2
valid_sources[0x5a]	20	1			T31	1		T32	1		T45	1
valid_sources[0x5b]	20	1			T31	1		T32	1		T45	1
valid_sources[0x5c]	60	1			T31	3		T32	3		T45	3
valid_sources[0x5d]	380	1			T31	19		T32	19		T45	19
valid_sources[0x5f]	20	1			T31	1		T32	1		T45	1
valid_sources[0x60]	160	1			T23	4		T33	4		T34	4
valid_sources[0x61]	60	1			T31	3		T32	3		T45	3
valid_sources[0x62]	60	1			T31	3		T32	3		T45	3
valid_sources[0x63]	100	1			T31	5		T32	5		T45	5
valid_sources[0x64]	20	1			T31	1		T32	1		T45	1
valid_sources[0x65]	160	1			T31	8		T32	8		T45	8
valid_sources[0x66]	140	1			T31	7		T32	7		T45	7
valid_sources[0x67]	300	1			T31	5		T32	5		T45	5
valid_sources[0x68]	810	1			T31	3		T32	3		T45	3
valid_sources[0x69]	40	1			T31	2		T32	2		T45	2
valid_sources[0x6c]	200	1			T31	10		T32	10		T45	10
valid_sources[0x6d]	80	1			T31	4		T32	4		T45	4
valid_sources[0x6e]	140	1			T31	2		T32	2		T45	2
valid_sources[0x6f]	110	1			T31	3		T32	3		T45	3
valid_sources[0x70]	40	1			T31	2		T32	2		T45	2
valid_sources[0x71]	250	1			T31	10		T32	10		T45	10
valid_sources[0x72]	20	1			T31	1		T32	1		T45	1
valid_sources[0x73]	80	1			T26	2		T27	2		T44	2
valid_sources[0x75]	40	1			T31	2		T32	2		T45	2
valid_sources[0x76]	40	1			T31	2		T32	2		T45	2
valid_sources[0x77]	110	1			T31	3		T32	3		T45	3
valid_sources[0x78]	90	1			T31	2		T32	2		T45	2
valid_sources[0x7a]	20	1			T31	1		T32	1		T45	1
valid_sources[0x7b]	440	1			T31	2		T32	2		T45	2
valid_sources[0x7d]	100	1			T31	5		T32	5		T45	5
valid_sources[0x7e]	560	1			T23	14		T33	14		T34	14
valid_sources[0x7f]	460	1			T31	3		T32	3		T45	3
valid_sources[0x80]	40	1			T31	2		T32	2		T45	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5690

1

T23

40

T24

2

T26

1

values[0x0]

all_enables

biggest_size

4340

1

T24

6

T31

211

T32

211

values[0x1]

all_enables

biggest_size

4540

1

T24

4

T31

223

T32

223