Unified Coverage Report :: Group :: tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_kmac_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	85.71	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
rom_ctrl_kmac_cg	85.71	1	100	1	64	64

---

Group Instance : rom_ctrl_kmac_cg
Comment: KMAC interface behaviors

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance rom_ctrl_kmac_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance rom_ctrl_kmac_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_kmac_done	3	0	3	100.00	100	1	1	0
cp_kmac_ready	4	1	3	75.00	100	1	1	0

Summary for Variable cp_kmac_done

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_kmac_done

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
kmac_first	70	1			T25	1		T31	1		T32	1
same_cycle	70	1			T25	1		T31	1		T32	1
rom_first	1810	1			T17	1		T18	1		T19	1

---

Summary for Variable cp_kmac_ready

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	1	3	75.00

User Defined Bins for cp_kmac_ready

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
zero_delay_5	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stall_repeat	138036960	1			T17	65386		T18	65606		T19	65386
stall_long	14542325	1			T17	6862		T18	6885		T19	6862
stall_1	546220	1			T17	253		T18	252		T19	253