Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.27 96.89 84.90 97.17 93.33 96.41 97.89 86.31


Total test records in report: 450
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T264 /workspace/coverage/default/0.rom_ctrl_smoke.13247977929428617970162779349648766524232951583195137454648934205629931370751 Nov 22 12:36:22 PM PST 23 Nov 22 12:36:52 PM PST 23 6265461576 ps
T265 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.31024975133487728974858666744317201480093298733151462619854687500125795058177 Nov 22 12:36:26 PM PST 23 Nov 22 12:36:54 PM PST 23 6233818126 ps
T266 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3321827575296243544483149301156546190566518255376151168276023454196651398310 Nov 22 12:36:38 PM PST 23 Nov 22 12:42:23 PM PST 23 69854280986 ps
T267 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.112792405505824271492218064198764284440694003014878248478569315873319733168501 Nov 22 12:36:48 PM PST 23 Nov 22 12:42:38 PM PST 23 69854280986 ps
T268 /workspace/coverage/default/48.rom_ctrl_stress_all.90877019884583614603204681190096019977379776554291377336542186160268645643867 Nov 22 12:38:15 PM PST 23 Nov 22 12:39:00 PM PST 23 9415977006 ps
T269 /workspace/coverage/default/34.rom_ctrl_smoke.99931358117124705088742407927181897712959119899229236796527745329734473020078 Nov 22 12:37:17 PM PST 23 Nov 22 12:37:51 PM PST 23 6265461576 ps
T270 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2605508378711506702625269623372880111250431342788918467308662522589239126597 Nov 22 12:37:15 PM PST 23 Nov 22 12:43:09 PM PST 23 69854280986 ps
T271 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.24460545756438979189212151736340409786044156751157425988062239948037577201360 Nov 22 12:36:27 PM PST 23 Nov 22 12:36:55 PM PST 23 6233818126 ps
T272 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.19328915015896076743466856184025628909240431547282449563754334863825045782829 Nov 22 12:37:05 PM PST 23 Nov 22 12:37:34 PM PST 23 6233818126 ps
T273 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.91436991107678241750638871312359009572547570108851107974496900772567903094099 Nov 22 12:36:49 PM PST 23 Nov 22 12:42:43 PM PST 23 69854280986 ps
T274 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.84075904698904920212076422060322830688548952641645122171675393886833326216963 Nov 22 12:37:15 PM PST 23 Nov 22 12:37:34 PM PST 23 3151732636 ps
T275 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.105822937958407823963329438419371492602089626898418346104852627072993834218389 Nov 22 12:37:32 PM PST 23 Nov 22 12:43:18 PM PST 23 69854280986 ps
T276 /workspace/coverage/default/11.rom_ctrl_smoke.72807559112134376646605164002288961315160111942579048858511000285067401638462 Nov 22 12:36:37 PM PST 23 Nov 22 12:37:07 PM PST 23 6265461576 ps
T277 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.25688938922731748355202217358598740145313998426272504137820193910831893992686 Nov 22 12:37:42 PM PST 23 Nov 22 12:38:14 PM PST 23 6233818126 ps
T278 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.90577739917244300843057552694383602043362883740582566770693536648584824935541 Nov 22 12:37:00 PM PST 23 Nov 22 12:37:27 PM PST 23 6233818126 ps
T279 /workspace/coverage/default/4.rom_ctrl_stress_all.81674511221688756908588223479936398100962585185341762610756101797204259993099 Nov 22 12:36:23 PM PST 23 Nov 22 12:37:07 PM PST 23 9415977006 ps
T280 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.16426382950155814155918650899920727406216932479969243500895479439670609876910 Nov 22 12:37:51 PM PST 23 Nov 22 12:43:40 PM PST 23 69854280986 ps
T281 /workspace/coverage/default/9.rom_ctrl_smoke.84444626298310007509077287740630472523413618702697026542663300621670366886346 Nov 22 12:36:28 PM PST 23 Nov 22 12:36:58 PM PST 23 6265461576 ps
T282 /workspace/coverage/default/38.rom_ctrl_stress_all.47143467929068033795102612281235116262786782720934995014152732844931382140585 Nov 22 12:37:44 PM PST 23 Nov 22 12:38:37 PM PST 23 9415977006 ps
T283 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.70283931938112158031139739228688865401746037300421616439469383921286286185679 Nov 22 12:37:08 PM PST 23 Nov 22 12:37:24 PM PST 23 3151732636 ps
T284 /workspace/coverage/default/43.rom_ctrl_stress_all.115039496894218677362919338255844898903967012890169949979746704312828842834891 Nov 22 12:37:50 PM PST 23 Nov 22 12:38:43 PM PST 23 9415977006 ps
T285 /workspace/coverage/default/42.rom_ctrl_alert_test.19043403146781221291666330223365018138385844788043323524237893601018632554597 Nov 22 12:37:49 PM PST 23 Nov 22 12:38:09 PM PST 23 3124113076 ps
T286 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.40381475771079245293134931787699846325893833772676430693548209417503468480108 Nov 22 12:36:48 PM PST 23 Nov 22 12:37:03 PM PST 23 3151732636 ps
T287 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.107712834847363138630810242240749428020678470523209766368250118360367743368448 Nov 22 12:37:53 PM PST 23 Nov 22 12:43:51 PM PST 23 69854280986 ps
T288 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.54152506383103866587436968449599014538665428894749924466028324394929939337396 Nov 22 12:37:13 PM PST 23 Nov 22 12:37:34 PM PST 23 3151732636 ps
T289 /workspace/coverage/default/40.rom_ctrl_smoke.75405575631129065675273215543454791552287878274184794973297123900017993772630 Nov 22 12:37:47 PM PST 23 Nov 22 12:38:25 PM PST 23 6265461576 ps
T290 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.42992898908468278892533225846428240599441519810439123136523105796967464764204 Nov 22 12:37:12 PM PST 23 Nov 22 12:37:46 PM PST 23 6233818126 ps
T291 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.89330752020887252084279963985907206196874788595793217264350502450975211918782 Nov 22 12:37:45 PM PST 23 Nov 22 12:38:22 PM PST 23 6233818126 ps
T34 /workspace/coverage/default/2.rom_ctrl_sec_cm.58051439570455269130579882294238392848366422840890097405975792667779387610596 Nov 22 12:36:25 PM PST 23 Nov 22 12:38:25 PM PST 23 3444857586 ps
T292 /workspace/coverage/default/15.rom_ctrl_alert_test.55252825394360401247219546253888942021129765564240419814733016180957579079012 Nov 22 12:36:48 PM PST 23 Nov 22 12:37:02 PM PST 23 3124113076 ps
T293 /workspace/coverage/default/28.rom_ctrl_stress_all.29354602328139289794538057090145353771093936573762869150497755050537713198261 Nov 22 12:37:02 PM PST 23 Nov 22 12:37:48 PM PST 23 9415977006 ps
T294 /workspace/coverage/default/22.rom_ctrl_smoke.34823968077978279516916913837590977607761187409228143438183646633027513326409 Nov 22 12:36:47 PM PST 23 Nov 22 12:37:17 PM PST 23 6265461576 ps
T295 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.104272147728516387262688060287352957173457639462775046663214956845255722101689 Nov 22 12:37:15 PM PST 23 Nov 22 12:37:34 PM PST 23 3151732636 ps
T296 /workspace/coverage/default/31.rom_ctrl_stress_all.94415993325717260964037069850602223228692115961969830641220794168441504419134 Nov 22 12:37:18 PM PST 23 Nov 22 12:38:05 PM PST 23 9415977006 ps
T297 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.95226558362697272235467827476186982160731593463858499243209456493094138264792 Nov 22 12:36:21 PM PST 23 Nov 22 12:36:36 PM PST 23 3151732636 ps
T298 /workspace/coverage/default/3.rom_ctrl_smoke.7163758533717880603311082826519816502022537125035792783857472773859076127538 Nov 22 12:36:42 PM PST 23 Nov 22 12:37:12 PM PST 23 6265461576 ps
T299 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.48620840863957022060413035678387702345686600604871257821441597109001355014651 Nov 22 12:37:51 PM PST 23 Nov 22 12:38:13 PM PST 23 3151732636 ps
T300 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.34725148700178298125393045479798647303917990788619949647632691340913426873331 Nov 22 12:37:44 PM PST 23 Nov 22 12:38:09 PM PST 23 3151732636 ps
T301 /workspace/coverage/default/5.rom_ctrl_smoke.31581170759867600082071491184864674436013190163361954096316087052244271013910 Nov 22 12:37:13 PM PST 23 Nov 22 12:37:49 PM PST 23 6265461576 ps
T302 /workspace/coverage/default/34.rom_ctrl_alert_test.44268967284628808321225144391094058602594364820661371504775651850063085092284 Nov 22 12:37:20 PM PST 23 Nov 22 12:37:38 PM PST 23 3124113076 ps
T303 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.80276053290056073216831924371614812831890445723203797986015492255606283642238 Nov 22 12:36:45 PM PST 23 Nov 22 12:37:00 PM PST 23 3151732636 ps
T304 /workspace/coverage/default/17.rom_ctrl_stress_all.81989473284221955290244567103328317192804991929068324108931947575178009502412 Nov 22 12:36:45 PM PST 23 Nov 22 12:37:31 PM PST 23 9415977006 ps
T305 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.74571236131261959931128577171943921598946534008454413394999675788148677740582 Nov 22 12:36:36 PM PST 23 Nov 22 12:37:04 PM PST 23 6233818126 ps
T306 /workspace/coverage/default/18.rom_ctrl_alert_test.47637417954576547143489443698219356428553679825699461731119296289330476573383 Nov 22 12:37:00 PM PST 23 Nov 22 12:37:14 PM PST 23 3124113076 ps
T307 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.61246676376174008863986718553183384224027314121759924050720846768559041750666 Nov 22 12:36:48 PM PST 23 Nov 22 12:37:03 PM PST 23 3151732636 ps
T308 /workspace/coverage/default/29.rom_ctrl_alert_test.68083120341197556481848233288349310495842638161658590875461270358338848131759 Nov 22 12:37:11 PM PST 23 Nov 22 12:37:33 PM PST 23 3124113076 ps
T309 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.96177816794832635832554544623517901168379607041240782451148276900256851796514 Nov 22 12:37:12 PM PST 23 Nov 22 12:37:46 PM PST 23 6233818126 ps
T310 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.80789192192102463868548125742653601554485327330236252013609652569746497243093 Nov 22 12:36:31 PM PST 23 Nov 22 12:36:46 PM PST 23 3151732636 ps
T311 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.83848866768243355757467721377301456989434472799291945105167262983793043379660 Nov 22 12:37:00 PM PST 23 Nov 22 12:37:16 PM PST 23 3151732636 ps
T312 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.111431908725962170748280308056107860533677057784058302605920913468917924813062 Nov 22 12:37:47 PM PST 23 Nov 22 12:38:21 PM PST 23 6233818126 ps
T313 /workspace/coverage/default/2.rom_ctrl_smoke.92669762964073432021118244903666266397609170405470462793779188643026025289851 Nov 22 12:36:21 PM PST 23 Nov 22 12:36:51 PM PST 23 6265461576 ps
T314 /workspace/coverage/default/30.rom_ctrl_alert_test.59740045422924942217036881597358520746909291587270692953431504095979327196739 Nov 22 12:37:13 PM PST 23 Nov 22 12:37:33 PM PST 23 3124113076 ps
T315 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.23250456348470665357253396295134382969899919288848268860605488623557132587118 Nov 22 12:37:01 PM PST 23 Nov 22 12:42:53 PM PST 23 69854280986 ps
T316 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.88825172159592705833376561170726708286406644439809978667686725629545093546703 Nov 22 12:36:51 PM PST 23 Nov 22 12:37:05 PM PST 23 3151732636 ps
T317 /workspace/coverage/default/20.rom_ctrl_stress_all.64921106248753009757300675080532005255451099743987885540730112043759327520628 Nov 22 12:36:45 PM PST 23 Nov 22 12:37:30 PM PST 23 9415977006 ps
T318 /workspace/coverage/default/9.rom_ctrl_stress_all.107201068344283857145871352392395333970638325854571900406985104742710773982418 Nov 22 12:37:15 PM PST 23 Nov 22 12:38:02 PM PST 23 9415977006 ps
T319 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.95693927991016561734296350492640255430382044387401148956500999914288153850606 Nov 22 12:37:20 PM PST 23 Nov 22 12:37:52 PM PST 23 6233818126 ps
T320 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.65885192075583865864686498638535463023619325889822356091915420182392178044790 Nov 22 12:37:34 PM PST 23 Nov 22 12:38:02 PM PST 23 6233818126 ps
T321 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.56538156509399240434255177841639513070158881032416399515996278236665656920489 Nov 22 12:36:49 PM PST 23 Nov 22 12:37:16 PM PST 23 6233818126 ps
T322 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.76077780997691024923951141727469544917578832983181121091943824548370175317581 Nov 22 12:37:11 PM PST 23 Nov 22 12:37:46 PM PST 23 6233818126 ps
T323 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.74265067835486406224787060237596179612969089980920690913845409155450163852669 Nov 22 12:38:11 PM PST 23 Nov 22 12:38:37 PM PST 23 6233818126 ps
T324 /workspace/coverage/default/23.rom_ctrl_smoke.43200309806922956718950575190084176404522258188301204338767674177245191902908 Nov 22 12:36:50 PM PST 23 Nov 22 12:37:20 PM PST 23 6265461576 ps
T325 /workspace/coverage/default/37.rom_ctrl_smoke.40441576675296594304084160559275951898042886958848240974632028921783355428033 Nov 22 12:37:45 PM PST 23 Nov 22 12:38:25 PM PST 23 6265461576 ps
T326 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.112933220992066968269847862669709010553137876812579870117494503085087005600178 Nov 22 12:37:05 PM PST 23 Nov 22 12:42:59 PM PST 23 69854280986 ps
T327 /workspace/coverage/default/33.rom_ctrl_stress_all.99025034813235246660870149719067705345156121920980108618539875528950223320671 Nov 22 12:37:34 PM PST 23 Nov 22 12:38:19 PM PST 23 9415977006 ps
T328 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.32500564899542377708731761166884218366178946304924270549047324195189577457149 Nov 22 12:36:27 PM PST 23 Nov 22 12:36:55 PM PST 23 6233818126 ps
T329 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.89714601607385753114981526952733655176932415520656322407064948045970806252088 Nov 22 12:36:43 PM PST 23 Nov 22 12:42:29 PM PST 23 69854280986 ps
T330 /workspace/coverage/default/42.rom_ctrl_smoke.13200090577651864415230107953407894295701715337051482009043697058376622961351 Nov 22 12:37:46 PM PST 23 Nov 22 12:38:25 PM PST 23 6265461576 ps
T331 /workspace/coverage/default/23.rom_ctrl_stress_all.49826085648835508885762671386860097595061138269544942478069525146968559948563 Nov 22 12:36:51 PM PST 23 Nov 22 12:37:36 PM PST 23 9415977006 ps
T332 /workspace/coverage/default/6.rom_ctrl_alert_test.73518909461865109135458518873503278280622171673059570618314091369764277870336 Nov 22 12:36:36 PM PST 23 Nov 22 12:36:50 PM PST 23 3124113076 ps
T333 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.60641234724147594727654301993503996532336744988820948429939130386071912656932 Nov 22 12:36:31 PM PST 23 Nov 22 12:42:17 PM PST 23 69854280986 ps
T334 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.9294637267584457162095280220994703550981314480855231398407058705614873422956 Nov 22 12:36:28 PM PST 23 Nov 22 12:36:43 PM PST 23 3151732636 ps
T335 /workspace/coverage/default/25.rom_ctrl_smoke.62363143347136234780428446283717743276474160110975179751828771930063475362282 Nov 22 12:37:01 PM PST 23 Nov 22 12:37:33 PM PST 23 6265461576 ps
T336 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.81978221736959744003665207338583822112389786138055545239300505944645903000663 Nov 22 12:37:57 PM PST 23 Nov 22 12:38:29 PM PST 23 6233818126 ps
T337 /workspace/coverage/default/7.rom_ctrl_alert_test.51865801732824588158525170865307188766378779374303332279228160736487321157334 Nov 22 12:36:30 PM PST 23 Nov 22 12:36:43 PM PST 23 3124113076 ps
T338 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.84406548240505121193886775147497986641746964387953047867462988533320363712265 Nov 22 12:37:05 PM PST 23 Nov 22 12:42:54 PM PST 23 69854280986 ps
T339 /workspace/coverage/default/4.rom_ctrl_alert_test.103476516579978225481930138387024678198282977076736816406858143657495069393821 Nov 22 12:36:30 PM PST 23 Nov 22 12:36:44 PM PST 23 3124113076 ps
T340 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.34266985515065055706689841056831888826574625741356735310547434101723127849129 Nov 22 12:38:12 PM PST 23 Nov 22 12:38:26 PM PST 23 3151732636 ps
T341 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.101027968897490315262721602092582009795387435813773701231894107804363110001732 Nov 22 12:37:59 PM PST 23 Nov 22 12:38:16 PM PST 23 3151732636 ps
T342 /workspace/coverage/default/9.rom_ctrl_alert_test.105613947983513618479449003742542295343164879092809935608040279891114134793150 Nov 22 12:36:30 PM PST 23 Nov 22 12:36:44 PM PST 23 3124113076 ps
T343 /workspace/coverage/default/43.rom_ctrl_smoke.49233852791515470171038332296546908102875742435692307750595841167940160741041 Nov 22 12:37:53 PM PST 23 Nov 22 12:38:30 PM PST 23 6265461576 ps
T344 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.23707826974918551613035651652393186080451668127387623432439443378470175267398 Nov 22 12:38:08 PM PST 23 Nov 22 12:38:35 PM PST 23 6233818126 ps
T345 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.23514643061897233234567550357489964138049315768892667250042800621079555259684 Nov 22 12:36:30 PM PST 23 Nov 22 12:42:16 PM PST 23 69854280986 ps
T346 /workspace/coverage/default/19.rom_ctrl_stress_all.87838541671328719259618223925680045513941357688885186782851249047956013322214 Nov 22 12:36:43 PM PST 23 Nov 22 12:37:29 PM PST 23 9415977006 ps
T347 /workspace/coverage/default/44.rom_ctrl_stress_all.74814633752527945151170211244475120799964145730406497316736366695251402833021 Nov 22 12:37:55 PM PST 23 Nov 22 12:38:45 PM PST 23 9415977006 ps
T348 /workspace/coverage/default/43.rom_ctrl_alert_test.66952096314777097077473015159349655388000465943868640934927699832923780469996 Nov 22 12:37:54 PM PST 23 Nov 22 12:38:15 PM PST 23 3124113076 ps
T349 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.36710128238666091055181052083168987205445313027016982077977873776475892760200 Nov 22 12:37:17 PM PST 23 Nov 22 12:37:48 PM PST 23 6233818126 ps
T350 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.34714166858616264617333633618206564783413482801172433781221385903667571670374 Nov 22 12:37:01 PM PST 23 Nov 22 12:37:29 PM PST 23 6233818126 ps
T351 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.75472557513228236178385376603994979337643692449981723966140315304913716835192 Nov 22 12:37:44 PM PST 23 Nov 22 12:38:22 PM PST 23 6233818126 ps
T352 /workspace/coverage/default/32.rom_ctrl_smoke.53001559772452202144294234445123671947217480682915955239073274182675798401057 Nov 22 12:37:20 PM PST 23 Nov 22 12:37:55 PM PST 23 6265461576 ps
T353 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.32354311527518282598757784998675759753015549174854777928187140720842921655010 Nov 22 12:36:25 PM PST 23 Nov 22 12:42:09 PM PST 23 69854280986 ps
T354 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.86675550659473755789857730985626047048209447860609373332870332413753086539172 Nov 22 12:37:02 PM PST 23 Nov 22 12:37:17 PM PST 23 3151732636 ps
T355 /workspace/coverage/default/16.rom_ctrl_alert_test.66172051169975876062737124811781243718198333274717012424866083450630960924630 Nov 22 12:36:43 PM PST 23 Nov 22 12:36:58 PM PST 23 3124113076 ps
T356 /workspace/coverage/default/10.rom_ctrl_stress_all.105909361968073073647169945102993800910991494536765130721651167636331309320017 Nov 22 12:36:33 PM PST 23 Nov 22 12:37:17 PM PST 23 9415977006 ps
T357 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.91185175187854047608379288112460647748604025647667331753681136128528983586781 Nov 22 12:37:07 PM PST 23 Nov 22 12:37:24 PM PST 23 3151732636 ps
T358 /workspace/coverage/default/21.rom_ctrl_stress_all.99713653410235411700462834307533415565093771518768568995315534797357439310360 Nov 22 12:36:51 PM PST 23 Nov 22 12:37:35 PM PST 23 9415977006 ps
T359 /workspace/coverage/default/33.rom_ctrl_smoke.89961320598777095482174465925094908763655403020444422859864551349525830466914 Nov 22 12:37:33 PM PST 23 Nov 22 12:38:03 PM PST 23 6265461576 ps
T360 /workspace/coverage/default/39.rom_ctrl_smoke.10752641101890041856419264372984122037922757439719209780539888657279735483671 Nov 22 12:37:44 PM PST 23 Nov 22 12:38:25 PM PST 23 6265461576 ps
T361 /workspace/coverage/default/45.rom_ctrl_alert_test.63067636743051487864664790121437580832296609589067995348845743992449183014701 Nov 22 12:38:53 PM PST 23 Nov 22 12:39:07 PM PST 23 3124113076 ps
T362 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.53500820802068218415823123010026623518388512551980343422880812115196750427029 Nov 22 12:37:43 PM PST 23 Nov 22 12:38:07 PM PST 23 3151732636 ps
T363 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.17407001542811218204548953109148936911087329312339143528008228781734320851852 Nov 22 12:37:12 PM PST 23 Nov 22 12:37:47 PM PST 23 6233818126 ps
T364 /workspace/coverage/default/31.rom_ctrl_alert_test.21048060311851837276843513207564115002989915439110840315036879632083885186938 Nov 22 12:37:31 PM PST 23 Nov 22 12:37:45 PM PST 23 3124113076 ps
T365 /workspace/coverage/default/26.rom_ctrl_smoke.11400309871437283435368778150452516446957539382740094868196199419869302712766 Nov 22 12:37:05 PM PST 23 Nov 22 12:37:36 PM PST 23 6265461576 ps
T366 /workspace/coverage/default/11.rom_ctrl_stress_all.110418611615797589897801327392606141029013230090628771951096557644355009904603 Nov 22 12:36:35 PM PST 23 Nov 22 12:37:21 PM PST 23 9415977006 ps
T367 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.33210321194156583399180525241345579567911357935923810188211806346683719262720 Nov 22 12:37:33 PM PST 23 Nov 22 12:43:11 PM PST 23 69854280986 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.11019507937053900407803527877409186545392838026612803833877399743221829647145 Nov 22 01:16:22 PM PST 23 Nov 22 01:16:36 PM PST 23 3124113076 ps
T369 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.83266674651402342378218867436521847319320657051191788100745846685975508686194 Nov 22 01:16:38 PM PST 23 Nov 22 01:16:51 PM PST 23 3124113076 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.107705297601054800455392318865014643167133905743839046848198425406665987304797 Nov 22 01:16:52 PM PST 23 Nov 22 01:17:14 PM PST 23 3124113076 ps
T79 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.28256642271640571096820317451233770868897119201001567147008135719731273698587 Nov 22 01:16:33 PM PST 23 Nov 22 01:21:21 PM PST 23 65914678386 ps
T72 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.10327532096444684545037655626447767452937707424038019114833192172042094083521 Nov 22 01:16:40 PM PST 23 Nov 22 01:16:58 PM PST 23 3124113076 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.47942339592060696244364276511052759015832172412209710776437311540942322299852 Nov 22 01:16:22 PM PST 23 Nov 22 01:16:36 PM PST 23 3124113076 ps
T372 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.27128775859472223453115449520878877116255471888116291750334808730378126098510 Nov 22 01:17:14 PM PST 23 Nov 22 01:17:33 PM PST 23 3135422826 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.12867369004195872438692622115054449514606127305897776407221520114370193697831 Nov 22 01:16:35 PM PST 23 Nov 22 01:16:50 PM PST 23 3124113076 ps
T374 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.71442577098983785933633471551449299520248812402127592892317580976983919257272 Nov 22 01:16:22 PM PST 23 Nov 22 01:17:46 PM PST 23 3476453456 ps
T80 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.19066605917340979166347833709180794182018451190170248379148865636696180213960 Nov 22 01:16:35 PM PST 23 Nov 22 01:21:26 PM PST 23 65914678386 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.34315984062345681384506419579967601067691704898184890778161148250762367454737 Nov 22 01:17:15 PM PST 23 Nov 22 01:17:35 PM PST 23 3142303916 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.33924537780176711128654343411076521646671023979344181348345749790734270771341 Nov 22 01:17:16 PM PST 23 Nov 22 01:22:12 PM PST 23 65914678386 ps
T73 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.8683431046399686896927709129497053864551790407566771825566348685399885092796 Nov 22 01:16:57 PM PST 23 Nov 22 01:17:24 PM PST 23 3124113076 ps
T82 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.68153338065568210175335845403320242003484153674170641820873771208087089588640 Nov 22 01:16:51 PM PST 23 Nov 22 01:21:46 PM PST 23 65914678386 ps
T99 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.44698211041226657848801778652997399888385614382187410881618548189803398012639 Nov 22 01:16:40 PM PST 23 Nov 22 01:16:53 PM PST 23 3124113076 ps
T376 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.68048353530373573660999772285757044799150998817576491323042243358387257051378 Nov 22 01:16:41 PM PST 23 Nov 22 01:16:55 PM PST 23 3135422826 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.72830456161481082306120592354110621749136485430628316909136793080084294984378 Nov 22 01:16:52 PM PST 23 Nov 22 01:17:18 PM PST 23 3135422826 ps
T378 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.69818809117588057320698179106925490117046513428291306584062945197536881917525 Nov 22 01:16:40 PM PST 23 Nov 22 01:16:55 PM PST 23 3142303916 ps
T379 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.67848433672146786595536951833434240050108855134461909992770163588074647342963 Nov 22 01:16:48 PM PST 23 Nov 22 01:17:04 PM PST 23 3124113076 ps
T380 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.53415341925922699125826911677240902968293804528735425097563085237273759199073 Nov 22 01:16:36 PM PST 23 Nov 22 01:16:51 PM PST 23 3135422826 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.110048203537217434373340288989779999599489733189753594625598995596284346045891 Nov 22 01:16:31 PM PST 23 Nov 22 01:16:44 PM PST 23 3124113076 ps
T381 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.95866726053368773269427136949850879382068902833768675405688297487939924060208 Nov 22 01:16:34 PM PST 23 Nov 22 01:16:50 PM PST 23 3142303916 ps
T382 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.36876960831422377756144532703807213913017538883956432230450195987078914717922 Nov 22 01:17:04 PM PST 23 Nov 22 01:17:31 PM PST 23 3124113076 ps
T383 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.18606912674795185591713759176861996245700831590091883321306964825930992338269 Nov 22 01:16:57 PM PST 23 Nov 22 01:17:21 PM PST 23 3135422826 ps
T384 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.100886731202495562579471271931505200461502804700415282724643074457257554528201 Nov 22 01:16:44 PM PST 23 Nov 22 01:18:06 PM PST 23 3476453456 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.93821958677239403755250391592231589641651487360106724322816652439937720731160 Nov 22 01:16:30 PM PST 23 Nov 22 01:16:47 PM PST 23 3124113076 ps
T386 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.12809733949189516041280916617378668385897425246565994641208072651677870233967 Nov 22 01:16:51 PM PST 23 Nov 22 01:17:16 PM PST 23 3142303916 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.51529702863509658706422238463393988970788162512143542214399464973716200744326 Nov 22 01:16:24 PM PST 23 Nov 22 01:21:21 PM PST 23 65914678386 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.54999077556080173088973154041204672678534779992518922848638855554963734497062 Nov 22 01:16:34 PM PST 23 Nov 22 01:16:48 PM PST 23 3124113076 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.80331997401337559734824460074915843101220181956691639980342380042988046450799 Nov 22 01:16:39 PM PST 23 Nov 22 01:16:56 PM PST 23 3138518126 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.20544158488271338673919351084866472424017406471511694503616411115754532727824 Nov 22 01:16:31 PM PST 23 Nov 22 01:16:46 PM PST 23 3142303916 ps
T390 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.97675466595572681518641829507556102112375493390503702211483067176507601487083 Nov 22 01:16:33 PM PST 23 Nov 22 01:17:55 PM PST 23 3476453456 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.75412446458880979368144184731348898410330297460211226652004870565590603896977 Nov 22 01:16:02 PM PST 23 Nov 22 01:16:17 PM PST 23 3124113076 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.69339694854844616691273814280545525874057572570579063987707724065549837546897 Nov 22 01:16:40 PM PST 23 Nov 22 01:16:58 PM PST 23 3124113076 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.21796929983919137497493748823502686512255091127097184128264036753588670161551 Nov 22 01:16:33 PM PST 23 Nov 22 01:21:18 PM PST 23 65914678386 ps
T393 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.34868166079609920032932472204597996391340538151321069670605182650337675834660 Nov 22 01:16:40 PM PST 23 Nov 22 01:16:53 PM PST 23 3124113076 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.93784128329267269455415193817458564292905149517230153735094171601978506798586 Nov 22 01:16:36 PM PST 23 Nov 22 01:16:51 PM PST 23 3124113076 ps
T395 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.14433779736090049812206681940360742216254835012722718876739922782750235897941 Nov 22 01:16:52 PM PST 23 Nov 22 01:17:17 PM PST 23 3142303916 ps
T396 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.94442576501082018230198019576522093743348348630125042718154159772078047773818 Nov 22 01:18:44 PM PST 23 Nov 22 01:23:25 PM PST 23 65914678386 ps
T397 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.74049188654147899657587941679348926023238212852835191651426697782764573038081 Nov 22 01:17:07 PM PST 23 Nov 22 01:18:37 PM PST 23 3476453456 ps
T398 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.15281829754793200911418473043803071189451454258031350149018987214487649843926 Nov 22 01:16:52 PM PST 23 Nov 22 01:18:24 PM PST 23 3476453456 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.66274486722898824886402617620057113608765689313139130265729158461451000128179 Nov 22 01:16:43 PM PST 23 Nov 22 01:16:57 PM PST 23 3124113076 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.99341301892701861510081226853800542031408525779065911126757611734369963640334 Nov 22 01:16:33 PM PST 23 Nov 22 01:16:46 PM PST 23 3124113076 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.64934802183047915468002400583045605838170549904211024426236810102050983789132 Nov 22 01:16:41 PM PST 23 Nov 22 01:18:04 PM PST 23 3476453456 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.17659650369679608579431863515311048185730410935674029031180402871897990888747 Nov 22 01:16:41 PM PST 23 Nov 22 01:16:55 PM PST 23 3135422826 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.50789990591859236065250142464228034787755688949849808629038997873629876091741 Nov 22 01:16:35 PM PST 23 Nov 22 01:16:50 PM PST 23 3124113076 ps
T403 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.13979031468411747887081320858356750570042344917170671110923557556129592367507 Nov 22 01:16:29 PM PST 23 Nov 22 01:16:46 PM PST 23 3124113076 ps
T404 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.111773261123757571877565713673574629434058072978081141185007747540358959952591 Nov 22 01:16:32 PM PST 23 Nov 22 01:16:45 PM PST 23 3124113076 ps
T405 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.108038666882905088748265814509800597519136408803141639690825476646888740762103 Nov 22 01:16:36 PM PST 23 Nov 22 01:16:51 PM PST 23 3124113076 ps
T406 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.92085318965964085737092996475473138633428704146855152373862892935140805694539 Nov 22 01:16:41 PM PST 23 Nov 22 01:16:57 PM PST 23 3142303916 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.16623821595848495659587614325316522197084678964271308098972871088792049433907 Nov 22 01:16:20 PM PST 23 Nov 22 01:16:36 PM PST 23 3142303916 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.93204130212852234120304383608608812099519337600227974811319231040668036366093 Nov 22 01:16:33 PM PST 23 Nov 22 01:16:47 PM PST 23 3124113076 ps
T409 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.5820907030799179230843325079600903223161219206032975073101559448093202789102 Nov 22 01:16:23 PM PST 23 Nov 22 01:21:08 PM PST 23 65914678386 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.87208039674802530998085313838213320832409808701356981829123185526327321388081 Nov 22 01:16:21 PM PST 23 Nov 22 01:16:35 PM PST 23 3124113076 ps
T411 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.12766551631937081308787056052278365921426172530881846446558875664068549387652 Nov 22 01:16:41 PM PST 23 Nov 22 01:16:55 PM PST 23 3124113076 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.42448907138159787257534314271481090260892880985664307054502019500760953556602 Nov 22 01:16:35 PM PST 23 Nov 22 01:16:50 PM PST 23 3124113076 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.6910971923859173493507411984143388912841454385434120685720542273108607238879 Nov 22 01:16:14 PM PST 23 Nov 22 01:21:03 PM PST 23 65914678386 ps
T414 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.44899451860257935458583760621913851986503222023938483051534088172622975571122 Nov 22 01:16:57 PM PST 23 Nov 22 01:21:50 PM PST 23 65914678386 ps
T415 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.104444140448835766065977174864937482639868351939745795059774071432862149081750 Nov 22 01:16:20 PM PST 23 Nov 22 01:16:35 PM PST 23 3124113076 ps
T416 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.21899187105614614160806412576297859249973340358323862348812107508913486504595 Nov 22 01:16:50 PM PST 23 Nov 22 01:18:22 PM PST 23 3476453456 ps
T417 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.12148778616382276165277846906285526996503166073447829068723830783817389228238 Nov 22 01:16:52 PM PST 23 Nov 22 01:21:52 PM PST 23 65914678386 ps
T418 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.106652953245887609505657329869209805887576327723563418951382782098747136844749 Nov 22 01:16:36 PM PST 23 Nov 22 01:16:52 PM PST 23 3142303916 ps
T419 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.103117900458160212525616679778495050187993042652066441099675558993859443071590 Nov 22 01:16:51 PM PST 23 Nov 22 01:18:24 PM PST 23 3476453456 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.89292172854871341620681164444409874449750164899579333770330283106319825403363 Nov 22 01:16:22 PM PST 23 Nov 22 01:16:37 PM PST 23 3124113076 ps
T421 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.7186167349956085521654323081287322444287019778813075734167969920811831983855 Nov 22 01:16:52 PM PST 23 Nov 22 01:17:15 PM PST 23 3124113076 ps
T422 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.48019859174666839955835849033326388097133404747012149320184820940910912770663 Nov 22 01:16:41 PM PST 23 Nov 22 01:21:31 PM PST 23 65914678386 ps
T102 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.68400461538825752297104515393744470453235755058603922025310825193551929138100 Nov 22 01:16:52 PM PST 23 Nov 22 01:17:18 PM PST 23 3124113076 ps
T423 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.71473590178091361398335676226277226049663128362494338918777602817212562731776 Nov 22 01:18:06 PM PST 23 Nov 22 01:22:57 PM PST 23 65914678386 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.101959381853742641267656868366396949723388887356876489216506419375800692873411 Nov 22 01:16:52 PM PST 23 Nov 22 01:17:22 PM PST 23 3124113076 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2756152705863407079415958262201128966479600227252787538627068451210282298399 Nov 22 01:16:23 PM PST 23 Nov 22 01:17:47 PM PST 23 3476453456 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.46475917767450060853469754173484503033340134837654618462418096919477519342526 Nov 22 01:16:22 PM PST 23 Nov 22 01:16:41 PM PST 23 3124113076 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.99125659024528250687160450776743379835629713622566354015765037646096927527538 Nov 22 01:16:01 PM PST 23 Nov 22 01:16:20 PM PST 23 3124113076 ps
T428 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.95866855303263275040696026772753920745906396095280546939680655861590161198797 Nov 22 01:16:33 PM PST 23 Nov 22 01:17:56 PM PST 23 3476453456 ps
T429 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.64704147546226526816069367971339294204577639351706680801119631721613268249372 Nov 22 01:16:44 PM PST 23 Nov 22 01:17:02 PM PST 23 3124113076 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.44522729048905710321620898211921153647814982302716810179602963423148472019327 Nov 22 01:16:34 PM PST 23 Nov 22 01:16:48 PM PST 23 3135422826 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.49495243886101834234589869962712570962416718806202690703528400561996565349836 Nov 22 01:16:30 PM PST 23 Nov 22 01:16:47 PM PST 23 3138518126 ps
T432 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.52643767110874318109225296235854595468019108371636321719645238346993915911083 Nov 22 01:18:06 PM PST 23 Nov 22 01:19:33 PM PST 23 3476453456 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.98044479283747337825161620768093789950056639323885589112423004436302537289837 Nov 22 01:16:22 PM PST 23 Nov 22 01:16:37 PM PST 23 3135422826 ps
T434 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.46313078040012401536486809770703403458680910368045688046308160320432270105916 Nov 22 01:17:05 PM PST 23 Nov 22 01:17:27 PM PST 23 3135422826 ps
T435 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.82090293524203433699600741774402169248766336607560683847831814657481556388044 Nov 22 01:16:39 PM PST 23 Nov 22 01:16:57 PM PST 23 3124113076 ps
T436 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.44190587225187551748784158380155533342920630938675457020361803475553912358657 Nov 22 01:17:26 PM PST 23 Nov 22 01:18:51 PM PST 23 3476453456 ps
T437 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.41252142193171439348681659782455441541851043790295718536108560851746413516893 Nov 22 01:16:38 PM PST 23 Nov 22 01:21:29 PM PST 23 65914678386 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.45247568530545904376290382592567471324696233579485999473588123697115951643857 Nov 22 01:16:21 PM PST 23 Nov 22 01:16:35 PM PST 23 3124113076 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.58558596692367990318048078659742694124571884924780951263342507437801736960327 Nov 22 01:16:51 PM PST 23 Nov 22 01:17:13 PM PST 23 3124113076 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.13354778713238292610047992456687137173720755894134499926875339696965192985665 Nov 22 01:17:04 PM PST 23 Nov 22 01:17:27 PM PST 23 3135422826 ps
T441 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.88997152190635794597935654954609044262946179341312392335157523756117377988853 Nov 22 01:16:34 PM PST 23 Nov 22 01:21:22 PM PST 23 65914678386 ps
T442 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.55676318714588710770195246367129070987838525482702919149969817869707753516206 Nov 22 01:16:28 PM PST 23 Nov 22 01:16:41 PM PST 23 3135422826 ps
T443 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.87024559585171171165198582461826134067490964493891947726791982182167825040334 Nov 22 01:16:52 PM PST 23 Nov 22 01:17:18 PM PST 23 3135422826 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.43894356393054556844757207275603301932602313724984747668839561700313066811606 Nov 22 01:16:30 PM PST 23 Nov 22 01:16:44 PM PST 23 3124113076 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.84542936432556982719559247668360753235318617466862560607879598031540601974502 Nov 22 01:16:14 PM PST 23 Nov 22 01:21:04 PM PST 23 65914678386 ps
T446 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.65648548209216802136529673123264741356815472026736951087183184758822841081280 Nov 22 01:16:35 PM PST 23 Nov 22 01:16:54 PM PST 23 3124113076 ps
T447 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.86359709500921872096673701138287137910775972568320150068326166011169791252773 Nov 22 01:16:50 PM PST 23 Nov 22 01:18:22 PM PST 23 3476453456 ps
T448 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.14656351519860668328038124425199532148029519802932515323505910321922538682250 Nov 22 01:16:49 PM PST 23 Nov 22 01:17:05 PM PST 23 3124113076 ps
T449 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.70469340958323740109989006856098249612832047062809685206381457388014178242063 Nov 22 01:16:52 PM PST 23 Nov 22 01:17:17 PM PST 23 3142303916 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.46045421426324362383862166293215849167957696042136094656130806718381080575817 Nov 22 01:16:35 PM PST 23 Nov 22 01:16:53 PM PST 23 3138518126 ps

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.66825642944338562959632160049305960489674501391453488850924975959472173849478
Short name T17
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.98 seconds
Started Nov 22 01:16:25 PM PST 23
Finished Nov 22 01:16:43 PM PST 23
Peak memory 218904 kb
Host smart-3200d757-24bf-48f7-9def-b4da300b3c44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66825642944338562959632160049305960489674501391453488850924975959472173849478 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.66825642944338562959632160049305960489674501391453488850924975959472173849478
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.83515681368243122924604606957219894318092645213116177488072802994590121039514
Short name T4
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.16 seconds
Started Nov 22 12:37:00 PM PST 23
Finished Nov 22 12:42:43 PM PST 23
Peak memory 237612 kb
Host smart-f2eaddcc-99e4-42c3-83ee-5a2b61c35484
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83515681368243122924604606957219894318092645213116177488072802994590121039514 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.835156813682431229246046069572198943180926452131161774880
72802994590121039514
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.79162457807686601420671823406277533009397342766545833496226265567331317150782
Short name T19
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.11 seconds
Started Nov 22 01:16:20 PM PST 23
Finished Nov 22 01:17:43 PM PST 23
Peak memory 210916 kb
Host smart-b214ec15-9db1-440c-96d6-fe80c1360e75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79162457807686601420671823406277533009397342766545833496226265567331317150782 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.79162457807686601420671823406277533009397342766545833496226265567331317150782
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.109980611154598554827375596905048750511700874720502525818216935542887098713164
Short name T5
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.24 seconds
Started Nov 22 12:36:22 PM PST 23
Finished Nov 22 12:37:06 PM PST 23
Peak memory 212872 kb
Host smart-dffa3947-4f30-43ae-a447-e2a730709ce4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109980611154598554827375596905048750511700874720502525818216935
542887098713164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.10998061115459855482737559690504875051170087472050
2525818216935542887098713164
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.38204840714053160825143726740582651240760928018719017852388339725088805938911
Short name T30
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.49 seconds
Started Nov 22 01:16:21 PM PST 23
Finished Nov 22 01:21:11 PM PST 23
Peak memory 218964 kb
Host smart-50231b96-c786-4d6d-96e1-f6e504511346
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38204840714053160825143726740582651240760928018719017852388339725088805938911 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.38204840714053160825143726740582651240760928018719017852
388339725088805938911
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.110048203537217434373340288989779999599489733189753594625598995596284346045891
Short name T100
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.64 seconds
Started Nov 22 01:16:31 PM PST 23
Finished Nov 22 01:16:44 PM PST 23
Peak memory 210832 kb
Host smart-14ef4840-4b2c-4845-be75-914f2d0731e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110048203537217434373340288989779999599489733189753594625598995596284346045891 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.110048203537217434373340288989779999599489733189753594625598995596284346045891
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.110566562421150087143550075703164760957197302843106422454717697648260826531875
Short name T29
Test name
Test status
Simulation time 3444857586 ps
CPU time 117.56 seconds
Started Nov 22 12:36:21 PM PST 23
Finished Nov 22 12:38:20 PM PST 23
Peak memory 236680 kb
Host smart-8e1909b1-2ecd-4e7d-9582-998eeebf6857
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110566562421150087143550075703164760957197302843106422454717697648260826531875 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.110566562421150087143550075703164760957197302843106422454717697648260826531875
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.79723951045754379791189227972853671438099570737308274750015510445287897333393
Short name T20
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.22 seconds
Started Nov 22 01:16:33 PM PST 23
Finished Nov 22 01:16:49 PM PST 23
Peak memory 210804 kb
Host smart-b5fc42a5-1e0e-497c-884b-bb9a9019cf27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79723951045754379791189227972853671438099570737308274750015510445287897333393
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.797239510457543797911892279728536714380995707373082747
50015510445287897333393
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.113447823491467957247012442154457273078725859024654221380938318478330089142778
Short name T53
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.37 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:18 PM PST 23
Peak memory 213416 kb
Host smart-7767faba-f072-4325-9b86-3cf9387297d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134478234914679572470124421544572730787258
59024654221380938318478330089142778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.11344782349
1467957247012442154457273078725859024654221380938318478330089142778
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.43894356393054556844757207275603301932602313724984747668839561700313066811606
Short name T444
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Nov 22 01:16:30 PM PST 23
Finished Nov 22 01:16:44 PM PST 23
Peak memory 210832 kb
Host smart-eae82afc-c95f-4a94-9680-d9ab297730d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43894356393054556844757207275603301932602313724984747668839561700313066811606 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.43894356393054556844757207275603301932602313724984747668839561700313066811606
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1183610256180022553958688306643790420445602399804760689893334520611748107012
Short name T126
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.03 seconds
Started Nov 22 12:36:37 PM PST 23
Finished Nov 22 12:37:04 PM PST 23
Peak memory 211516 kb
Host smart-817b1846-e9c4-4dc4-9b85-6d3a02dfcdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183610256180022553958688306643790420445602399804760689893334520611748107012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.rom_ctrl_kmac_err_chk.1183610256180022553958688306643790420445602399804760689893334520611748107012
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.44878989681240030393485530134818721105938430183431940781172498007597024253875
Short name T136
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.96 seconds
Started Nov 22 12:36:38 PM PST 23
Finished Nov 22 12:36:53 PM PST 23
Peak memory 211108 kb
Host smart-94748383-a9ff-4fb3-88dc-611b409e28bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44878989681240030393485530134818721105938430183431940781172498007597024253875 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.44878989681240030393485530134818721105938430183431940781172498007597024253875
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.38952686055761227698399218248209112701390139736228484949467527088843974699853
Short name T119
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.99 seconds
Started Nov 22 12:36:34 PM PST 23
Finished Nov 22 12:36:48 PM PST 23
Peak memory 211060 kb
Host smart-3cf1c457-7601-44c7-ac28-7c3ea72a88dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38952686055761227698399218248209112701390139736228484949467527088843974699853 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.38952686055761227698399218248209112701390139736228484949467527088843974699853
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.47942339592060696244364276511052759015832172412209710776437311540942322299852
Short name T371
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.09 seconds
Started Nov 22 01:16:22 PM PST 23
Finished Nov 22 01:16:36 PM PST 23
Peak memory 210820 kb
Host smart-19fd57ea-ca9b-49bf-bcae-e9ebb58e4f00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47942339592060696244364276511052759015832172412209710776437311540942322299852 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.47942339592060696244364276511052759015832172412209710776437311540942322299852
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.110146970250612886773319981555578911370840676513991007214403238860078645451137
Short name T112
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.92 seconds
Started Nov 22 12:36:26 PM PST 23
Finished Nov 22 12:36:56 PM PST 23
Peak memory 212748 kb
Host smart-0339b93f-0aa5-4ad2-9f5a-c99801a2ce11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110146970250612886773319981555578911370840676513991007214403238860078645451137 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.rom_ctrl_smoke.110146970250612886773319981555578911370840676513991007214403238860078645451137
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.104444140448835766065977174864937482639868351939745795059774071432862149081750
Short name T415
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.7 seconds
Started Nov 22 01:16:20 PM PST 23
Finished Nov 22 01:16:35 PM PST 23
Peak memory 210720 kb
Host smart-e2241bfe-6621-4399-b8d7-63e3b4028317
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104444140448835766065977174864937482639868351939745795059774071432862149081750 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.104444140448835766065977174864937482639868351939745795059774071432862149081750
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.70509517316244721794254919544442260302025789228164686017390096072533115696500
Short name T77
Test name
Test status
Simulation time 3138518126 ps
CPU time 16 seconds
Started Nov 22 01:16:21 PM PST 23
Finished Nov 22 01:16:39 PM PST 23
Peak memory 210784 kb
Host smart-0dd12107-e932-4c52-bc21-583c5c827013
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70509517316244721794254919544442260302025789228164686017390096072533115696500 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.70509517316244721794254919544442260302025789228164686017390096072533115696500
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.98044479283747337825161620768093789950056639323885589112423004436302537289837
Short name T433
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.48 seconds
Started Nov 22 01:16:22 PM PST 23
Finished Nov 22 01:16:37 PM PST 23
Peak memory 213372 kb
Host smart-18a5bbc3-0e39-400b-b643-59179d789d7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9804447928374733782516162076809378995005663
9323885589112423004436302537289837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.9804447928374
7337825161620768093789950056639323885589112423004436302537289837
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.75412446458880979368144184731348898410330297460211226652004870565590603896977
Short name T391
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.33 seconds
Started Nov 22 01:16:02 PM PST 23
Finished Nov 22 01:16:17 PM PST 23
Peak memory 210736 kb
Host smart-e7509f1c-fe0b-40f2-bdd8-3dfbc1c56b8a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75412446458880979368144184731348898410330297460211226652004870565590603896977 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.7541244645888097936814418473134889841033029746021122665200
4870565590603896977
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.11019507937053900407803527877409186545392838026612803833877399743221829647145
Short name T368
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.04 seconds
Started Nov 22 01:16:22 PM PST 23
Finished Nov 22 01:16:36 PM PST 23
Peak memory 210756 kb
Host smart-d78d9b88-4b4f-4b24-b3a9-1ea5e28ba629
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11019507937053900407803527877409186545392838026612803833877399743221829647145 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.11019507937053900407803527877409186545392838026612803833877399743221829647145
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.6910971923859173493507411984143388912841454385434120685720542273108607238879
Short name T413
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.19 seconds
Started Nov 22 01:16:14 PM PST 23
Finished Nov 22 01:21:03 PM PST 23
Peak memory 218816 kb
Host smart-ead3738f-4f22-4382-825d-fc4fdf20e1c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6910971923859173493507411984143388912841454385434120685720542273108607238879 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.691097192385917349350741198414338891284145438543412068572
0542273108607238879
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.16623821595848495659587614325316522197084678964271308098972871088792049433907
Short name T407
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.11 seconds
Started Nov 22 01:16:20 PM PST 23
Finished Nov 22 01:16:36 PM PST 23
Peak memory 210700 kb
Host smart-52f812a8-c94e-4771-8538-696832da37e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16623821595848495659587614325316522197084678964271308098972871088792049433907
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.166238215958484956595876143253165221970846789642713080
98972871088792049433907
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.99125659024528250687160450776743379835629713622566354015765037646096927527538
Short name T427
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.56 seconds
Started Nov 22 01:16:01 PM PST 23
Finished Nov 22 01:16:20 PM PST 23
Peak memory 219000 kb
Host smart-0929b5a5-b5a9-4b4e-8003-560268c00f52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99125659024528250687160450776743379835629713622566354015765037646096927527538 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.99125659024528250687160450776743379835629713622566354015765037646096927527538
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.15829837423776011815378181284824838886289896947288113850380469221093043355672
Short name T56
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.28 seconds
Started Nov 22 01:16:21 PM PST 23
Finished Nov 22 01:17:44 PM PST 23
Peak memory 211040 kb
Host smart-e1e94064-5c7d-48c0-bed7-e05ee68817f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15829837423776011815378181284824838886289896947288113850380469221093043355672 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.15829837423776011815378181284824838886289896947288113850380469221093043355672
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.45247568530545904376290382592567471324696233579485999473588123697115951643857
Short name T438
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.29 seconds
Started Nov 22 01:16:21 PM PST 23
Finished Nov 22 01:16:35 PM PST 23
Peak memory 210680 kb
Host smart-709043b3-e9b0-4f37-9bbf-12691adad187
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45247568530545904376290382592567471324696233579485999473588123697115951643857 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.45247568530545904376290382592567471324696233579485999473588123697115951643857
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.46045421426324362383862166293215849167957696042136094656130806718381080575817
Short name T450
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.45 seconds
Started Nov 22 01:16:35 PM PST 23
Finished Nov 22 01:16:53 PM PST 23
Peak memory 210800 kb
Host smart-bb649b3a-9193-47e8-8639-b6a8b2581259
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46045421426324362383862166293215849167957696042136094656130806718381080575817 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.46045421426324362383862166293215849167957696042136094656130806718381080575817
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.44522729048905710321620898211921153647814982302716810179602963423148472019327
Short name T430
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.15 seconds
Started Nov 22 01:16:34 PM PST 23
Finished Nov 22 01:16:48 PM PST 23
Peak memory 213436 kb
Host smart-8db8ff38-5000-407a-9b34-cf8753a23002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4452272904890571032162089821192115364781498
2302716810179602963423148472019327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4452272904890
5710321620898211921153647814982302716810179602963423148472019327
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4605812135479479241729602182136862931113098802354983460642776670208832337702
Short name T76
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.21 seconds
Started Nov 22 01:16:34 PM PST 23
Finished Nov 22 01:16:49 PM PST 23
Peak memory 210788 kb
Host smart-3f846141-13d0-415e-9cb1-e62d91b09778
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4605812135479479241729602182136862931113098802354983460642776670208832337702 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4605812135479479241729602182136862931113098802354983460642776670208832337702
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.50789990591859236065250142464228034787755688949849808629038997873629876091741
Short name T402
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.37 seconds
Started Nov 22 01:16:35 PM PST 23
Finished Nov 22 01:16:50 PM PST 23
Peak memory 210800 kb
Host smart-ad1a8acf-11be-4774-b7dd-2cb3fe943cdb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50789990591859236065250142464228034787755688949849808629038997873629876091741 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.5078999059185923606525014246422803478775568894984980862903
8997873629876091741
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.58558596692367990318048078659742694124571884924780951263342507437801736960327
Short name T439
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Nov 22 01:16:51 PM PST 23
Finished Nov 22 01:17:13 PM PST 23
Peak memory 210636 kb
Host smart-15f085ce-0599-4786-80f5-66c59c54c731
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58558596692367990318048078659742694124571884924780951263342507437801736960327 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.58558596692367990318048078659742694124571884924780951263342507437801736960327
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.84542936432556982719559247668360753235318617466862560607879598031540601974502
Short name T445
Test name
Test status
Simulation time 65914678386 ps
CPU time 288.7 seconds
Started Nov 22 01:16:14 PM PST 23
Finished Nov 22 01:21:04 PM PST 23
Peak memory 218924 kb
Host smart-22ddcf29-c9b2-4d1e-964b-8833047d374d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84542936432556982719559247668360753235318617466862560607879598031540601974502 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.84542936432556982719559247668360753235318617466862560607
879598031540601974502
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.21766259387846424859562630395451473449474980984996974235893305275243641410874
Short name T70
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.04 seconds
Started Nov 22 01:16:22 PM PST 23
Finished Nov 22 01:16:41 PM PST 23
Peak memory 218924 kb
Host smart-e82e812b-098a-4a26-97da-0a96d1a25a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21766259387846424859562630395451473449474980984996974235893305275243641410874 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.21766259387846424859562630395451473449474980984996974235893305275243641410874
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.13354778713238292610047992456687137173720755894134499926875339696965192985665
Short name T440
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.52 seconds
Started Nov 22 01:17:04 PM PST 23
Finished Nov 22 01:17:27 PM PST 23
Peak memory 213440 kb
Host smart-b7f84008-e62c-45f1-86bc-d7890578ed0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335477871323829261004799245668713717372075
5894134499926875339696965192985665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.133547787132
38292610047992456687137173720755894134499926875339696965192985665
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.111773261123757571877565713673574629434058072978081141185007747540358959952591
Short name T404
Test name
Test status
Simulation time 3124113076 ps
CPU time 12 seconds
Started Nov 22 01:16:32 PM PST 23
Finished Nov 22 01:16:45 PM PST 23
Peak memory 210824 kb
Host smart-23f84e0b-f156-4501-a8f8-be0dfb4b9e4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111773261123757571877565713673574629434058072978081141185007747540358959952591 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.111773261123757571877565713673574629434058072978081141185007747540358959952591
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.88997152190635794597935654954609044262946179341312392335157523756117377988853
Short name T441
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.68 seconds
Started Nov 22 01:16:34 PM PST 23
Finished Nov 22 01:21:22 PM PST 23
Peak memory 218956 kb
Host smart-373b3760-4d62-4e91-8004-dc882b87e4bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88997152190635794597935654954609044262946179341312392335157523756117377988853 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.8899715219063579459793565495460904426294617934131239233
5157523756117377988853
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.67823275093913450967430472991437756704075797785398065296700684847992747461800
Short name T86
Test name
Test status
Simulation time 3142303916 ps
CPU time 14 seconds
Started Nov 22 01:16:30 PM PST 23
Finished Nov 22 01:16:45 PM PST 23
Peak memory 210816 kb
Host smart-61c08c93-6161-4a38-b784-710b415d1033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67823275093913450967430472991437756704075797785398065296700684847992747461800
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.67823275093913450967430472991437756704075797785398065
296700684847992747461800
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.99613025501318514655143219124114542554496854727151876956922451624886386853125
Short name T55
Test name
Test status
Simulation time 3124113076 ps
CPU time 17.12 seconds
Started Nov 22 01:17:02 PM PST 23
Finished Nov 22 01:17:30 PM PST 23
Peak memory 218992 kb
Host smart-1735f78f-aa35-4424-8002-27984292d9c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99613025501318514655143219124114542554496854727151876956922451624886386853125 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.99613025501318514655143219124114542554496854727151876956922451624886386853125
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.97675466595572681518641829507556102112375493390503702211483067176507601487083
Short name T390
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.72 seconds
Started Nov 22 01:16:33 PM PST 23
Finished Nov 22 01:17:55 PM PST 23
Peak memory 211056 kb
Host smart-484be3c1-b295-4ddd-a76e-3962ecc61915
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97675466595572681518641829507556102112375493390503702211483067176507601487083 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.97675466595572681518641829507556102112375493390503702211483067176507601487083
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.55676318714588710770195246367129070987838525482702919149969817869707753516206
Short name T442
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.18 seconds
Started Nov 22 01:16:28 PM PST 23
Finished Nov 22 01:16:41 PM PST 23
Peak memory 213432 kb
Host smart-3d358144-ac5b-417e-a9a2-0f46054c67a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5567631871458871077019524636712907098783852
5482702919149969817869707753516206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.556763187145
88710770195246367129070987838525482702919149969817869707753516206
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.12766551631937081308787056052278365921426172530881846446558875664068549387652
Short name T411
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.58 seconds
Started Nov 22 01:16:41 PM PST 23
Finished Nov 22 01:16:55 PM PST 23
Peak memory 210364 kb
Host smart-11b66deb-1fab-45cf-81b1-accb8955fcda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12766551631937081308787056052278365921426172530881846446558875664068549387652 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.12766551631937081308787056052278365921426172530881846446558875664068549387652
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.41252142193171439348681659782455441541851043790295718536108560851746413516893
Short name T437
Test name
Test status
Simulation time 65914678386 ps
CPU time 289.35 seconds
Started Nov 22 01:16:38 PM PST 23
Finished Nov 22 01:21:29 PM PST 23
Peak memory 219012 kb
Host smart-59763acc-a3c3-49a3-9dba-a8bdca518fcc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41252142193171439348681659782455441541851043790295718536108560851746413516893 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.4125214219317143934868165978245544154185104379029571853
6108560851746413516893
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.70661817691462320015460603065288610345444949839283155439634678201348733339118
Short name T85
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.13 seconds
Started Nov 22 01:16:29 PM PST 23
Finished Nov 22 01:16:44 PM PST 23
Peak memory 210816 kb
Host smart-49c05bb9-3e77-4a7c-98d2-669e9b8b09de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70661817691462320015460603065288610345444949839283155439634678201348733339118
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.70661817691462320015460603065288610345444949839283155
439634678201348733339118
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.13979031468411747887081320858356750570042344917170671110923557556129592367507
Short name T403
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.84 seconds
Started Nov 22 01:16:29 PM PST 23
Finished Nov 22 01:16:46 PM PST 23
Peak memory 218992 kb
Host smart-ed651879-72fe-4a69-81bb-5f14ba28f91e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13979031468411747887081320858356750570042344917170671110923557556129592367507 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.13979031468411747887081320858356750570042344917170671110923557556129592367507
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1547466446936790334481875176134250462387602490380084753993918112483853382429
Short name T105
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.93 seconds
Started Nov 22 01:16:58 PM PST 23
Finished Nov 22 01:18:30 PM PST 23
Peak memory 211000 kb
Host smart-c4adb30d-7cfb-4eae-aa0c-bff19d243f13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547466446936790334481875176134250462387602490380084753993918112483853382429 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.1547466446936790334481875176134250462387602490380084753993918112483853382429
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.17659650369679608579431863515311048185730410935674029031180402871897990888747
Short name T401
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.57 seconds
Started Nov 22 01:16:41 PM PST 23
Finished Nov 22 01:16:55 PM PST 23
Peak memory 213136 kb
Host smart-29d84350-6c22-4a4a-96f9-d6535f35076d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765965036967960857943186351531104818573041
0935674029031180402871897990888747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.176596503696
79608579431863515311048185730410935674029031180402871897990888747
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.83266674651402342378218867436521847319320657051191788100745846685975508686194
Short name T369
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.21 seconds
Started Nov 22 01:16:38 PM PST 23
Finished Nov 22 01:16:51 PM PST 23
Peak memory 210828 kb
Host smart-b9ac4c11-e7a4-4c26-886f-9121f30315f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83266674651402342378218867436521847319320657051191788100745846685975508686194 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.83266674651402342378218867436521847319320657051191788100745846685975508686194
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.12148778616382276165277846906285526996503166073447829068723830783817389228238
Short name T417
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.49 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:21:52 PM PST 23
Peak memory 218952 kb
Host smart-7107e21a-938e-4e47-b0e9-d03c62559951
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12148778616382276165277846906285526996503166073447829068723830783817389228238 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.1214877861638227616527784690628552699650316607344782906
8723830783817389228238
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.95866726053368773269427136949850879382068902833768675405688297487939924060208
Short name T381
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.94 seconds
Started Nov 22 01:16:34 PM PST 23
Finished Nov 22 01:16:50 PM PST 23
Peak memory 210808 kb
Host smart-9cf37bed-68c7-4c17-b477-e3467d0bcd0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95866726053368773269427136949850879382068902833768675405688297487939924060208
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.95866726053368773269427136949850879382068902833768675
405688297487939924060208
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.10327532096444684545037655626447767452937707424038019114833192172042094083521
Short name T72
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.53 seconds
Started Nov 22 01:16:40 PM PST 23
Finished Nov 22 01:16:58 PM PST 23
Peak memory 218904 kb
Host smart-a9ebeda5-eb69-41bc-83cc-2225d52b54fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10327532096444684545037655626447767452937707424038019114833192172042094083521 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.10327532096444684545037655626447767452937707424038019114833192172042094083521
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.15281829754793200911418473043803071189451454258031350149018987214487649843926
Short name T398
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.28 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:18:24 PM PST 23
Peak memory 210800 kb
Host smart-f82c8d3a-6fde-43a4-9626-43bc40015063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15281829754793200911418473043803071189451454258031350149018987214487649843926 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.15281829754793200911418473043803071189451454258031350149018987214487649843926
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.54999077556080173088973154041204672678534779992518922848638855554963734497062
Short name T387
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Nov 22 01:16:34 PM PST 23
Finished Nov 22 01:16:48 PM PST 23
Peak memory 210688 kb
Host smart-9d5e76bd-5d55-428c-8cc6-c5dd003d6862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54999077556080173088973154041204672678534779992518922848638855554963734497062 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.54999077556080173088973154041204672678534779992518922848638855554963734497062
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.48019859174666839955835849033326388097133404747012149320184820940910912770663
Short name T422
Test name
Test status
Simulation time 65914678386 ps
CPU time 288.52 seconds
Started Nov 22 01:16:41 PM PST 23
Finished Nov 22 01:21:31 PM PST 23
Peak memory 218584 kb
Host smart-bbeb4efc-e190-47be-8643-9540fb66ff5f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48019859174666839955835849033326388097133404747012149320184820940910912770663 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.4801985917466683995583584903332638809713340474701214932
0184820940910912770663
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.14433779736090049812206681940360742216254835012722718876739922782750235897941
Short name T395
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.27 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:17 PM PST 23
Peak memory 210800 kb
Host smart-e1b44fe2-57a7-47c2-8b96-f573fd5b46ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14433779736090049812206681940360742216254835012722718876739922782750235897941
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.14433779736090049812206681940360742216254835012722718
876739922782750235897941
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.101959381853742641267656868366396949723388887356876489216506419375800692873411
Short name T424
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.98 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:22 PM PST 23
Peak memory 219036 kb
Host smart-9bb33bea-60a8-4182-8e98-24d3a31990cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101959381853742641267656868366396949723388887356876489216506419375800692873411 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.101959381853742641267656868366396949723388887356876489216506419375800692873411
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.44190587225187551748784158380155533342920630938675457020361803475553912358657
Short name T436
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.68 seconds
Started Nov 22 01:17:26 PM PST 23
Finished Nov 22 01:18:51 PM PST 23
Peak memory 211060 kb
Host smart-4630d722-3cbd-4683-b58f-49c0ea7156d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44190587225187551748784158380155533342920630938675457020361803475553912358657 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.44190587225187551748784158380155533342920630938675457020361803475553912358657
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.27128775859472223453115449520878877116255471888116291750334808730378126098510
Short name T372
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.68 seconds
Started Nov 22 01:17:14 PM PST 23
Finished Nov 22 01:17:33 PM PST 23
Peak memory 213364 kb
Host smart-12e8141b-5857-4651-949c-6fcf87fe0186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712877585947222345311544952087887711625547
1888116291750334808730378126098510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.271287758594
72223453115449520878877116255471888116291750334808730378126098510
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.7186167349956085521654323081287322444287019778813075734167969920811831983855
Short name T421
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.52 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:15 PM PST 23
Peak memory 210816 kb
Host smart-9f7616e1-981d-411b-838a-7240b86ad8f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7186167349956085521654323081287322444287019778813075734167969920811831983855 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.7186167349956085521654323081287322444287019778813075734167969920811831983855
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.71473590178091361398335676226277226049663128362494338918777602817212562731776
Short name T423
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.98 seconds
Started Nov 22 01:18:06 PM PST 23
Finished Nov 22 01:22:57 PM PST 23
Peak memory 218924 kb
Host smart-e4d73cfc-eb3c-48bb-90d7-b5bae958204f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71473590178091361398335676226277226049663128362494338918777602817212562731776 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.7147359017809136139833567622627722604966312836249433891
8777602817212562731776
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.92871217469509295923130558639421071244625888378304002734388150372838195724256
Short name T106
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.15 seconds
Started Nov 22 01:16:34 PM PST 23
Finished Nov 22 01:16:50 PM PST 23
Peak memory 210484 kb
Host smart-caff04f2-6fd2-417d-9c54-59f9c5b457d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92871217469509295923130558639421071244625888378304002734388150372838195724256
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.92871217469509295923130558639421071244625888378304002
734388150372838195724256
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.89864823594986566389375400681099372433773457538126100864888163033197893489237
Short name T71
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.3 seconds
Started Nov 22 01:16:37 PM PST 23
Finished Nov 22 01:16:55 PM PST 23
Peak memory 218920 kb
Host smart-f7be5870-b0b2-4fa6-b2e7-2bd5fa05e4f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89864823594986566389375400681099372433773457538126100864888163033197893489237 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.89864823594986566389375400681099372433773457538126100864888163033197893489237
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.23824572318842381940076793233508516086894246672422042363935106814378034131483
Short name T50
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.42 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 211048 kb
Host smart-39bc2136-4768-4da6-a41e-4d53b1424b98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23824572318842381940076793233508516086894246672422042363935106814378034131483 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.23824572318842381940076793233508516086894246672422042363935106814378034131483
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.12246079856864861679700904797085393940230514001830863106792636168566662313077
Short name T25
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.63 seconds
Started Nov 22 01:17:13 PM PST 23
Finished Nov 22 01:17:32 PM PST 23
Peak memory 213408 kb
Host smart-1c38d20b-2898-473a-8230-8fbba45cc42e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224607985686486167970090479708539394023051
4001830863106792636168566662313077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.122460798568
64861679700904797085393940230514001830863106792636168566662313077
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.46485158797796259984744088903414521591377354328256849489172442266929240100473
Short name T78
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.29 seconds
Started Nov 22 01:16:37 PM PST 23
Finished Nov 22 01:16:51 PM PST 23
Peak memory 210688 kb
Host smart-0f3125b8-b0bf-4f86-9972-ca5c14548725
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46485158797796259984744088903414521591377354328256849489172442266929240100473 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.46485158797796259984744088903414521591377354328256849489172442266929240100473
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.68153338065568210175335845403320242003484153674170641820873771208087089588640
Short name T82
Test name
Test status
Simulation time 65914678386 ps
CPU time 284.84 seconds
Started Nov 22 01:16:51 PM PST 23
Finished Nov 22 01:21:46 PM PST 23
Peak memory 218936 kb
Host smart-2f70a23c-294c-441a-a81d-2b75de910842
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68153338065568210175335845403320242003484153674170641820873771208087089588640 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.6815333806556821017533584540332024200348415367417064182
0873771208087089588640
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.53919034169885622961914555198504142727440406362209241502458843985699073467732
Short name T87
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.08 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:20 PM PST 23
Peak memory 210792 kb
Host smart-41bcc957-b545-47c1-9264-2a3cd3602373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53919034169885622961914555198504142727440406362209241502458843985699073467732
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.53919034169885622961914555198504142727440406362209241
502458843985699073467732
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.8683431046399686896927709129497053864551790407566771825566348685399885092796
Short name T73
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.71 seconds
Started Nov 22 01:16:57 PM PST 23
Finished Nov 22 01:17:24 PM PST 23
Peak memory 218900 kb
Host smart-2cd9ad69-d7f6-4646-9b50-4f2a9a43ce61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8683431046399686896927709129497053864551790407566771825566348685399885092796 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.8683431046399686896927709129497053864551790407566771825566348685399885092796
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.103117900458160212525616679778495050187993042652066441099675558993859443071590
Short name T419
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.87 seconds
Started Nov 22 01:16:51 PM PST 23
Finished Nov 22 01:18:24 PM PST 23
Peak memory 210452 kb
Host smart-15aa033f-b3fa-4da4-9e10-9053847c7028
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103117900458160212525616679778495050187993042652066441099675558993859443071590 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.103117900458160212525616679778495050187993042652066441099675558993859443071590
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.53415341925922699125826911677240902968293804528735425097563085237273759199073
Short name T380
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.61 seconds
Started Nov 22 01:16:36 PM PST 23
Finished Nov 22 01:16:51 PM PST 23
Peak memory 213328 kb
Host smart-60c971ff-3647-4d28-86f3-b10bc325f3e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5341534192592269912582691167724090296829380
4528735425097563085237273759199073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.534153419259
22699125826911677240902968293804528735425097563085237273759199073
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.108038666882905088748265814509800597519136408803141639690825476646888740762103
Short name T405
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.49 seconds
Started Nov 22 01:16:36 PM PST 23
Finished Nov 22 01:16:51 PM PST 23
Peak memory 210792 kb
Host smart-8d435295-4000-44b7-bded-3e4935ac7215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108038666882905088748265814509800597519136408803141639690825476646888740762103 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.108038666882905088748265814509800597519136408803141639690825476646888740762103
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.28256642271640571096820317451233770868897119201001567147008135719731273698587
Short name T79
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.84 seconds
Started Nov 22 01:16:33 PM PST 23
Finished Nov 22 01:21:21 PM PST 23
Peak memory 218960 kb
Host smart-6b2d0cd4-e8f9-4ef6-8047-80786684920f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28256642271640571096820317451233770868897119201001567147008135719731273698587 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.2825664227164057109682031745123377086889711920100156714
7008135719731273698587
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.70469340958323740109989006856098249612832047062809685206381457388014178242063
Short name T449
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.33 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:17 PM PST 23
Peak memory 210808 kb
Host smart-52ac6feb-ba33-4904-a438-94cc55a3908a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70469340958323740109989006856098249612832047062809685206381457388014178242063
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.70469340958323740109989006856098249612832047062809685
206381457388014178242063
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.64704147546226526816069367971339294204577639351706680801119631721613268249372
Short name T429
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.6 seconds
Started Nov 22 01:16:44 PM PST 23
Finished Nov 22 01:17:02 PM PST 23
Peak memory 219008 kb
Host smart-1ae751a8-6c5b-4d26-b01d-ae79a1390d69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64704147546226526816069367971339294204577639351706680801119631721613268249372 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.64704147546226526816069367971339294204577639351706680801119631721613268249372
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.86359709500921872096673701138287137910775972568320150068326166011169791252773
Short name T447
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.47 seconds
Started Nov 22 01:16:50 PM PST 23
Finished Nov 22 01:18:22 PM PST 23
Peak memory 211044 kb
Host smart-50ebf0da-2dbb-4a63-88c8-59796b6cc9f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86359709500921872096673701138287137910775972568320150068326166011169791252773 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.86359709500921872096673701138287137910775972568320150068326166011169791252773
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.6204262369908708422277225852675469624888533465610049647567467849068903676396
Short name T24
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.09 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:15 PM PST 23
Peak memory 213412 kb
Host smart-2c8b27f6-b6f1-4618-ad81-c8561eb29d2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6204262369908708422277225852675469624888533
465610049647567467849068903676396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.6204262369908
708422277225852675469624888533465610049647567467849068903676396
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.107705297601054800455392318865014643167133905743839046848198425406665987304797
Short name T370
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.9 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:14 PM PST 23
Peak memory 210540 kb
Host smart-b55a7ffe-051c-4251-8275-10d73658e942
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107705297601054800455392318865014643167133905743839046848198425406665987304797 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.107705297601054800455392318865014643167133905743839046848198425406665987304797
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.44899451860257935458583760621913851986503222023938483051534088172622975571122
Short name T414
Test name
Test status
Simulation time 65914678386 ps
CPU time 280.83 seconds
Started Nov 22 01:16:57 PM PST 23
Finished Nov 22 01:21:50 PM PST 23
Peak memory 218820 kb
Host smart-81541e32-b0de-4eec-9fc2-c5af204e173b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44899451860257935458583760621913851986503222023938483051534088172622975571122 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.4489945186025793545858376062191385198650322202393848305
1534088172622975571122
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.12809733949189516041280916617378668385897425246565994641208072651677870233967
Short name T386
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.82 seconds
Started Nov 22 01:16:51 PM PST 23
Finished Nov 22 01:17:16 PM PST 23
Peak memory 210792 kb
Host smart-5090c5f0-2496-4502-b9bd-cadf373c9d5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12809733949189516041280916617378668385897425246565994641208072651677870233967
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.12809733949189516041280916617378668385897425246565994
641208072651677870233967
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.12087655126961908884307019715773367905583848674712265033625267840350415450511
Short name T51
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.34 seconds
Started Nov 22 01:16:43 PM PST 23
Finished Nov 22 01:17:01 PM PST 23
Peak memory 219008 kb
Host smart-9b29d7b8-1d73-4fa9-8c70-576d0e556553
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12087655126961908884307019715773367905583848674712265033625267840350415450511 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.12087655126961908884307019715773367905583848674712265033625267840350415450511
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.52643767110874318109225296235854595468019108371636321719645238346993915911083
Short name T432
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.96 seconds
Started Nov 22 01:18:06 PM PST 23
Finished Nov 22 01:19:33 PM PST 23
Peak memory 211056 kb
Host smart-42edf3c9-083d-4af6-9181-c6c75d13197d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52643767110874318109225296235854595468019108371636321719645238346993915911083 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.52643767110874318109225296235854595468019108371636321719645238346993915911083
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.103944158554537135264485689432339551826141783122298825638338915474093124696349
Short name T18
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.12 seconds
Started Nov 22 01:16:51 PM PST 23
Finished Nov 22 01:17:14 PM PST 23
Peak memory 212832 kb
Host smart-2014385e-11fb-42bd-b27c-251c2ae0bce9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039441585545371352644856894323395518261417
83122298825638338915474093124696349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.10394415855
4537135264485689432339551826141783122298825638338915474093124696349
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.14656351519860668328038124425199532148029519802932515323505910321922538682250
Short name T448
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.24 seconds
Started Nov 22 01:16:49 PM PST 23
Finished Nov 22 01:17:05 PM PST 23
Peak memory 210812 kb
Host smart-359e1fa7-722a-448d-af60-d5b977cbc4e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14656351519860668328038124425199532148029519802932515323505910321922538682250 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.14656351519860668328038124425199532148029519802932515323505910321922538682250
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.19066605917340979166347833709180794182018451190170248379148865636696180213960
Short name T80
Test name
Test status
Simulation time 65914678386 ps
CPU time 289 seconds
Started Nov 22 01:16:35 PM PST 23
Finished Nov 22 01:21:26 PM PST 23
Peak memory 218940 kb
Host smart-e2468f6d-b85b-44be-bb42-9f47b365e785
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19066605917340979166347833709180794182018451190170248379148865636696180213960 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.1906660591734097916634783370918079418201845119017024837
9148865636696180213960
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.106652953245887609505657329869209805887576327723563418951382782098747136844749
Short name T418
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.14 seconds
Started Nov 22 01:16:36 PM PST 23
Finished Nov 22 01:16:52 PM PST 23
Peak memory 210820 kb
Host smart-e0f985b4-2f40-4f09-83cb-0f87c5256068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106652953245887609505657329869209805887576327723563418951382782098747136844749
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.1066529532458876095056573298692098058875763277235634
18951382782098747136844749
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.65648548209216802136529673123264741356815472026736951087183184758822841081280
Short name T446
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.68 seconds
Started Nov 22 01:16:35 PM PST 23
Finished Nov 22 01:16:54 PM PST 23
Peak memory 219000 kb
Host smart-44dab36e-d20b-470a-9e52-c0af4e01fda1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65648548209216802136529673123264741356815472026736951087183184758822841081280 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.65648548209216802136529673123264741356815472026736951087183184758822841081280
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.64005815658760182201271636453495770326121547211304489903271738876639022660030
Short name T57
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.45 seconds
Started Nov 22 01:16:49 PM PST 23
Finished Nov 22 01:18:15 PM PST 23
Peak memory 211052 kb
Host smart-3ac77438-54c6-422e-9085-dd52bba75ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64005815658760182201271636453495770326121547211304489903271738876639022660030 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.64005815658760182201271636453495770326121547211304489903271738876639022660030
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.18606912674795185591713759176861996245700831590091883321306964825930992338269
Short name T383
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.01 seconds
Started Nov 22 01:16:57 PM PST 23
Finished Nov 22 01:17:21 PM PST 23
Peak memory 213384 kb
Host smart-3bec73e3-8b00-4d9c-a533-2d25eb175244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860691267479518559171375917686199624570083
1590091883321306964825930992338269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.186069126747
95185591713759176861996245700831590091883321306964825930992338269
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.84495971568821709406729342811177432803018347710875546663845851088609107969289
Short name T108
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Nov 22 01:16:58 PM PST 23
Finished Nov 22 01:17:21 PM PST 23
Peak memory 210756 kb
Host smart-00ab4fe5-d235-42cf-a209-cd6195cccd2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84495971568821709406729342811177432803018347710875546663845851088609107969289 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.84495971568821709406729342811177432803018347710875546663845851088609107969289
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.94442576501082018230198019576522093743348348630125042718154159772078047773818
Short name T396
Test name
Test status
Simulation time 65914678386 ps
CPU time 278.12 seconds
Started Nov 22 01:18:44 PM PST 23
Finished Nov 22 01:23:25 PM PST 23
Peak memory 218536 kb
Host smart-6be33d60-d072-4a96-8da0-efab81fecaed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94442576501082018230198019576522093743348348630125042718154159772078047773818 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.9444257650108201823019801957652209374334834863012504271
8154159772078047773818
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.34315984062345681384506419579967601067691704898184890778161148250762367454737
Short name T375
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.08 seconds
Started Nov 22 01:17:15 PM PST 23
Finished Nov 22 01:17:35 PM PST 23
Peak memory 210700 kb
Host smart-a0fc753b-a8b7-490e-ae03-1d2366896048
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34315984062345681384506419579967601067691704898184890778161148250762367454737
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.34315984062345681384506419579967601067691704898184890
778161148250762367454737
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.98017819747394459648555403380679460174418787958391245292315893368259998617913
Short name T68
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.72 seconds
Started Nov 22 01:16:36 PM PST 23
Finished Nov 22 01:16:55 PM PST 23
Peak memory 218984 kb
Host smart-853320cd-cb93-44c3-b666-80bcc88b1a6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98017819747394459648555403380679460174418787958391245292315893368259998617913 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.98017819747394459648555403380679460174418787958391245292315893368259998617913
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.74049188654147899657587941679348926023238212852835191651426697782764573038081
Short name T397
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.36 seconds
Started Nov 22 01:17:07 PM PST 23
Finished Nov 22 01:18:37 PM PST 23
Peak memory 210876 kb
Host smart-94b040a2-5c4a-4daf-a316-47e1dc984be9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74049188654147899657587941679348926023238212852835191651426697782764573038081 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.74049188654147899657587941679348926023238212852835191651426697782764573038081
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.68400461538825752297104515393744470453235755058603922025310825193551929138100
Short name T102
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.14 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:18 PM PST 23
Peak memory 210788 kb
Host smart-cb70db7a-5299-44ef-993b-8c660c597433
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68400461538825752297104515393744470453235755058603922025310825193551929138100 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.68400461538825752297104515393744470453235755058603922025310825193551929138100
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.84145986723403736567429302138322914555505408511900069451696540294401024817061
Short name T98
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.83 seconds
Started Nov 22 01:16:36 PM PST 23
Finished Nov 22 01:16:51 PM PST 23
Peak memory 210796 kb
Host smart-aaddaf25-3319-4879-801b-dcadb774e6a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84145986723403736567429302138322914555505408511900069451696540294401024817061 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.84145986723403736567429302138322914555505408511900069451696540294401024817061
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.80331997401337559734824460074915843101220181956691639980342380042988046450799
Short name T388
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.87 seconds
Started Nov 22 01:16:39 PM PST 23
Finished Nov 22 01:16:56 PM PST 23
Peak memory 210700 kb
Host smart-96dd00e6-a537-4644-afe3-1d4ce6a8d8e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80331997401337559734824460074915843101220181956691639980342380042988046450799 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.80331997401337559734824460074915843101220181956691639980342380042988046450799
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.72830456161481082306120592354110621749136485430628316909136793080084294984378
Short name T377
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.58 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:18 PM PST 23
Peak memory 213412 kb
Host smart-80d0f0ca-d3f9-4908-abb6-e1f5a7f0950e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7283045616148108230612059235411062174913648
5430628316909136793080084294984378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.7283045616148
1082306120592354110621749136485430628316909136793080084294984378
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.93784128329267269455415193817458564292905149517230153735094171601978506798586
Short name T394
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.18 seconds
Started Nov 22 01:16:36 PM PST 23
Finished Nov 22 01:16:51 PM PST 23
Peak memory 210812 kb
Host smart-30cc9774-6671-488c-94e0-af164bab614f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93784128329267269455415193817458564292905149517230153735094171601978506798586 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.93784128329267269455415193817458564292905149517230153735094171601978506798586
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.115051359479883768650624400273735580482671212339325440519253620039724417221729
Short name T65
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.87 seconds
Started Nov 22 01:16:58 PM PST 23
Finished Nov 22 01:17:21 PM PST 23
Peak memory 210780 kb
Host smart-2edb49bb-58ba-4723-b708-0b93ffe60e63
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115051359479883768650624400273735580482671212339325440519253620039724417221729 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.115051359479883768650624400273735580482671212339325440519
253620039724417221729
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.115527164015556520557927670040015607189966667229362664362397277039260160602869
Short name T104
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Nov 22 01:16:38 PM PST 23
Finished Nov 22 01:16:51 PM PST 23
Peak memory 210824 kb
Host smart-def5c9c8-3f41-4a36-b8d8-b68a758e4c1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115527164015556520557927670040015607189966667229362664362397277039260160602869 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.115527164015556520557927670040015607189966667229362664362397277039260160602869
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.51529702863509658706422238463393988970788162512143542214399464973716200744326
Short name T83
Test name
Test status
Simulation time 65914678386 ps
CPU time 294.88 seconds
Started Nov 22 01:16:24 PM PST 23
Finished Nov 22 01:21:21 PM PST 23
Peak memory 218804 kb
Host smart-769953e0-4762-4861-839f-fd62d0a7e1de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51529702863509658706422238463393988970788162512143542214399464973716200744326 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.51529702863509658706422238463393988970788162512143542214
399464973716200744326
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.83149169321933232782662728156176308162234458241363716607025672806920429412784
Short name T61
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.57 seconds
Started Nov 22 01:16:58 PM PST 23
Finished Nov 22 01:17:22 PM PST 23
Peak memory 210768 kb
Host smart-81500730-01a7-43af-9583-e4bd8e2889c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83149169321933232782662728156176308162234458241363716607025672806920429412784
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.831491693219332327826627281561763081622344582413637166
07025672806920429412784
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.69339694854844616691273814280545525874057572570579063987707724065549837546897
Short name T392
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.22 seconds
Started Nov 22 01:16:40 PM PST 23
Finished Nov 22 01:16:58 PM PST 23
Peak memory 219008 kb
Host smart-5d62c66e-d371-4565-9570-77697a224ed4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69339694854844616691273814280545525874057572570579063987707724065549837546897 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.69339694854844616691273814280545525874057572570579063987707724065549837546897
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.64934802183047915468002400583045605838170549904211024426236810102050983789132
Short name T400
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.14 seconds
Started Nov 22 01:16:41 PM PST 23
Finished Nov 22 01:18:04 PM PST 23
Peak memory 210984 kb
Host smart-0f98f032-4cd9-409b-862a-a56f50103e80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64934802183047915468002400583045605838170549904211024426236810102050983789132 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.64934802183047915468002400583045605838170549904211024426236810102050983789132
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.44698211041226657848801778652997399888385614382187410881618548189803398012639
Short name T99
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Nov 22 01:16:40 PM PST 23
Finished Nov 22 01:16:53 PM PST 23
Peak memory 210700 kb
Host smart-f6bff341-4d11-4cb3-962b-928d9e33553c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44698211041226657848801778652997399888385614382187410881618548189803398012639 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.44698211041226657848801778652997399888385614382187410881618548189803398012639
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.93204130212852234120304383608608812099519337600227974811319231040668036366093
Short name T408
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.66 seconds
Started Nov 22 01:16:33 PM PST 23
Finished Nov 22 01:16:47 PM PST 23
Peak memory 210792 kb
Host smart-e6d76c3d-ee11-4127-9984-fb47d02f7239
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93204130212852234120304383608608812099519337600227974811319231040668036366093 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.93204130212852234120304383608608812099519337600227974811319231040668036366093
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.50546317529645369717275143940342112221144636151664712849355634443349993595251
Short name T60
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.36 seconds
Started Nov 22 01:16:39 PM PST 23
Finished Nov 22 01:16:56 PM PST 23
Peak memory 210700 kb
Host smart-0f2b5d4a-aa03-4de7-95db-12e5212705f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50546317529645369717275143940342112221144636151664712849355634443349993595251 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.50546317529645369717275143940342112221144636151664712849355634443349993595251
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.93602349301146603398935124099486272396946102912043532427771578507621750349143
Short name T52
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.5 seconds
Started Nov 22 01:16:30 PM PST 23
Finished Nov 22 01:16:44 PM PST 23
Peak memory 213424 kb
Host smart-31c382a8-f34b-41f0-b9d9-d54035cb53b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9360234930114660339893512409948627239694610
2912043532427771578507621750349143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.9360234930114
6603398935124099486272396946102912043532427771578507621750349143
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.68964730390510928711635854856769700344760588399360673402958378019407312950418
Short name T59
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.11 seconds
Started Nov 22 01:16:24 PM PST 23
Finished Nov 22 01:16:38 PM PST 23
Peak memory 210788 kb
Host smart-4604c99e-f34c-472c-8c07-a1f5a191090f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68964730390510928711635854856769700344760588399360673402958378019407312950418 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.68964730390510928711635854856769700344760588399360673402958378019407312950418
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.89292172854871341620681164444409874449750164899579333770330283106319825403363
Short name T420
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.01 seconds
Started Nov 22 01:16:22 PM PST 23
Finished Nov 22 01:16:37 PM PST 23
Peak memory 210700 kb
Host smart-e942e776-9fd4-4df2-9e2d-66d96bbf6c38
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89292172854871341620681164444409874449750164899579333770330283106319825403363 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.8929217285487134162068116444440987444975016489957933377033
0283106319825403363
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.98844342397396090246487092124314221221117923131735067676037345703928384456470
Short name T66
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.14 seconds
Started Nov 22 01:16:22 PM PST 23
Finished Nov 22 01:16:37 PM PST 23
Peak memory 210780 kb
Host smart-9a12be45-ae87-409c-b8bc-5180e141e4bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98844342397396090246487092124314221221117923131735067676037345703928384456470 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.98844342397396090246487092124314221221117923131735067676037345703928384456470
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.33924537780176711128654343411076521646671023979344181348345749790734270771341
Short name T81
Test name
Test status
Simulation time 65914678386 ps
CPU time 289.97 seconds
Started Nov 22 01:17:16 PM PST 23
Finished Nov 22 01:22:12 PM PST 23
Peak memory 218804 kb
Host smart-bacead51-d943-4711-a52c-7bcfb08d8d8d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33924537780176711128654343411076521646671023979344181348345749790734270771341 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.33924537780176711128654343411076521646671023979344181348
345749790734270771341
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.38763912804167724441135484280052683736245084393373246181576834797589591567279
Short name T88
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.26 seconds
Started Nov 22 01:16:23 PM PST 23
Finished Nov 22 01:16:39 PM PST 23
Peak memory 210752 kb
Host smart-875e090d-11e0-4da5-bc7c-e7de287530d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38763912804167724441135484280052683736245084393373246181576834797589591567279
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.387639128041677244411354842800526837362450843933732461
81576834797589591567279
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.93821958677239403755250391592231589641651487360106724322816652439937720731160
Short name T385
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.98 seconds
Started Nov 22 01:16:30 PM PST 23
Finished Nov 22 01:16:47 PM PST 23
Peak memory 218900 kb
Host smart-3569a12c-8642-44a0-bb58-b7d3a6c79d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93821958677239403755250391592231589641651487360106724322816652439937720731160 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.93821958677239403755250391592231589641651487360106724322816652439937720731160
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.9577454980723496267552553063235009336855831872385350215544713621873509554700
Short name T49
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.15 seconds
Started Nov 22 01:16:24 PM PST 23
Finished Nov 22 01:17:48 PM PST 23
Peak memory 211068 kb
Host smart-3cdcb567-8684-4a4f-91e5-9295ccee5c0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9577454980723496267552553063235009336855831872385350215544713621873509554700 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.9577454980723496267552553063235009336855831872385350215544713621873509554700
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.70908429648811832069995781304660543739359035406645911082635227500674883736023
Short name T26
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Nov 22 01:16:35 PM PST 23
Finished Nov 22 01:16:50 PM PST 23
Peak memory 210820 kb
Host smart-2080780f-d6a7-42c4-a254-e67079f1647f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70908429648811832069995781304660543739359035406645911082635227500674883736023 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.70908429648811832069995781304660543739359035406645911082635227500674883736023
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.66274486722898824886402617620057113608765689313139130265729158461451000128179
Short name T101
Test name
Test status
Simulation time 3124113076 ps
CPU time 13.11 seconds
Started Nov 22 01:16:43 PM PST 23
Finished Nov 22 01:16:57 PM PST 23
Peak memory 210772 kb
Host smart-d004febe-ff9f-43f9-938e-3565fe6e6e3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66274486722898824886402617620057113608765689313139130265729158461451000128179 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.66274486722898824886402617620057113608765689313139130265729158461451000128179
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.49495243886101834234589869962712570962416718806202690703528400561996565349836
Short name T431
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.71 seconds
Started Nov 22 01:16:30 PM PST 23
Finished Nov 22 01:16:47 PM PST 23
Peak memory 210812 kb
Host smart-1c371ce7-ffce-4738-9dc2-443b29e93b86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49495243886101834234589869962712570962416718806202690703528400561996565349836 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.49495243886101834234589869962712570962416718806202690703528400561996565349836
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.46771612132892860424967877779909010790104581385603622818827458400119435709603
Short name T23
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.51 seconds
Started Nov 22 01:16:22 PM PST 23
Finished Nov 22 01:16:36 PM PST 23
Peak memory 213424 kb
Host smart-7a333c4d-673f-4be0-8f19-ad09c0b8fc03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4677161213289286042496787777990901079010458
1385603622818827458400119435709603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4677161213289
2860424967877779909010790104581385603622818827458400119435709603
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.42448907138159787257534314271481090260892880985664307054502019500760953556602
Short name T412
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.27 seconds
Started Nov 22 01:16:35 PM PST 23
Finished Nov 22 01:16:50 PM PST 23
Peak memory 210772 kb
Host smart-54a542d7-26ea-420e-8b61-8846e22d7e39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42448907138159787257534314271481090260892880985664307054502019500760953556602 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.42448907138159787257534314271481090260892880985664307054502019500760953556602
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.99341301892701861510081226853800542031408525779065911126757611734369963640334
Short name T399
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.96 seconds
Started Nov 22 01:16:33 PM PST 23
Finished Nov 22 01:16:46 PM PST 23
Peak memory 210692 kb
Host smart-02af44c9-4720-49be-9019-0e73ad6f217e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99341301892701861510081226853800542031408525779065911126757611734369963640334 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.9934130189270186151008122685380054203140852577906591112675
7611734369963640334
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.12867369004195872438692622115054449514606127305897776407221520114370193697831
Short name T373
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.17 seconds
Started Nov 22 01:16:35 PM PST 23
Finished Nov 22 01:16:50 PM PST 23
Peak memory 210796 kb
Host smart-08d33e46-c6cf-4cc6-8578-907078065d2c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12867369004195872438692622115054449514606127305897776407221520114370193697831 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.12867369004195872438692622115054449514606127305897776407221520114370193697831
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.20544158488271338673919351084866472424017406471511694503616411115754532727824
Short name T389
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.02 seconds
Started Nov 22 01:16:31 PM PST 23
Finished Nov 22 01:16:46 PM PST 23
Peak memory 210768 kb
Host smart-60a9218e-3456-4de4-870b-32795bc0ae89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20544158488271338673919351084866472424017406471511694503616411115754532727824
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.205441584882713386739193510848664724240174064715116945
03616411115754532727824
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.46475917767450060853469754173484503033340134837654618462418096919477519342526
Short name T426
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.49 seconds
Started Nov 22 01:16:22 PM PST 23
Finished Nov 22 01:16:41 PM PST 23
Peak memory 219060 kb
Host smart-c444be28-1875-4f35-9562-41685340f73a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46475917767450060853469754173484503033340134837654618462418096919477519342526 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.46475917767450060853469754173484503033340134837654618462418096919477519342526
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2756152705863407079415958262201128966479600227252787538627068451210282298399
Short name T425
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.03 seconds
Started Nov 22 01:16:23 PM PST 23
Finished Nov 22 01:17:47 PM PST 23
Peak memory 211028 kb
Host smart-34d5a723-b6e8-47ba-971c-3b10239f9402
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756152705863407079415958262201128966479600227252787538627068451210282298399 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.2756152705863407079415958262201128966479600227252787538627068451210282298399
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.68048353530373573660999772285757044799150998817576491323042243358387257051378
Short name T376
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.41 seconds
Started Nov 22 01:16:41 PM PST 23
Finished Nov 22 01:16:55 PM PST 23
Peak memory 213292 kb
Host smart-f11fd4ff-e84b-4ec9-b147-7efb14a57809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6804835353037357366099977228575704479915099
8817576491323042243358387257051378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.6804835353037
3573660999772285757044799150998817576491323042243358387257051378
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.111018878567762978558139914872860697097868575039233584988107301677107720470486
Short name T62
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.26 seconds
Started Nov 22 01:16:31 PM PST 23
Finished Nov 22 01:16:44 PM PST 23
Peak memory 210812 kb
Host smart-3a4f33a5-3828-4f98-aff0-cd46ca48757b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111018878567762978558139914872860697097868575039233584988107301677107720470486 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.111018878567762978558139914872860697097868575039233584988107301677107720470486
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.109645492236484845081247470764480704573458775089238441251774142756502134195431
Short name T32
Test name
Test status
Simulation time 65914678386 ps
CPU time 290.3 seconds
Started Nov 22 01:16:32 PM PST 23
Finished Nov 22 01:21:24 PM PST 23
Peak memory 218944 kb
Host smart-f4346f8b-7458-4707-a650-5a352f9178a2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109645492236484845081247470764480704573458775089238441251774142756502134195431 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.1096454922364848450812474707644807045734587750892384412
51774142756502134195431
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.92772885091190227588296643437932476292342384082434592714300951693208508141511
Short name T63
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.25 seconds
Started Nov 22 01:16:21 PM PST 23
Finished Nov 22 01:16:38 PM PST 23
Peak memory 210804 kb
Host smart-8444a9e1-123d-4327-bcf1-4238b93871d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92772885091190227588296643437932476292342384082434592714300951693208508141511
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.927728850911902275882966434379324762923423840824345927
14300951693208508141511
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.31927525070229301145174267623718633021454563105109086078710949077666441624674
Short name T69
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.37 seconds
Started Nov 22 01:16:30 PM PST 23
Finished Nov 22 01:16:48 PM PST 23
Peak memory 219024 kb
Host smart-519744f7-69b1-4e59-a8cd-cdbde60f6bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31927525070229301145174267623718633021454563105109086078710949077666441624674 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.31927525070229301145174267623718633021454563105109086078710949077666441624674
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.100886731202495562579471271931505200461502804700415282724643074457257554528201
Short name T384
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.52 seconds
Started Nov 22 01:16:44 PM PST 23
Finished Nov 22 01:18:06 PM PST 23
Peak memory 211020 kb
Host smart-b277ff0a-05fb-45bc-b0e4-ab3c287ffc0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100886731202495562579471271931505200461502804700415282724643074457257554528201 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.100886731202495562579471271931505200461502804700415282724643074457257554528201
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.46313078040012401536486809770703403458680910368045688046308160320432270105916
Short name T434
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.31 seconds
Started Nov 22 01:17:05 PM PST 23
Finished Nov 22 01:17:27 PM PST 23
Peak memory 213412 kb
Host smart-d6a1a5a9-6257-41e1-8cd7-2a1afb729f56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4631307804001240153648680977070340345868091
0368045688046308160320432270105916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4631307804001
2401536486809770703403458680910368045688046308160320432270105916
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.67848433672146786595536951833434240050108855134461909992770163588074647342963
Short name T379
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.31 seconds
Started Nov 22 01:16:48 PM PST 23
Finished Nov 22 01:17:04 PM PST 23
Peak memory 210804 kb
Host smart-dfe93164-1e22-47a3-8094-4d7afee07315
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67848433672146786595536951833434240050108855134461909992770163588074647342963 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.67848433672146786595536951833434240050108855134461909992770163588074647342963
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.21796929983919137497493748823502686512255091127097184128264036753588670161551
Short name T84
Test name
Test status
Simulation time 65914678386 ps
CPU time 284.04 seconds
Started Nov 22 01:16:33 PM PST 23
Finished Nov 22 01:21:18 PM PST 23
Peak memory 218800 kb
Host smart-2c0fec51-a1a3-4b3b-bafd-6c1713e692f7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21796929983919137497493748823502686512255091127097184128264036753588670161551 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.21796929983919137497493748823502686512255091127097184128
264036753588670161551
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.69818809117588057320698179106925490117046513428291306584062945197536881917525
Short name T378
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.99 seconds
Started Nov 22 01:16:40 PM PST 23
Finished Nov 22 01:16:55 PM PST 23
Peak memory 210752 kb
Host smart-86424550-b3d4-4599-95fc-266ce1ed1ee9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69818809117588057320698179106925490117046513428291306584062945197536881917525
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.698188091175880573206981791069254901170465134282913065
84062945197536881917525
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.52742997963875109160049267056466797005045391518186283148123653150500876168025
Short name T22
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.61 seconds
Started Nov 22 01:16:31 PM PST 23
Finished Nov 22 01:16:49 PM PST 23
Peak memory 219060 kb
Host smart-317f3e0d-821c-45ae-9288-1fec4dabbe72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52742997963875109160049267056466797005045391518186283148123653150500876168025 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.52742997963875109160049267056466797005045391518186283148123653150500876168025
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.13719272373535320834791517288027809932526726397506866859831705911041249762773
Short name T58
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.39 seconds
Started Nov 22 01:16:30 PM PST 23
Finished Nov 22 01:17:52 PM PST 23
Peak memory 211036 kb
Host smart-4698f409-91b0-4b16-8691-524a675e1655
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13719272373535320834791517288027809932526726397506866859831705911041249762773 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.13719272373535320834791517288027809932526726397506866859831705911041249762773
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.78658793997420927166118745432275363703404195230880522224220062719403392770697
Short name T54
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.68 seconds
Started Nov 22 01:16:50 PM PST 23
Finished Nov 22 01:17:13 PM PST 23
Peak memory 213412 kb
Host smart-81580706-949f-44f9-9ebe-c82d2456887c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7865879399742092716611874543227536370340419
5230880522224220062719403392770697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.7865879399742
0927166118745432275363703404195230880522224220062719403392770697
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.87208039674802530998085313838213320832409808701356981829123185526327321388081
Short name T410
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Nov 22 01:16:21 PM PST 23
Finished Nov 22 01:16:35 PM PST 23
Peak memory 210816 kb
Host smart-5b1895ce-601c-47d9-9034-1f0f0d83bc54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87208039674802530998085313838213320832409808701356981829123185526327321388081 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.87208039674802530998085313838213320832409808701356981829123185526327321388081
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.5820907030799179230843325079600903223161219206032975073101559448093202789102
Short name T409
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.66 seconds
Started Nov 22 01:16:23 PM PST 23
Finished Nov 22 01:21:08 PM PST 23
Peak memory 218912 kb
Host smart-0d85c126-b149-47f7-b10b-b307c3e3896f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5820907030799179230843325079600903223161219206032975073101559448093202789102 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.582090703079917923084332507960090322316121920603297507310
1559448093202789102
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.39212952393554571195991179649396116994700120008264067767371271881348930624674
Short name T21
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.23 seconds
Started Nov 22 01:16:21 PM PST 23
Finished Nov 22 01:16:38 PM PST 23
Peak memory 210824 kb
Host smart-e4c52c8f-0120-40ba-ba2b-531ee3faa7bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39212952393554571195991179649396116994700120008264067767371271881348930624674
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.392129523935545711959911796493961169947001200082640677
67371271881348930624674
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.82090293524203433699600741774402169248766336607560683847831814657481556388044
Short name T435
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.45 seconds
Started Nov 22 01:16:39 PM PST 23
Finished Nov 22 01:16:57 PM PST 23
Peak memory 219064 kb
Host smart-073715ad-2bcf-48ba-a5a6-1483b28f9b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82090293524203433699600741774402169248766336607560683847831814657481556388044 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.82090293524203433699600741774402169248766336607560683847831814657481556388044
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.95866855303263275040696026772753920745906396095280546939680655861590161198797
Short name T428
Test name
Test status
Simulation time 3476453456 ps
CPU time 81 seconds
Started Nov 22 01:16:33 PM PST 23
Finished Nov 22 01:17:56 PM PST 23
Peak memory 211036 kb
Host smart-c224c760-9925-4a3b-b2c8-b671e1f27073
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95866855303263275040696026772753920745906396095280546939680655861590161198797 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.95866855303263275040696026772753920745906396095280546939680655861590161198797
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.20781314427694708950591450633621346733727368155168749277293547774053007555782
Short name T67
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.51 seconds
Started Nov 22 01:16:50 PM PST 23
Finished Nov 22 01:17:10 PM PST 23
Peak memory 213400 kb
Host smart-ddfd7368-258a-4c89-920b-6de24dc2f3fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078131442769470895059145063362134673372736
8155168749277293547774053007555782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2078131442769
4708950591450633621346733727368155168749277293547774053007555782
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.34868166079609920032932472204597996391340538151321069670605182650337675834660
Short name T393
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.37 seconds
Started Nov 22 01:16:40 PM PST 23
Finished Nov 22 01:16:53 PM PST 23
Peak memory 210712 kb
Host smart-1f39e0e2-456d-417a-b000-b8b24fc72363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34868166079609920032932472204597996391340538151321069670605182650337675834660 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.34868166079609920032932472204597996391340538151321069670605182650337675834660
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.76811142238730725460725432347912421876430631055370510521865469994281672252345
Short name T64
Test name
Test status
Simulation time 65914678386 ps
CPU time 284.23 seconds
Started Nov 22 01:16:42 PM PST 23
Finished Nov 22 01:21:27 PM PST 23
Peak memory 218944 kb
Host smart-1a4948ce-f7aa-4cc8-ba1b-55544b59c17b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76811142238730725460725432347912421876430631055370510521865469994281672252345 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.76811142238730725460725432347912421876430631055370510521
865469994281672252345
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.92085318965964085737092996475473138633428704146855152373862892935140805694539
Short name T406
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.57 seconds
Started Nov 22 01:16:41 PM PST 23
Finished Nov 22 01:16:57 PM PST 23
Peak memory 210732 kb
Host smart-402033f4-e9b9-41dc-9166-4f88f09ef027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92085318965964085737092996475473138633428704146855152373862892935140805694539
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.920853189659640857370929964754731386334287041468551523
73862892935140805694539
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.21899187105614614160806412576297859249973340358323862348812107508913486504595
Short name T416
Test name
Test status
Simulation time 3476453456 ps
CPU time 83.17 seconds
Started Nov 22 01:16:50 PM PST 23
Finished Nov 22 01:18:22 PM PST 23
Peak memory 211016 kb
Host smart-38e13331-cba9-4fc5-9920-5ee69e80ec30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21899187105614614160806412576297859249973340358323862348812107508913486504595 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.21899187105614614160806412576297859249973340358323862348812107508913486504595
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.87024559585171171165198582461826134067490964493891947726791982182167825040334
Short name T443
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.46 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:18 PM PST 23
Peak memory 213344 kb
Host smart-270c1d84-56b1-4f6c-88a0-ee2d17dba3d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8702455958517117116519858246182613406749096
4493891947726791982182167825040334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.8702455958517
1171165198582461826134067490964493891947726791982182167825040334
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3185400115899507131099145239369655540351493766771084188822692539589328896706
Short name T75
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.18 seconds
Started Nov 22 01:16:41 PM PST 23
Finished Nov 22 01:16:54 PM PST 23
Peak memory 210428 kb
Host smart-bb03d528-b67e-443e-b390-064b2203ce8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185400115899507131099145239369655540351493766771084188822692539589328896706 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3185400115899507131099145239369655540351493766771084188822692539589328896706
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.21390893872282160816469662080911527038204711048150182326429880358209371264055
Short name T31
Test name
Test status
Simulation time 65914678386 ps
CPU time 288.25 seconds
Started Nov 22 01:16:22 PM PST 23
Finished Nov 22 01:21:13 PM PST 23
Peak memory 218964 kb
Host smart-4414ea29-cd1e-4016-87a8-9a82f6705766
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21390893872282160816469662080911527038204711048150182326429880358209371264055 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.21390893872282160816469662080911527038204711048150182326
429880358209371264055
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.87205927790525802091168355896466515603833505088809863767328880776149501317340
Short name T107
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.02 seconds
Started Nov 22 01:16:33 PM PST 23
Finished Nov 22 01:16:50 PM PST 23
Peak memory 210820 kb
Host smart-a0cae5b8-0906-44ee-a4ef-2cebeb07735d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87205927790525802091168355896466515603833505088809863767328880776149501317340
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.872059277905258020911683558964665156038335050888098637
67328880776149501317340
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.36876960831422377756144532703807213913017538883956432230450195987078914717922
Short name T382
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.48 seconds
Started Nov 22 01:17:04 PM PST 23
Finished Nov 22 01:17:31 PM PST 23
Peak memory 219044 kb
Host smart-01925aae-b8b4-455e-bfbf-5785015d993f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36876960831422377756144532703807213913017538883956432230450195987078914717922 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.36876960831422377756144532703807213913017538883956432230450195987078914717922
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.71442577098983785933633471551449299520248812402127592892317580976983919257272
Short name T374
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.88 seconds
Started Nov 22 01:16:22 PM PST 23
Finished Nov 22 01:17:46 PM PST 23
Peak memory 210980 kb
Host smart-3264fcc4-5fa6-4945-a042-a79a9e1a5929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71442577098983785933633471551449299520248812402127592892317580976983919257272 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.71442577098983785933633471551449299520248812402127592892317580976983919257272
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.750316113229763309299345545791242102221504647152558440988315980722090476519
Short name T165
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.46 seconds
Started Nov 22 12:36:19 PM PST 23
Finished Nov 22 12:36:33 PM PST 23
Peak memory 211216 kb
Host smart-7cf098df-cfaf-441f-b149-2c588ec0975e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750316113229763309299345545791242102221504647152558440988315980722090476519 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.750316113229763309299345545791242102221504647152558440988315980722090476519
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.5126244246025520929784582829265094653439976907765783750993821716216373907543
Short name T160
Test name
Test status
Simulation time 69854280986 ps
CPU time 350.42 seconds
Started Nov 22 12:36:30 PM PST 23
Finished Nov 22 12:42:21 PM PST 23
Peak memory 237636 kb
Host smart-2670d9f6-79ad-4adf-92c9-feb3d53cadc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5126244246025520929784582829265094653439976907765783750993821716216373907543 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.51262442460255209297845828292650946534399769077657837509938
21716216373907543
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.56043878492236852361921799729531718086083815831910799899031088071157493970802
Short name T224
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.02 seconds
Started Nov 22 12:36:20 PM PST 23
Finished Nov 22 12:36:47 PM PST 23
Peak memory 211496 kb
Host smart-3b08d8f5-9114-42b1-aae5-8483453eaba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56043878492236852361921799729531718086083815831910799899031088071157493970802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.rom_ctrl_kmac_err_chk.56043878492236852361921799729531718086083815831910799899031088071157493970802
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.95226558362697272235467827476186982160731593463858499243209456493094138264792
Short name T297
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.65 seconds
Started Nov 22 12:36:21 PM PST 23
Finished Nov 22 12:36:36 PM PST 23
Peak memory 211088 kb
Host smart-4f431d03-e238-4cb9-97d9-9c302cd41269
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95226558362697272235467827476186982160731593463858499243209456493094138264792 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.95226558362697272235467827476186982160731593463858499243209456493094138264792
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.13247977929428617970162779349648766524232951583195137454648934205629931370751
Short name T264
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.65 seconds
Started Nov 22 12:36:22 PM PST 23
Finished Nov 22 12:36:52 PM PST 23
Peak memory 212824 kb
Host smart-3ce8c85c-4c07-48c3-baa1-58fe6a8998cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13247977929428617970162779349648766524232951583195137454648934205629931370751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.rom_ctrl_smoke.13247977929428617970162779349648766524232951583195137454648934205629931370751
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.22813121995309099774161219124940064115363130661299413920739484426427448124409
Short name T74
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.34 seconds
Started Nov 22 12:36:27 PM PST 23
Finished Nov 22 12:37:11 PM PST 23
Peak memory 212804 kb
Host smart-6c0c18ab-ecbe-484f-88b0-64fd5c5f54de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228131219953090997741612191249400641153631306612994139207394844
26427448124409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.228131219953090997741612191249400641153631306612994
13920739484426427448124409
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.103689004991693602244137340290662293981777361955356825017358773847517484839516
Short name T263
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.83 seconds
Started Nov 22 12:36:21 PM PST 23
Finished Nov 22 12:36:34 PM PST 23
Peak memory 211068 kb
Host smart-5553a677-3435-4c97-8e20-554b830ba603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103689004991693602244137340290662293981777361955356825017358773847517484839516 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.103689004991693602244137340290662293981777361955356825017358773847517484839516
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.96782146938941142518556899326086054242446266902062086757706243369007286985396
Short name T149
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.69 seconds
Started Nov 22 12:36:20 PM PST 23
Finished Nov 22 12:42:07 PM PST 23
Peak memory 237616 kb
Host smart-4dfad52e-60e0-4ee0-a3d7-03197d195f4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96782146938941142518556899326086054242446266902062086757706243369007286985396 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.9678214693894114251855689932608605424244626690206208675770
6243369007286985396
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.73497057041988830520483947354486475723550600905531840417106507483237165199523
Short name T156
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.68 seconds
Started Nov 22 12:36:22 PM PST 23
Finished Nov 22 12:36:49 PM PST 23
Peak memory 211556 kb
Host smart-37d86d77-5aa6-4068-bf23-20f1a30a7428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73497057041988830520483947354486475723550600905531840417106507483237165199523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.rom_ctrl_kmac_err_chk.73497057041988830520483947354486475723550600905531840417106507483237165199523
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.80789192192102463868548125742653601554485327330236252013609652569746497243093
Short name T310
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.48 seconds
Started Nov 22 12:36:31 PM PST 23
Finished Nov 22 12:36:46 PM PST 23
Peak memory 211104 kb
Host smart-3b19a6ba-9f49-4ff5-934e-aee157e80eb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80789192192102463868548125742653601554485327330236252013609652569746497243093 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.80789192192102463868548125742653601554485327330236252013609652569746497243093
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.85864358247977668767744192332552775617955305600376173912497447862604365439707
Short name T28
Test name
Test status
Simulation time 3444857586 ps
CPU time 118.29 seconds
Started Nov 22 12:36:20 PM PST 23
Finished Nov 22 12:38:20 PM PST 23
Peak memory 236624 kb
Host smart-9bbbf8f7-1ab5-4adc-b141-7deb6d78dd46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85864358247977668767744192332552775617955305600376173912497447862604365439707 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.85864358247977668767744192332552775617955305600376173912497447862604365439707
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.74621493207379940010360333186799084173833529504071027130432968320604577459497
Short name T243
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.55 seconds
Started Nov 22 12:36:37 PM PST 23
Finished Nov 22 12:36:51 PM PST 23
Peak memory 211064 kb
Host smart-96e1f26b-081f-4692-b977-423788f09792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74621493207379940010360333186799084173833529504071027130432968320604577459497 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.74621493207379940010360333186799084173833529504071027130432968320604577459497
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.112792405505824271492218064198764284440694003014878248478569315873319733168501
Short name T267
Test name
Test status
Simulation time 69854280986 ps
CPU time 349.34 seconds
Started Nov 22 12:36:48 PM PST 23
Finished Nov 22 12:42:38 PM PST 23
Peak memory 237624 kb
Host smart-4b658c55-d7ac-477a-a3eb-7a5897275a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112792405505824271492218064198764284440694003014878248478569315873319733168501 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.11279240550582427149221806419876428444069400301487824847
8569315873319733168501
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.74571236131261959931128577171943921598946534008454413394999675788148677740582
Short name T305
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.51 seconds
Started Nov 22 12:36:36 PM PST 23
Finished Nov 22 12:37:04 PM PST 23
Peak memory 211492 kb
Host smart-146250f7-b3d4-44d4-9003-845e26f51db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74571236131261959931128577171943921598946534008454413394999675788148677740582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.rom_ctrl_kmac_err_chk.74571236131261959931128577171943921598946534008454413394999675788148677740582
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.100322848790340126486720772122166451236620348306697093380374054410931756309428
Short name T248
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.27 seconds
Started Nov 22 12:36:37 PM PST 23
Finished Nov 22 12:36:52 PM PST 23
Peak memory 211108 kb
Host smart-24b1f677-a1f3-420f-a816-9effe63af3ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100322848790340126486720772122166451236620348306697093380374054410931756309428 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.100322848790340126486720772122166451236620348306697093380374054410931756309428
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.232454524091590606681953015222564117094123041193920440555089952288277076053
Short name T249
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.93 seconds
Started Nov 22 12:36:32 PM PST 23
Finished Nov 22 12:37:02 PM PST 23
Peak memory 212708 kb
Host smart-0f1e7306-c2e6-42f2-9054-eea204026753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232454524091590606681953015222564117094123041193920440555089952288277076053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ba
se_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.rom_ctrl_smoke.232454524091590606681953015222564117094123041193920440555089952288277076053
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.105909361968073073647169945102993800910991494536765130721651167636331309320017
Short name T356
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.44 seconds
Started Nov 22 12:36:33 PM PST 23
Finished Nov 22 12:37:17 PM PST 23
Peak memory 212804 kb
Host smart-d83f94a4-0d24-43bb-87d8-f74098740d02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105909361968073073647169945102993800910991494536765130721651167
636331309320017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.1059093619680730736471699451029938009109914945367
65130721651167636331309320017
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.89714601607385753114981526952733655176932415520656322407064948045970806252088
Short name T329
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.61 seconds
Started Nov 22 12:36:43 PM PST 23
Finished Nov 22 12:42:29 PM PST 23
Peak memory 237620 kb
Host smart-951aed32-eb55-4980-9947-7c61134a1378
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89714601607385753114981526952733655176932415520656322407064948045970806252088 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.897146016073857531149815269527336551769324155206563224070
64948045970806252088
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.48941779133578620266921702276813687133483522908057230469114798789083713299891
Short name T202
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.69 seconds
Started Nov 22 12:36:35 PM PST 23
Finished Nov 22 12:36:50 PM PST 23
Peak memory 211100 kb
Host smart-21e3d83b-3e07-4fb6-becb-bf2f8af1395e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48941779133578620266921702276813687133483522908057230469114798789083713299891 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.48941779133578620266921702276813687133483522908057230469114798789083713299891
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.72807559112134376646605164002288961315160111942579048858511000285067401638462
Short name T276
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.83 seconds
Started Nov 22 12:36:37 PM PST 23
Finished Nov 22 12:37:07 PM PST 23
Peak memory 212772 kb
Host smart-43acdd0a-8eb5-4d0f-8ccd-dadd582f4ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72807559112134376646605164002288961315160111942579048858511000285067401638462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.rom_ctrl_smoke.72807559112134376646605164002288961315160111942579048858511000285067401638462
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.110418611615797589897801327392606141029013230090628771951096557644355009904603
Short name T366
Test name
Test status
Simulation time 9415977006 ps
CPU time 44.18 seconds
Started Nov 22 12:36:35 PM PST 23
Finished Nov 22 12:37:21 PM PST 23
Peak memory 212796 kb
Host smart-6dc0adfa-e8ed-4db1-aeb5-71cd4bb06e79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110418611615797589897801327392606141029013230090628771951096557
644355009904603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.1104186116157975898978013273926061410290132300906
28771951096557644355009904603
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.12110637734505381132422289903766294332172818604724429292425461856760878248148
Short name T183
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.42 seconds
Started Nov 22 12:36:47 PM PST 23
Finished Nov 22 12:37:00 PM PST 23
Peak memory 211084 kb
Host smart-bfd40ce0-28aa-45c3-8501-729c8681455b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12110637734505381132422289903766294332172818604724429292425461856760878248148 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.12110637734505381132422289903766294332172818604724429292425461856760878248148
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.94895674541233430977228946360828396069107018309729353864692257122730506291926
Short name T154
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.65 seconds
Started Nov 22 12:36:50 PM PST 23
Finished Nov 22 12:42:32 PM PST 23
Peak memory 237716 kb
Host smart-927695b9-57c6-48e1-87e4-4e3a2414803d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94895674541233430977228946360828396069107018309729353864692257122730506291926 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.948956745412334309772289463608283960691070183097293538646
92257122730506291926
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.25270828931928184250127041138531438159729691206940681372628943240955266923155
Short name T180
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.16 seconds
Started Nov 22 12:36:36 PM PST 23
Finished Nov 22 12:37:04 PM PST 23
Peak memory 211556 kb
Host smart-4f673e4b-4018-41ed-8db0-efdff4afe8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25270828931928184250127041138531438159729691206940681372628943240955266923155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.rom_ctrl_kmac_err_chk.25270828931928184250127041138531438159729691206940681372628943240955266923155
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.80276053290056073216831924371614812831890445723203797986015492255606283642238
Short name T303
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.67 seconds
Started Nov 22 12:36:45 PM PST 23
Finished Nov 22 12:37:00 PM PST 23
Peak memory 211088 kb
Host smart-1a4f9ce9-7074-4469-8435-6ddf99962a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80276053290056073216831924371614812831890445723203797986015492255606283642238 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.80276053290056073216831924371614812831890445723203797986015492255606283642238
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.113170909939665037532667823041068821661519411359059284934277068582590461017866
Short name T8
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.93 seconds
Started Nov 22 12:36:36 PM PST 23
Finished Nov 22 12:37:06 PM PST 23
Peak memory 212772 kb
Host smart-3553fc1a-6174-4a11-a150-2569a794e64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113170909939665037532667823041068821661519411359059284934277068582590461017866 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.rom_ctrl_smoke.113170909939665037532667823041068821661519411359059284934277068582590461017866
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.65184175378249884710339631767890670968822833620564105406156458570338766935111
Short name T123
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.52 seconds
Started Nov 22 12:36:35 PM PST 23
Finished Nov 22 12:37:20 PM PST 23
Peak memory 212852 kb
Host smart-d2cb8708-529e-45f6-b2f5-06152a8ce814
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651841753782498847103396317678906709688228336205641054061564585
70338766935111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.65184175378249884710339631767890670968822833620564
105406156458570338766935111
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.100415227954411306826503226457361185791610200077858168885958807147049980553998
Short name T1
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Nov 22 12:36:39 PM PST 23
Finished Nov 22 12:36:53 PM PST 23
Peak memory 211064 kb
Host smart-f79e1fef-fae7-46a2-bb11-18e0d9f5408f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100415227954411306826503226457361185791610200077858168885958807147049980553998 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.100415227954411306826503226457361185791610200077858168885958807147049980553998
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3321827575296243544483149301156546190566518255376151168276023454196651398310
Short name T266
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.94 seconds
Started Nov 22 12:36:38 PM PST 23
Finished Nov 22 12:42:23 PM PST 23
Peak memory 237588 kb
Host smart-9a3c68bb-4dd1-49f4-a231-f520059d1963
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321827575296243544483149301156546190566518255376151168276023454196651398310 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.3321827575296243544483149301156546190566518255376151168276
023454196651398310
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.92048691887243325705539936585257661884314500118548760447318749850215446533089
Short name T251
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.77 seconds
Started Nov 22 12:36:45 PM PST 23
Finished Nov 22 12:37:22 PM PST 23
Peak memory 211520 kb
Host smart-24eb294f-6899-4244-a1df-5c2794e23772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92048691887243325705539936585257661884314500118548760447318749850215446533089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.rom_ctrl_kmac_err_chk.92048691887243325705539936585257661884314500118548760447318749850215446533089
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.34324793553783286271778146291185005006313627931317634458746947923710183812198
Short name T177
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.44 seconds
Started Nov 22 12:36:37 PM PST 23
Finished Nov 22 12:37:07 PM PST 23
Peak memory 212772 kb
Host smart-9b717e2e-dcc8-4538-8058-68da68e1ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34324793553783286271778146291185005006313627931317634458746947923710183812198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.rom_ctrl_smoke.34324793553783286271778146291185005006313627931317634458746947923710183812198
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.42072887068067049984960218370702931689915341613887472765426757855034731990383
Short name T190
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.74 seconds
Started Nov 22 12:36:35 PM PST 23
Finished Nov 22 12:37:19 PM PST 23
Peak memory 212816 kb
Host smart-dfc18924-b647-492f-b902-7eaefb7a3de4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420728870680670499849602183707029316899153416138874727654267578
55034731990383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.42072887068067049984960218370702931689915341613887
472765426757855034731990383
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.16576232769669707996757894642665453439997521604223789351099877501767744342461
Short name T110
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.53 seconds
Started Nov 22 12:36:49 PM PST 23
Finished Nov 22 12:37:03 PM PST 23
Peak memory 211112 kb
Host smart-55fd9282-fca1-445f-b324-426ea4efff6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16576232769669707996757894642665453439997521604223789351099877501767744342461 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.16576232769669707996757894642665453439997521604223789351099877501767744342461
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.12913729555140575075766488011036149010700206250098979338333855788727635432911
Short name T147
Test name
Test status
Simulation time 69854280986 ps
CPU time 352.35 seconds
Started Nov 22 12:36:40 PM PST 23
Finished Nov 22 12:42:33 PM PST 23
Peak memory 237664 kb
Host smart-48fccfe4-d02e-41dc-b78d-5d9eda7c8de0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12913729555140575075766488011036149010700206250098979338333855788727635432911 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.129137295551405750757664880110361490107002062500989793383
33855788727635432911
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.56538156509399240434255177841639513070158881032416399515996278236665656920489
Short name T321
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.29 seconds
Started Nov 22 12:36:49 PM PST 23
Finished Nov 22 12:37:16 PM PST 23
Peak memory 211528 kb
Host smart-dbcbee7d-4295-4fe8-ae1f-01f325a6762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56538156509399240434255177841639513070158881032416399515996278236665656920489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.rom_ctrl_kmac_err_chk.56538156509399240434255177841639513070158881032416399515996278236665656920489
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.40381475771079245293134931787699846325893833772676430693548209417503468480108
Short name T286
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.66 seconds
Started Nov 22 12:36:48 PM PST 23
Finished Nov 22 12:37:03 PM PST 23
Peak memory 211088 kb
Host smart-584064fb-81fb-4148-9f06-53e910d3b32b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40381475771079245293134931787699846325893833772676430693548209417503468480108 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.40381475771079245293134931787699846325893833772676430693548209417503468480108
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.9033127593179006282737460368208294277685091214032990179875818388016555627522
Short name T174
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.35 seconds
Started Nov 22 12:36:38 PM PST 23
Finished Nov 22 12:37:08 PM PST 23
Peak memory 212712 kb
Host smart-5fe98fd3-2157-4644-8422-734a650c9f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9033127593179006282737460368208294277685091214032990179875818388016555627522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.rom_ctrl_smoke.9033127593179006282737460368208294277685091214032990179875818388016555627522
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.70712908628828741114032258744763354285547997855391797026528677403092944616317
Short name T182
Test name
Test status
Simulation time 9415977006 ps
CPU time 44.51 seconds
Started Nov 22 12:36:37 PM PST 23
Finished Nov 22 12:37:23 PM PST 23
Peak memory 212816 kb
Host smart-93a9110f-44ef-4d06-a3fb-3fef5ed0eb46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707129086288287411140322587447633542855479978553917970265286774
03092944616317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.70712908628828741114032258744763354285547997855391
797026528677403092944616317
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.55252825394360401247219546253888942021129765564240419814733016180957579079012
Short name T292
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.43 seconds
Started Nov 22 12:36:48 PM PST 23
Finished Nov 22 12:37:02 PM PST 23
Peak memory 211096 kb
Host smart-a3611c5c-1900-45d8-94e1-a29ef19da1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55252825394360401247219546253888942021129765564240419814733016180957579079012 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.55252825394360401247219546253888942021129765564240419814733016180957579079012
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.91436991107678241750638871312359009572547570108851107974496900772567903094099
Short name T273
Test name
Test status
Simulation time 69854280986 ps
CPU time 352.94 seconds
Started Nov 22 12:36:49 PM PST 23
Finished Nov 22 12:42:43 PM PST 23
Peak memory 237652 kb
Host smart-0f22c015-e300-416d-89ff-9fd14c5eb6df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91436991107678241750638871312359009572547570108851107974496900772567903094099 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.914369911076782417506388713123590095725475701088511079744
96900772567903094099
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.22415851034284279864303198224156664429190933507037120035569993969250098309835
Short name T219
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.61 seconds
Started Nov 22 12:36:57 PM PST 23
Finished Nov 22 12:37:25 PM PST 23
Peak memory 211528 kb
Host smart-be774347-7d7d-4365-8bf5-515285dbaf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22415851034284279864303198224156664429190933507037120035569993969250098309835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.rom_ctrl_kmac_err_chk.22415851034284279864303198224156664429190933507037120035569993969250098309835
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.31351247200745337944935968553250468193900185999284570198279205087596727765869
Short name T175
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.29 seconds
Started Nov 22 12:36:47 PM PST 23
Finished Nov 22 12:37:01 PM PST 23
Peak memory 210988 kb
Host smart-29c188f7-21dc-4316-b74a-aa2c63c10df3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31351247200745337944935968553250468193900185999284570198279205087596727765869 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.31351247200745337944935968553250468193900185999284570198279205087596727765869
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.91012514833968769193190980918834481008927900123907187921208029931390149846089
Short name T169
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.21 seconds
Started Nov 22 12:36:40 PM PST 23
Finished Nov 22 12:37:10 PM PST 23
Peak memory 212828 kb
Host smart-4023bf10-19f4-4bf9-b231-1f50ba95e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91012514833968769193190980918834481008927900123907187921208029931390149846089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.rom_ctrl_smoke.91012514833968769193190980918834481008927900123907187921208029931390149846089
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.70691527484340752560566611464838425358718917550345299636154208463042846622678
Short name T3
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.24 seconds
Started Nov 22 12:36:40 PM PST 23
Finished Nov 22 12:37:24 PM PST 23
Peak memory 212932 kb
Host smart-e34b1a40-16ee-407a-908a-e7850a719a13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706915274843407525605666114648384253587189175503452996361542084
63042846622678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.70691527484340752560566611464838425358718917550345
299636154208463042846622678
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.66172051169975876062737124811781243718198333274717012424866083450630960924630
Short name T355
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.63 seconds
Started Nov 22 12:36:43 PM PST 23
Finished Nov 22 12:36:58 PM PST 23
Peak memory 211076 kb
Host smart-e72959a4-ee87-454d-8992-4b61d69cf798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66172051169975876062737124811781243718198333274717012424866083450630960924630 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.66172051169975876062737124811781243718198333274717012424866083450630960924630
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.74429717107224668569207801095247482108279071527627097045255154887053759614355
Short name T47
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.41 seconds
Started Nov 22 12:36:57 PM PST 23
Finished Nov 22 12:42:45 PM PST 23
Peak memory 237600 kb
Host smart-f29c24ad-21a3-4827-beab-0d84ad6d568b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74429717107224668569207801095247482108279071527627097045255154887053759614355 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.744297171072246685692078010952474821082790715276270970452
55154887053759614355
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.92711128587036722501282339764964601796265946891654408381726003223952841618704
Short name T109
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.46 seconds
Started Nov 22 12:36:50 PM PST 23
Finished Nov 22 12:37:16 PM PST 23
Peak memory 211500 kb
Host smart-9a6d231e-646f-4a8a-8623-a88eb4674df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92711128587036722501282339764964601796265946891654408381726003223952841618704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.rom_ctrl_kmac_err_chk.92711128587036722501282339764964601796265946891654408381726003223952841618704
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.95400092786164942229488385817123592659347855752876520770737025299827557375024
Short name T192
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.07 seconds
Started Nov 22 12:36:50 PM PST 23
Finished Nov 22 12:37:04 PM PST 23
Peak memory 211112 kb
Host smart-3c6b1d02-36e5-47c6-a7f1-c4d7c5e66b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95400092786164942229488385817123592659347855752876520770737025299827557375024 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.95400092786164942229488385817123592659347855752876520770737025299827557375024
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.71333258437295544365997119192961105906305868705291475401778440696913923898954
Short name T38
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.1 seconds
Started Nov 22 12:36:48 PM PST 23
Finished Nov 22 12:37:18 PM PST 23
Peak memory 212760 kb
Host smart-0a1f6efc-e43f-4d46-8dea-3e936ca8b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71333258437295544365997119192961105906305868705291475401778440696913923898954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.rom_ctrl_smoke.71333258437295544365997119192961105906305868705291475401778440696913923898954
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.114051453750958116049518421212914695180447378807434602176747847427219753985237
Short name T193
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.46 seconds
Started Nov 22 12:36:50 PM PST 23
Finished Nov 22 12:37:35 PM PST 23
Peak memory 212848 kb
Host smart-31636a71-8009-4a85-9a53-1d5d683bc595
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114051453750958116049518421212914695180447378807434602176747847
427219753985237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.1140514537509581160495184212129146951804473788074
34602176747847427219753985237
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.74223387544938272598043027961179680772031808729833491726459531717694198802870
Short name T118
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.38 seconds
Started Nov 22 12:36:50 PM PST 23
Finished Nov 22 12:37:04 PM PST 23
Peak memory 211024 kb
Host smart-194c1c35-5576-4908-b965-65321093ca0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74223387544938272598043027961179680772031808729833491726459531717694198802870 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.74223387544938272598043027961179680772031808729833491726459531717694198802870
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.79734259244792852523498084172007356605159000418505996421483123639480863850340
Short name T205
Test name
Test status
Simulation time 69854280986 ps
CPU time 348.18 seconds
Started Nov 22 12:36:50 PM PST 23
Finished Nov 22 12:42:40 PM PST 23
Peak memory 237700 kb
Host smart-69f4ed82-3160-4398-9c9d-22c98f69916e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79734259244792852523498084172007356605159000418505996421483123639480863850340 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.797342592447928525234980841720073566051590004185059964214
83123639480863850340
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.25202634259209952114109608333163767413043839558296189993541244143650482068483
Short name T128
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.39 seconds
Started Nov 22 12:36:42 PM PST 23
Finished Nov 22 12:37:09 PM PST 23
Peak memory 211552 kb
Host smart-859e06e4-72ca-46b9-b96e-67987ab2617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25202634259209952114109608333163767413043839558296189993541244143650482068483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.rom_ctrl_kmac_err_chk.25202634259209952114109608333163767413043839558296189993541244143650482068483
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.41061112464966179766357154172500303843341641305822027778397145504731654620890
Short name T36
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.5 seconds
Started Nov 22 12:36:51 PM PST 23
Finished Nov 22 12:37:06 PM PST 23
Peak memory 211080 kb
Host smart-2f494323-250e-42f6-9fe8-68755c01ecd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41061112464966179766357154172500303843341641305822027778397145504731654620890 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.41061112464966179766357154172500303843341641305822027778397145504731654620890
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.84474329203903679576704933634153095968715738295934580769072491568643106458084
Short name T95
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.58 seconds
Started Nov 22 12:36:46 PM PST 23
Finished Nov 22 12:37:16 PM PST 23
Peak memory 212748 kb
Host smart-c0cc7c49-2272-45b1-b987-8b7cff0f704e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84474329203903679576704933634153095968715738295934580769072491568643106458084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.rom_ctrl_smoke.84474329203903679576704933634153095968715738295934580769072491568643106458084
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.81989473284221955290244567103328317192804991929068324108931947575178009502412
Short name T304
Test name
Test status
Simulation time 9415977006 ps
CPU time 44.4 seconds
Started Nov 22 12:36:45 PM PST 23
Finished Nov 22 12:37:31 PM PST 23
Peak memory 212816 kb
Host smart-b1a92211-ed71-4687-8aa2-c21351e75d34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819894732842219552902445671033283171928049919290683241089319475
75178009502412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.81989473284221955290244567103328317192804991929068
324108931947575178009502412
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.47637417954576547143489443698219356428553679825699461731119296289330476573383
Short name T306
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.03 seconds
Started Nov 22 12:37:00 PM PST 23
Finished Nov 22 12:37:14 PM PST 23
Peak memory 211096 kb
Host smart-70401e5d-3bc0-4ec3-bbd7-c221bc6ce0de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47637417954576547143489443698219356428553679825699461731119296289330476573383 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.47637417954576547143489443698219356428553679825699461731119296289330476573383
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.23250456348470665357253396295134382969899919288848268860605488623557132587118
Short name T315
Test name
Test status
Simulation time 69854280986 ps
CPU time 349.45 seconds
Started Nov 22 12:37:01 PM PST 23
Finished Nov 22 12:42:53 PM PST 23
Peak memory 237616 kb
Host smart-ba105fb2-3d54-4603-a554-39dc3ff931e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23250456348470665357253396295134382969899919288848268860605488623557132587118 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.232504563484706653572533962951343829698999192888482688606
05488623557132587118
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.90577739917244300843057552694383602043362883740582566770693536648584824935541
Short name T278
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.63 seconds
Started Nov 22 12:37:00 PM PST 23
Finished Nov 22 12:37:27 PM PST 23
Peak memory 211528 kb
Host smart-de2de343-2998-4783-b525-c5fb5e258496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90577739917244300843057552694383602043362883740582566770693536648584824935541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.rom_ctrl_kmac_err_chk.90577739917244300843057552694383602043362883740582566770693536648584824935541
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.54152506383103866587436968449599014538665428894749924466028324394929939337396
Short name T288
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.65 seconds
Started Nov 22 12:37:13 PM PST 23
Finished Nov 22 12:37:34 PM PST 23
Peak memory 211092 kb
Host smart-b01346b9-6c22-4f94-b8d2-1c99a0e77826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54152506383103866587436968449599014538665428894749924466028324394929939337396 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.54152506383103866587436968449599014538665428894749924466028324394929939337396
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.72543357515460250939373843575798442017875677450545112160058994589846844851715
Short name T176
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.93 seconds
Started Nov 22 12:36:49 PM PST 23
Finished Nov 22 12:37:19 PM PST 23
Peak memory 212728 kb
Host smart-2ab08935-fe94-4c74-b381-3f1c9b788389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72543357515460250939373843575798442017875677450545112160058994589846844851715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.rom_ctrl_smoke.72543357515460250939373843575798442017875677450545112160058994589846844851715
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.12635392804341598272844542512535118415954467168457794210728012685241977423076
Short name T178
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.7 seconds
Started Nov 22 12:37:01 PM PST 23
Finished Nov 22 12:37:46 PM PST 23
Peak memory 212872 kb
Host smart-5f5fbceb-59ed-4c99-ae4a-d2d3001c3009
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126353928043415982728445425125351184159544671684577942107280126
85241977423076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.12635392804341598272844542512535118415954467168457
794210728012685241977423076
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.35701396468797087439328957810072981826230168841561882453472107112192918196663
Short name T116
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.38 seconds
Started Nov 22 12:37:10 PM PST 23
Finished Nov 22 12:37:31 PM PST 23
Peak memory 211100 kb
Host smart-39f3b901-90a1-4485-b881-82dae635ad3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35701396468797087439328957810072981826230168841561882453472107112192918196663 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.35701396468797087439328957810072981826230168841561882453472107112192918196663
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.101837963735018694240242265857041811758317878949705607550644800740626616413914
Short name T113
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.83 seconds
Started Nov 22 12:36:55 PM PST 23
Finished Nov 22 12:37:22 PM PST 23
Peak memory 211448 kb
Host smart-bd7bdbc7-199c-440e-88d9-e888c0f6c337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101837963735018694240242265857041811758317878949705607550644800740626616413914 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.rom_ctrl_kmac_err_chk.101837963735018694240242265857041811758317878949705607550644800740626616413914
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.78263130557305143065752938908594372670608672319877593311864739024938525304046
Short name T140
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.33 seconds
Started Nov 22 12:36:52 PM PST 23
Finished Nov 22 12:37:07 PM PST 23
Peak memory 211100 kb
Host smart-ad3e2ab5-6e59-4762-8a22-3b49262b0b42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78263130557305143065752938908594372670608672319877593311864739024938525304046 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.78263130557305143065752938908594372670608672319877593311864739024938525304046
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3919483687022618897713912788613806092935733584875565441530405599195893134896
Short name T96
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.92 seconds
Started Nov 22 12:36:47 PM PST 23
Finished Nov 22 12:37:17 PM PST 23
Peak memory 212700 kb
Host smart-c2ad08f7-fc22-4bcd-9a90-ccda77045949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919483687022618897713912788613806092935733584875565441530405599195893134896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.rom_ctrl_smoke.3919483687022618897713912788613806092935733584875565441530405599195893134896
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.87838541671328719259618223925680045513941357688885186782851249047956013322214
Short name T346
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.91 seconds
Started Nov 22 12:36:43 PM PST 23
Finished Nov 22 12:37:29 PM PST 23
Peak memory 212828 kb
Host smart-5bd3d958-1fb5-4e7b-a953-61d5b85295a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878385416713287192596182239256800455139413576888851867828512490
47956013322214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.87838541671328719259618223925680045513941357688885
186782851249047956013322214
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3097397562539207311844821458773152742644451569771019229964551071765973185627
Short name T207
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.54 seconds
Started Nov 22 12:36:23 PM PST 23
Finished Nov 22 12:36:37 PM PST 23
Peak memory 211156 kb
Host smart-2ec8c834-4610-43b1-9d70-d72952b69f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097397562539207311844821458773152742644451569771019229964551071765973185627 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3097397562539207311844821458773152742644451569771019229964551071765973185627
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.8294078859458523635308633947862951352921868141883469545863636974090076157481
Short name T238
Test name
Test status
Simulation time 69854280986 ps
CPU time 351.33 seconds
Started Nov 22 12:36:26 PM PST 23
Finished Nov 22 12:42:19 PM PST 23
Peak memory 237592 kb
Host smart-6c9eba37-accf-496c-9f3f-6cc1df98d877
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8294078859458523635308633947862951352921868141883469545863636974090076157481 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.82940788594585236353086339478629513529218681418834695458636
36974090076157481
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.102597973581121327212545522400388001502846280059755220838374452712712416916907
Short name T133
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.26 seconds
Started Nov 22 12:36:24 PM PST 23
Finished Nov 22 12:36:51 PM PST 23
Peak memory 211504 kb
Host smart-a2946d09-95b7-4cae-ab7a-a7bb012f4ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102597973581121327212545522400388001502846280059755220838374452712712416916907 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.rom_ctrl_kmac_err_chk.102597973581121327212545522400388001502846280059755220838374452712712416916907
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.53882481127413838647660391676642122820845710676412815088847580248865261930564
Short name T148
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.29 seconds
Started Nov 22 12:36:23 PM PST 23
Finished Nov 22 12:36:37 PM PST 23
Peak memory 211076 kb
Host smart-36d68f03-d6aa-44fc-a823-aa256b9beb05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53882481127413838647660391676642122820845710676412815088847580248865261930564 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.53882481127413838647660391676642122820845710676412815088847580248865261930564
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.58051439570455269130579882294238392848366422840890097405975792667779387610596
Short name T34
Test name
Test status
Simulation time 3444857586 ps
CPU time 118.24 seconds
Started Nov 22 12:36:25 PM PST 23
Finished Nov 22 12:38:25 PM PST 23
Peak memory 236676 kb
Host smart-54411aea-f2d7-43b1-932d-e9728c6f4949
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58051439570455269130579882294238392848366422840890097405975792667779387610596 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.58051439570455269130579882294238392848366422840890097405975792667779387610596
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.92669762964073432021118244903666266397609170405470462793779188643026025289851
Short name T313
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.58 seconds
Started Nov 22 12:36:21 PM PST 23
Finished Nov 22 12:36:51 PM PST 23
Peak memory 212720 kb
Host smart-c78d1fd0-806b-46a2-9df1-cfe64452f68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92669762964073432021118244903666266397609170405470462793779188643026025289851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.rom_ctrl_smoke.92669762964073432021118244903666266397609170405470462793779188643026025289851
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.19520699078304829460465388770551090733234459196866015464699983558458100430317
Short name T13
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.86 seconds
Started Nov 22 12:36:24 PM PST 23
Finished Nov 22 12:37:09 PM PST 23
Peak memory 212872 kb
Host smart-7f854a16-5099-4d18-852f-a794804038a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195206990783048294604653887705510907332344591968660154646999835
58458100430317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.195206990783048294604653887705510907332344591968660
15464699983558458100430317
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.30009906909454553830164926714208668875415586987529230253777905472212160706234
Short name T256
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.52 seconds
Started Nov 22 12:36:51 PM PST 23
Finished Nov 22 12:37:05 PM PST 23
Peak memory 211100 kb
Host smart-d58af159-035b-4338-8f31-6358ebef7997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30009906909454553830164926714208668875415586987529230253777905472212160706234 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.30009906909454553830164926714208668875415586987529230253777905472212160706234
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.45821477867142779016695480148240303721131807873163941527905975907572537807805
Short name T159
Test name
Test status
Simulation time 69854280986 ps
CPU time 350.34 seconds
Started Nov 22 12:36:56 PM PST 23
Finished Nov 22 12:42:49 PM PST 23
Peak memory 237636 kb
Host smart-833b4ef1-351b-45f5-b786-fbfdf7429be9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45821477867142779016695480148240303721131807873163941527905975907572537807805 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.458214778671427790166954801482403037211318078731639415279
05975907572537807805
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.71317437706364555379222220087726570383229421376427134124117766432806626117323
Short name T212
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.75 seconds
Started Nov 22 12:36:49 PM PST 23
Finished Nov 22 12:37:16 PM PST 23
Peak memory 211548 kb
Host smart-34549141-06ef-4db2-8f78-605ba46f7732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71317437706364555379222220087726570383229421376427134124117766432806626117323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.rom_ctrl_kmac_err_chk.71317437706364555379222220087726570383229421376427134124117766432806626117323
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.61246676376174008863986718553183384224027314121759924050720846768559041750666
Short name T307
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.26 seconds
Started Nov 22 12:36:48 PM PST 23
Finished Nov 22 12:37:03 PM PST 23
Peak memory 211112 kb
Host smart-66672d7d-e12e-451d-bac8-ca490fc7570d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61246676376174008863986718553183384224027314121759924050720846768559041750666 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.61246676376174008863986718553183384224027314121759924050720846768559041750666
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.104516838628039707514188473164517233364751986594520468525044149174519718181272
Short name T145
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.87 seconds
Started Nov 22 12:37:00 PM PST 23
Finished Nov 22 12:37:30 PM PST 23
Peak memory 212760 kb
Host smart-9a232671-0d88-46b8-8af0-c0fcc35c3eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104516838628039707514188473164517233364751986594520468525044149174519718181272 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.rom_ctrl_smoke.104516838628039707514188473164517233364751986594520468525044149174519718181272
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.64921106248753009757300675080532005255451099743987885540730112043759327520628
Short name T317
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.5 seconds
Started Nov 22 12:36:45 PM PST 23
Finished Nov 22 12:37:30 PM PST 23
Peak memory 212852 kb
Host smart-316a674c-79f7-471d-a765-9d3d5d8a9bd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649211062487530097573006750805320052554510997439878855407301120
43759327520628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.64921106248753009757300675080532005255451099743987
885540730112043759327520628
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.24503661791575449046121110504662212761895287991232267001660483836141061038237
Short name T111
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.06 seconds
Started Nov 22 12:37:00 PM PST 23
Finished Nov 22 12:37:14 PM PST 23
Peak memory 211096 kb
Host smart-01ead6a0-4ab1-45fc-ba5d-ba9bd5a0e93c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24503661791575449046121110504662212761895287991232267001660483836141061038237 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.24503661791575449046121110504662212761895287991232267001660483836141061038237
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.36734444774341568013038768921919380027346545107275772142882546905809752832418
Short name T173
Test name
Test status
Simulation time 69854280986 ps
CPU time 351.3 seconds
Started Nov 22 12:36:48 PM PST 23
Finished Nov 22 12:42:40 PM PST 23
Peak memory 237552 kb
Host smart-64bfd38b-eee0-400d-83d0-5474e5de6bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36734444774341568013038768921919380027346545107275772142882546905809752832418 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.367344447743415680130387689219193800273465451072757721428
82546905809752832418
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.12224588578471549260689524324335256725998353948341689861879599292349321032385
Short name T236
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.15 seconds
Started Nov 22 12:36:52 PM PST 23
Finished Nov 22 12:37:20 PM PST 23
Peak memory 211496 kb
Host smart-41d5ea4f-8c6d-481c-b272-23a2ef8a5c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12224588578471549260689524324335256725998353948341689861879599292349321032385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.rom_ctrl_kmac_err_chk.12224588578471549260689524324335256725998353948341689861879599292349321032385
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.83848866768243355757467721377301456989434472799291945105167262983793043379660
Short name T311
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.77 seconds
Started Nov 22 12:37:00 PM PST 23
Finished Nov 22 12:37:16 PM PST 23
Peak memory 211180 kb
Host smart-d33bf647-fb8d-4096-8771-c4aad9a551ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83848866768243355757467721377301456989434472799291945105167262983793043379660 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.83848866768243355757467721377301456989434472799291945105167262983793043379660
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.68568593757318226171817781910852755200033617158880773165520561198611713201530
Short name T222
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.24 seconds
Started Nov 22 12:36:50 PM PST 23
Finished Nov 22 12:37:21 PM PST 23
Peak memory 212632 kb
Host smart-f7155744-c1f3-429c-aa6f-25ae370e05c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68568593757318226171817781910852755200033617158880773165520561198611713201530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.rom_ctrl_smoke.68568593757318226171817781910852755200033617158880773165520561198611713201530
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.99713653410235411700462834307533415565093771518768568995315534797357439310360
Short name T358
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.15 seconds
Started Nov 22 12:36:51 PM PST 23
Finished Nov 22 12:37:35 PM PST 23
Peak memory 212856 kb
Host smart-158db1ee-0a1d-4136-a13f-45acb381f956
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997136534102354117004628343075334155650937715187685689953155347
97357439310360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.99713653410235411700462834307533415565093771518768
568995315534797357439310360
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.77315817663023120167080735977991912978521660261287709158380492921824996372398
Short name T198
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Nov 22 12:36:58 PM PST 23
Finished Nov 22 12:37:12 PM PST 23
Peak memory 211080 kb
Host smart-0def7a43-e317-4558-9b70-637ee8f60c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77315817663023120167080735977991912978521660261287709158380492921824996372398 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.77315817663023120167080735977991912978521660261287709158380492921824996372398
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.74570437603743160308373898978975691340337315658817491682533173143562426363559
Short name T35
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.93 seconds
Started Nov 22 12:36:59 PM PST 23
Finished Nov 22 12:42:47 PM PST 23
Peak memory 237616 kb
Host smart-f35e5932-abb2-4193-b7f3-f51225199136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74570437603743160308373898978975691340337315658817491682533173143562426363559 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.745704376037431603083738989789756913403373156588174916825
33173143562426363559
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.19328915015896076743466856184025628909240431547282449563754334863825045782829
Short name T272
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.8 seconds
Started Nov 22 12:37:05 PM PST 23
Finished Nov 22 12:37:34 PM PST 23
Peak memory 211532 kb
Host smart-710927f8-ae06-42f4-b1c1-8dd7338458f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19328915015896076743466856184025628909240431547282449563754334863825045782829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.rom_ctrl_kmac_err_chk.19328915015896076743466856184025628909240431547282449563754334863825045782829
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.20776523827444207412186219831604258940966380303597366573954152733594551074799
Short name T259
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.44 seconds
Started Nov 22 12:36:57 PM PST 23
Finished Nov 22 12:37:13 PM PST 23
Peak memory 210436 kb
Host smart-f04bc874-5c02-4451-b7c7-df1b38c756a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20776523827444207412186219831604258940966380303597366573954152733594551074799 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.20776523827444207412186219831604258940966380303597366573954152733594551074799
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.34823968077978279516916913837590977607761187409228143438183646633027513326409
Short name T294
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.22 seconds
Started Nov 22 12:36:47 PM PST 23
Finished Nov 22 12:37:17 PM PST 23
Peak memory 212716 kb
Host smart-ed26a5b5-7e7d-470d-89aa-769c054930bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34823968077978279516916913837590977607761187409228143438183646633027513326409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.rom_ctrl_smoke.34823968077978279516916913837590977607761187409228143438183646633027513326409
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.50627322648656368417053874321380715570256555185966908839013100942972600645973
Short name T229
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.6 seconds
Started Nov 22 12:36:53 PM PST 23
Finished Nov 22 12:37:38 PM PST 23
Peak memory 212852 kb
Host smart-5f5322b7-62e0-44dd-bcf7-e5085bd84ed7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506273226486563684170538743213807155702565551859669088390131009
42972600645973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.50627322648656368417053874321380715570256555185966
908839013100942972600645973
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.80204918547105832459050092142157613156689286561888099678764086182696558289456
Short name T262
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.68 seconds
Started Nov 22 12:37:15 PM PST 23
Finished Nov 22 12:37:33 PM PST 23
Peak memory 211124 kb
Host smart-5dfc37eb-e36c-4a6c-9da5-20d306ef4698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80204918547105832459050092142157613156689286561888099678764086182696558289456 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.80204918547105832459050092142157613156689286561888099678764086182696558289456
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.59570376332381756755236266218324946341486179080767425602475767410201459532753
Short name T250
Test name
Test status
Simulation time 69854280986 ps
CPU time 348.41 seconds
Started Nov 22 12:36:56 PM PST 23
Finished Nov 22 12:42:45 PM PST 23
Peak memory 237696 kb
Host smart-56094708-2f41-4b60-83a1-e9301efdd7a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59570376332381756755236266218324946341486179080767425602475767410201459532753 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.595703763323817567552362662183249463414861790807674256024
75767410201459532753
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.34714166858616264617333633618206564783413482801172433781221385903667571670374
Short name T350
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.57 seconds
Started Nov 22 12:37:01 PM PST 23
Finished Nov 22 12:37:29 PM PST 23
Peak memory 211548 kb
Host smart-97c53238-ec44-41f8-bc1a-eebf45c924e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34714166858616264617333633618206564783413482801172433781221385903667571670374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.rom_ctrl_kmac_err_chk.34714166858616264617333633618206564783413482801172433781221385903667571670374
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.88825172159592705833376561170726708286406644439809978667686725629545093546703
Short name T316
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.23 seconds
Started Nov 22 12:36:51 PM PST 23
Finished Nov 22 12:37:05 PM PST 23
Peak memory 211076 kb
Host smart-f5f57e68-73fe-4c77-896f-b7473610d64e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88825172159592705833376561170726708286406644439809978667686725629545093546703 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.88825172159592705833376561170726708286406644439809978667686725629545093546703
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.43200309806922956718950575190084176404522258188301204338767674177245191902908
Short name T324
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.36 seconds
Started Nov 22 12:36:50 PM PST 23
Finished Nov 22 12:37:20 PM PST 23
Peak memory 212720 kb
Host smart-c592c967-0848-42fc-ad24-66f695c4fc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43200309806922956718950575190084176404522258188301204338767674177245191902908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.rom_ctrl_smoke.43200309806922956718950575190084176404522258188301204338767674177245191902908
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.49826085648835508885762671386860097595061138269544942478069525146968559948563
Short name T331
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.73 seconds
Started Nov 22 12:36:51 PM PST 23
Finished Nov 22 12:37:36 PM PST 23
Peak memory 212840 kb
Host smart-a47eff5d-1595-4b8a-a337-ab5ad872b5fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498260856488355088857626713868600975950611382695449424780695251
46968559948563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.49826085648835508885762671386860097595061138269544
942478069525146968559948563
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.30384998949453330358347917160141401250654595817535438174784972566391107571569
Short name T187
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.81 seconds
Started Nov 22 12:37:05 PM PST 23
Finished Nov 22 12:37:19 PM PST 23
Peak memory 211040 kb
Host smart-15d9977f-c6fd-4436-bb73-0fbaa8f7265a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30384998949453330358347917160141401250654595817535438174784972566391107571569 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.30384998949453330358347917160141401250654595817535438174784972566391107571569
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.32507463875853091578529053216539472557267423478995906544262827802538336994621
Short name T43
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.37 seconds
Started Nov 22 12:37:07 PM PST 23
Finished Nov 22 12:42:56 PM PST 23
Peak memory 237700 kb
Host smart-49fc32be-1846-44d9-8662-5c4d22db9aa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32507463875853091578529053216539472557267423478995906544262827802538336994621 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.325074638758530915785290532165394725572674234789959065442
62827802538336994621
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.47943341112248881831312849279747364696960909715201515489791245009285763769479
Short name T237
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.58 seconds
Started Nov 22 12:37:16 PM PST 23
Finished Nov 22 12:37:46 PM PST 23
Peak memory 211552 kb
Host smart-1139c8a5-1636-44d4-98cc-4da55d9217ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47943341112248881831312849279747364696960909715201515489791245009285763769479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.rom_ctrl_kmac_err_chk.47943341112248881831312849279747364696960909715201515489791245009285763769479
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.86675550659473755789857730985626047048209447860609373332870332413753086539172
Short name T354
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.36 seconds
Started Nov 22 12:37:02 PM PST 23
Finished Nov 22 12:37:17 PM PST 23
Peak memory 211180 kb
Host smart-72c0d681-487e-4ed8-83c2-dd430daa6782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86675550659473755789857730985626047048209447860609373332870332413753086539172 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.86675550659473755789857730985626047048209447860609373332870332413753086539172
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.10562338021262393800202990955730255812584165748764162364598930309749690599489
Short name T157
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.41 seconds
Started Nov 22 12:37:00 PM PST 23
Finished Nov 22 12:37:30 PM PST 23
Peak memory 212860 kb
Host smart-9928718b-dba7-48c3-8ac2-a5fb1087617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10562338021262393800202990955730255812584165748764162364598930309749690599489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.rom_ctrl_smoke.10562338021262393800202990955730255812584165748764162364598930309749690599489
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.92072253176016812429421482147961742366243602687326952701095747856818856662407
Short name T153
Test name
Test status
Simulation time 9415977006 ps
CPU time 43 seconds
Started Nov 22 12:36:58 PM PST 23
Finished Nov 22 12:37:43 PM PST 23
Peak memory 212896 kb
Host smart-c8991e84-6036-407a-a9ab-63b44e5f3454
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920722531760168124294214821479617423662436026873269527010957478
56818856662407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.92072253176016812429421482147961742366243602687326
952701095747856818856662407
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.46040754335652089884405418483873520688835681582511404607337155295210443374874
Short name T14
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.89 seconds
Started Nov 22 12:37:07 PM PST 23
Finished Nov 22 12:37:23 PM PST 23
Peak memory 211000 kb
Host smart-a3fe5732-95ce-48c7-8e7d-8fab956d387e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46040754335652089884405418483873520688835681582511404607337155295210443374874 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.46040754335652089884405418483873520688835681582511404607337155295210443374874
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.14068385045112003299908240835114445560182277171915399493119735360157987866416
Short name T239
Test name
Test status
Simulation time 69854280986 ps
CPU time 350.4 seconds
Started Nov 22 12:37:08 PM PST 23
Finished Nov 22 12:43:01 PM PST 23
Peak memory 237632 kb
Host smart-83dcc24e-a61e-4d6a-961b-503568fb0946
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14068385045112003299908240835114445560182277171915399493119735360157987866416 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.140683850451120032999082408351144455601822771719153994931
19735360157987866416
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.35278605230252381511607981656903034445319355214598672432839970631996389581228
Short name T141
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.63 seconds
Started Nov 22 12:37:03 PM PST 23
Finished Nov 22 12:37:30 PM PST 23
Peak memory 211508 kb
Host smart-1dc04f0a-94ab-4ba6-be29-4f53465c86aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35278605230252381511607981656903034445319355214598672432839970631996389581228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.rom_ctrl_kmac_err_chk.35278605230252381511607981656903034445319355214598672432839970631996389581228
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3208130115546636085769178431212374629946288475799044192071297458065151859959
Short name T131
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.52 seconds
Started Nov 22 12:37:05 PM PST 23
Finished Nov 22 12:37:20 PM PST 23
Peak memory 211100 kb
Host smart-0c3b5df7-2cca-4b15-9b71-0324e9cda510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208130115546636085769178431212374629946288475799044192071297458065151859959 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3208130115546636085769178431212374629946288475799044192071297458065151859959
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.62363143347136234780428446283717743276474160110975179751828771930063475362282
Short name T335
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.14 seconds
Started Nov 22 12:37:01 PM PST 23
Finished Nov 22 12:37:33 PM PST 23
Peak memory 212728 kb
Host smart-c73e92a9-fe63-41f7-ac66-9d687f281160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62363143347136234780428446283717743276474160110975179751828771930063475362282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.rom_ctrl_smoke.62363143347136234780428446283717743276474160110975179751828771930063475362282
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.8174298201765993514578032805126980054702612339494745435620432123614534776917
Short name T253
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.78 seconds
Started Nov 22 12:37:09 PM PST 23
Finished Nov 22 12:37:54 PM PST 23
Peak memory 212840 kb
Host smart-ee1b3093-4183-4bce-a981-56137d8c7316
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817429820176599351457803280512698005470261233949474543562043212
3614534776917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.817429820176599351457803280512698005470261233949474
5435620432123614534776917
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.50478424991940650432365884636277822152081740766625999601387875122901348928659
Short name T209
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.48 seconds
Started Nov 22 12:37:15 PM PST 23
Finished Nov 22 12:37:33 PM PST 23
Peak memory 211068 kb
Host smart-ffe28a56-c7bf-4fb6-af41-980adc469637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50478424991940650432365884636277822152081740766625999601387875122901348928659 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.50478424991940650432365884636277822152081740766625999601387875122901348928659
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.112933220992066968269847862669709010553137876812579870117494503085087005600178
Short name T326
Test name
Test status
Simulation time 69854280986 ps
CPU time 351.45 seconds
Started Nov 22 12:37:05 PM PST 23
Finished Nov 22 12:42:59 PM PST 23
Peak memory 237584 kb
Host smart-376073df-ae44-4207-a8a6-cc157b820df7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112933220992066968269847862669709010553137876812579870117494503085087005600178 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.11293322099206696826984786266970901055313787681257987011
7494503085087005600178
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.42992898908468278892533225846428240599441519810439123136523105796967464764204
Short name T290
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.85 seconds
Started Nov 22 12:37:12 PM PST 23
Finished Nov 22 12:37:46 PM PST 23
Peak memory 211548 kb
Host smart-119712f3-dd00-4f9c-a0cb-17a77e5d9bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42992898908468278892533225846428240599441519810439123136523105796967464764204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.rom_ctrl_kmac_err_chk.42992898908468278892533225846428240599441519810439123136523105796967464764204
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.88322513210721644209160142180090690491459084085231444244634944769292662347600
Short name T37
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.66 seconds
Started Nov 22 12:37:05 PM PST 23
Finished Nov 22 12:37:21 PM PST 23
Peak memory 211112 kb
Host smart-6e578fc2-f2d4-44f2-a796-485def1a9d13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88322513210721644209160142180090690491459084085231444244634944769292662347600 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.88322513210721644209160142180090690491459084085231444244634944769292662347600
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.11400309871437283435368778150452516446957539382740094868196199419869302712766
Short name T365
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.21 seconds
Started Nov 22 12:37:05 PM PST 23
Finished Nov 22 12:37:36 PM PST 23
Peak memory 212760 kb
Host smart-73e31988-d076-4751-802f-f5cc7aed9d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11400309871437283435368778150452516446957539382740094868196199419869302712766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.rom_ctrl_smoke.11400309871437283435368778150452516446957539382740094868196199419869302712766
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.80359356183987986422783299572026556320773247074771052974420183771408635369571
Short name T162
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.48 seconds
Started Nov 22 12:37:09 PM PST 23
Finished Nov 22 12:37:54 PM PST 23
Peak memory 212832 kb
Host smart-4418c45e-a587-4419-aabf-cb4fe9cf02a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803593561839879864227832995720265563207732470747710529744201837
71408635369571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.80359356183987986422783299572026556320773247074771
052974420183771408635369571
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.8045748300845235427874378875680590872261285191168824511937196029504099340822
Short name T211
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.49 seconds
Started Nov 22 12:37:15 PM PST 23
Finished Nov 22 12:37:33 PM PST 23
Peak memory 211084 kb
Host smart-589ad3f9-c892-44b6-8a33-acb33f82e077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8045748300845235427874378875680590872261285191168824511937196029504099340822 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.8045748300845235427874378875680590872261285191168824511937196029504099340822
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.8583183112407414806673106724208196251904120778462569408619800187584866641605
Short name T11
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.81 seconds
Started Nov 22 12:37:17 PM PST 23
Finished Nov 22 12:43:09 PM PST 23
Peak memory 237596 kb
Host smart-a9387ccb-9681-4ce9-834c-97a81d39b288
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8583183112407414806673106724208196251904120778462569408619800187584866641605 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.8583183112407414806673106724208196251904120778462569408619
800187584866641605
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.17407001542811218204548953109148936911087329312339143528008228781734320851852
Short name T363
Test name
Test status
Simulation time 6233818126 ps
CPU time 26 seconds
Started Nov 22 12:37:12 PM PST 23
Finished Nov 22 12:37:47 PM PST 23
Peak memory 211536 kb
Host smart-3debb4fe-d734-41aa-89c5-65b72c28d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17407001542811218204548953109148936911087329312339143528008228781734320851852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.rom_ctrl_kmac_err_chk.17407001542811218204548953109148936911087329312339143528008228781734320851852
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.91185175187854047608379288112460647748604025647667331753681136128528983586781
Short name T357
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.6 seconds
Started Nov 22 12:37:07 PM PST 23
Finished Nov 22 12:37:24 PM PST 23
Peak memory 211088 kb
Host smart-01ce37f2-35d6-4371-9346-143eaf762767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91185175187854047608379288112460647748604025647667331753681136128528983586781 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.91185175187854047608379288112460647748604025647667331753681136128528983586781
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.73408571629622960647165898109028468858911273515112039498895905067708372864569
Short name T252
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.46 seconds
Started Nov 22 12:37:01 PM PST 23
Finished Nov 22 12:37:32 PM PST 23
Peak memory 212760 kb
Host smart-9fc83a69-7fb2-4937-a635-0b6b7348d882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73408571629622960647165898109028468858911273515112039498895905067708372864569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.rom_ctrl_smoke.73408571629622960647165898109028468858911273515112039498895905067708372864569
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.23665781058005720460669462907750142692474856658173602790766632640236815858302
Short name T199
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.09 seconds
Started Nov 22 12:37:06 PM PST 23
Finished Nov 22 12:37:51 PM PST 23
Peak memory 212756 kb
Host smart-c60756f7-19fb-4542-8b24-08ff77d7eb60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236657810580057204606694629077501426924748566581736027907666326
40236815858302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.23665781058005720460669462907750142692474856658173
602790766632640236815858302
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.20574506962644509037051261787675301938295923092862487007640715237431531222199
Short name T181
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.54 seconds
Started Nov 22 12:37:02 PM PST 23
Finished Nov 22 12:37:17 PM PST 23
Peak memory 211056 kb
Host smart-88f8c2a8-fe04-4bde-99af-ee82c37b7ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20574506962644509037051261787675301938295923092862487007640715237431531222199 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.20574506962644509037051261787675301938295923092862487007640715237431531222199
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.84406548240505121193886775147497986641746964387953047867462988533320363712265
Short name T338
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.36 seconds
Started Nov 22 12:37:05 PM PST 23
Finished Nov 22 12:42:54 PM PST 23
Peak memory 237564 kb
Host smart-b8e885ee-0377-4a9f-aecf-881817cabda8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84406548240505121193886775147497986641746964387953047867462988533320363712265 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.844065482405051211938867751474979866417469643879530478674
62988533320363712265
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.96177816794832635832554544623517901168379607041240782451148276900256851796514
Short name T309
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.86 seconds
Started Nov 22 12:37:12 PM PST 23
Finished Nov 22 12:37:46 PM PST 23
Peak memory 211560 kb
Host smart-1127823a-29f1-4eb9-9629-6b0a9790d8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96177816794832635832554544623517901168379607041240782451148276900256851796514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.rom_ctrl_kmac_err_chk.96177816794832635832554544623517901168379607041240782451148276900256851796514
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.25654880503695856365933868513461708897022606632071090699863064779856456235510
Short name T144
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Nov 22 12:37:24 PM PST 23
Finished Nov 22 12:37:40 PM PST 23
Peak memory 210628 kb
Host smart-f74d6f1f-95fa-4d98-b3a2-2c4b210f2a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25654880503695856365933868513461708897022606632071090699863064779856456235510 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.25654880503695856365933868513461708897022606632071090699863064779856456235510
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.36447324786699651236852259892253818615283388524131585401671932976295559806830
Short name T258
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.99 seconds
Started Nov 22 12:37:15 PM PST 23
Finished Nov 22 12:37:49 PM PST 23
Peak memory 212720 kb
Host smart-1de84a89-d066-42c7-acee-3402b8bf6792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36447324786699651236852259892253818615283388524131585401671932976295559806830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.rom_ctrl_smoke.36447324786699651236852259892253818615283388524131585401671932976295559806830
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.29354602328139289794538057090145353771093936573762869150497755050537713198261
Short name T293
Test name
Test status
Simulation time 9415977006 ps
CPU time 44.07 seconds
Started Nov 22 12:37:02 PM PST 23
Finished Nov 22 12:37:48 PM PST 23
Peak memory 212816 kb
Host smart-46294219-70a7-4758-9146-7f71e0a67a70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293546023281392897945380570901453537710939365737628691504977550
50537713198261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.29354602328139289794538057090145353771093936573762
869150497755050537713198261
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.68083120341197556481848233288349310495842638161658590875461270358338848131759
Short name T308
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.49 seconds
Started Nov 22 12:37:11 PM PST 23
Finished Nov 22 12:37:33 PM PST 23
Peak memory 211060 kb
Host smart-c0b80772-bc9c-4ad3-8221-1ca4c28e84f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68083120341197556481848233288349310495842638161658590875461270358338848131759 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.68083120341197556481848233288349310495842638161658590875461270358338848131759
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.107624753619376546752540898722489667725164169528555389884579127655625385583899
Short name T172
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.19 seconds
Started Nov 22 12:37:19 PM PST 23
Finished Nov 22 12:43:10 PM PST 23
Peak memory 237676 kb
Host smart-4c6a13fb-59bb-4813-b755-f9f72c9f4963
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107624753619376546752540898722489667725164169528555389884579127655625385583899 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.10762475361937654675254089872248966772516416952855538988
4579127655625385583899
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.36710128238666091055181052083168987205445313027016982077977873776475892760200
Short name T349
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.08 seconds
Started Nov 22 12:37:17 PM PST 23
Finished Nov 22 12:37:48 PM PST 23
Peak memory 211504 kb
Host smart-fdc25dce-5ced-450c-8575-d11937520414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36710128238666091055181052083168987205445313027016982077977873776475892760200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.rom_ctrl_kmac_err_chk.36710128238666091055181052083168987205445313027016982077977873776475892760200
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.70283931938112158031139739228688865401746037300421616439469383921286286185679
Short name T283
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.47 seconds
Started Nov 22 12:37:08 PM PST 23
Finished Nov 22 12:37:24 PM PST 23
Peak memory 211084 kb
Host smart-557f3c21-bed4-4dae-8e65-a9a7cb8210dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70283931938112158031139739228688865401746037300421616439469383921286286185679 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.70283931938112158031139739228688865401746037300421616439469383921286286185679
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.44194261157598300220697657986583764977499197595025620878218510526555043562119
Short name T42
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.53 seconds
Started Nov 22 12:37:10 PM PST 23
Finished Nov 22 12:37:48 PM PST 23
Peak memory 212728 kb
Host smart-4fb28913-ba44-4e0b-bcee-ea84aef06b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44194261157598300220697657986583764977499197595025620878218510526555043562119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.rom_ctrl_smoke.44194261157598300220697657986583764977499197595025620878218510526555043562119
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.70957645727395195447932213481371897109578569622409891602481583399087296880325
Short name T167
Test name
Test status
Simulation time 9415977006 ps
CPU time 43 seconds
Started Nov 22 12:37:24 PM PST 23
Finished Nov 22 12:38:10 PM PST 23
Peak memory 212840 kb
Host smart-364fad25-6594-44ad-b777-2bc04a9208c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709576457273951954479322134813718971095785696224098916024815833
99087296880325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.70957645727395195447932213481371897109578569622409
891602481583399087296880325
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.58871854254156316386850832295383903157065486157042814352667928079046882646072
Short name T185
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.65 seconds
Started Nov 22 12:36:30 PM PST 23
Finished Nov 22 12:36:44 PM PST 23
Peak memory 211088 kb
Host smart-bdc3c046-5476-4af5-a018-b35b7aff493b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58871854254156316386850832295383903157065486157042814352667928079046882646072 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.58871854254156316386850832295383903157065486157042814352667928079046882646072
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.13757894388555798452063879439398122644247778079497329264727050083839944474092
Short name T254
Test name
Test status
Simulation time 69854280986 ps
CPU time 333.04 seconds
Started Nov 22 12:36:42 PM PST 23
Finished Nov 22 12:42:15 PM PST 23
Peak memory 237684 kb
Host smart-a6f6009a-b411-41ae-8867-a83a334b49af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757894388555798452063879439398122644247778079497329264727050083839944474092 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.1375789438855579845206387943939812264424777807949732926472
7050083839944474092
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.73327326411499582250829951472307458950393612620722202752057824259309157146725
Short name T255
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.1 seconds
Started Nov 22 12:36:30 PM PST 23
Finished Nov 22 12:36:57 PM PST 23
Peak memory 211548 kb
Host smart-714be8b3-914d-436f-baaf-f8fea4a8a545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73327326411499582250829951472307458950393612620722202752057824259309157146725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.rom_ctrl_kmac_err_chk.73327326411499582250829951472307458950393612620722202752057824259309157146725
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.9294637267584457162095280220994703550981314480855231398407058705614873422956
Short name T334
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.55 seconds
Started Nov 22 12:36:28 PM PST 23
Finished Nov 22 12:36:43 PM PST 23
Peak memory 211052 kb
Host smart-5d3b16e9-b1c0-4af7-adad-16dfb73238f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9294637267584457162095280220994703550981314480855231398407058705614873422956 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.9294637267584457162095280220994703550981314480855231398407058705614873422956
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.35314971326190464453840505202606642195146070926194791189078129201229428132729
Short name T33
Test name
Test status
Simulation time 3444857586 ps
CPU time 113.97 seconds
Started Nov 22 12:36:46 PM PST 23
Finished Nov 22 12:38:41 PM PST 23
Peak memory 236672 kb
Host smart-094fa6eb-c231-4edd-a041-36c440921872
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35314971326190464453840505202606642195146070926194791189078129201229428132729 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.35314971326190464453840505202606642195146070926194791189078129201229428132729
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.7163758533717880603311082826519816502022537125035792783857472773859076127538
Short name T298
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.34 seconds
Started Nov 22 12:36:42 PM PST 23
Finished Nov 22 12:37:12 PM PST 23
Peak memory 212732 kb
Host smart-76a452a3-dcce-4652-b5aa-0209540857f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7163758533717880603311082826519816502022537125035792783857472773859076127538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.rom_ctrl_smoke.7163758533717880603311082826519816502022537125035792783857472773859076127538
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.106486864645220839235450988640447006226255111637059539255670070192701336994760
Short name T91
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.77 seconds
Started Nov 22 12:36:24 PM PST 23
Finished Nov 22 12:37:09 PM PST 23
Peak memory 212860 kb
Host smart-80f7c127-a380-479d-ac54-54ea968a8b7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106486864645220839235450988640447006226255111637059539255670070
192701336994760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.10648686464522083923545098864044700622625511163705
9539255670070192701336994760
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.59740045422924942217036881597358520746909291587270692953431504095979327196739
Short name T314
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.66 seconds
Started Nov 22 12:37:13 PM PST 23
Finished Nov 22 12:37:33 PM PST 23
Peak memory 211108 kb
Host smart-2cec3364-27cc-4f15-abc6-5299bc357a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59740045422924942217036881597358520746909291587270692953431504095979327196739 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.59740045422924942217036881597358520746909291587270692953431504095979327196739
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.72816883957386770815449142227312528531798718428000035239303171878516401589
Short name T214
Test name
Test status
Simulation time 69854280986 ps
CPU time 349.41 seconds
Started Nov 22 12:37:32 PM PST 23
Finished Nov 22 12:43:22 PM PST 23
Peak memory 237696 kb
Host smart-38a6965f-98b4-4fd5-ad61-e54b909a0ac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72816883957386770815449142227312528531798718428000035239303171878516401589 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.728168839573867708154491422273125285317987184280000352393031
71878516401589
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.101003939714494315498940715094670684877393825997171901434225356648032177361463
Short name T114
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.52 seconds
Started Nov 22 12:37:11 PM PST 23
Finished Nov 22 12:37:47 PM PST 23
Peak memory 211512 kb
Host smart-415ffc13-fc0f-44f8-941e-c0936e33aac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101003939714494315498940715094670684877393825997171901434225356648032177361463 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.rom_ctrl_kmac_err_chk.101003939714494315498940715094670684877393825997171901434225356648032177361463
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.95486447967702259751484824774187466281694277229899149254387339987602525912118
Short name T244
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.55 seconds
Started Nov 22 12:37:18 PM PST 23
Finished Nov 22 12:37:35 PM PST 23
Peak memory 211108 kb
Host smart-fecc724a-370d-478f-812c-8e6ebe663fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95486447967702259751484824774187466281694277229899149254387339987602525912118 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.95486447967702259751484824774187466281694277229899149254387339987602525912118
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.13106603101337495783975484005033227973636408273210935251198317429227655038768
Short name T6
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.39 seconds
Started Nov 22 12:37:21 PM PST 23
Finished Nov 22 12:37:55 PM PST 23
Peak memory 212748 kb
Host smart-c393016d-0404-4187-ad5a-b37b1da9e49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13106603101337495783975484005033227973636408273210935251198317429227655038768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.rom_ctrl_smoke.13106603101337495783975484005033227973636408273210935251198317429227655038768
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.94039400946324585864418861675402790010844065544623239266072051481948669217848
Short name T241
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.39 seconds
Started Nov 22 12:37:14 PM PST 23
Finished Nov 22 12:38:09 PM PST 23
Peak memory 212860 kb
Host smart-b3c89d64-f0db-4e9c-b6e6-34d73f99a7cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940394009463245858644188616754027900108440655446232392660720514
81948669217848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.94039400946324585864418861675402790010844065544623
239266072051481948669217848
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.21048060311851837276843513207564115002989915439110840315036879632083885186938
Short name T364
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.63 seconds
Started Nov 22 12:37:31 PM PST 23
Finished Nov 22 12:37:45 PM PST 23
Peak memory 211096 kb
Host smart-d7e6586e-ab77-4221-a968-0d73a6a5cdf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21048060311851837276843513207564115002989915439110840315036879632083885186938 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.21048060311851837276843513207564115002989915439110840315036879632083885186938
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.102776647871271832395420755838442349122308912422431694839319641006159810293951
Short name T168
Test name
Test status
Simulation time 69854280986 ps
CPU time 352.83 seconds
Started Nov 22 12:37:19 PM PST 23
Finished Nov 22 12:43:18 PM PST 23
Peak memory 237608 kb
Host smart-fc0f6c59-17c1-49da-8b37-98423184be75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102776647871271832395420755838442349122308912422431694839319641006159810293951 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.10277664787127183239542075583844234912230891242243169483
9319641006159810293951
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.58926487312133187380660463308943080349783631916511223563135960613892113254106
Short name T16
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.86 seconds
Started Nov 22 12:37:26 PM PST 23
Finished Nov 22 12:37:53 PM PST 23
Peak memory 211556 kb
Host smart-6a6dcfe6-44c2-4f79-9e2c-8ce0bda55bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58926487312133187380660463308943080349783631916511223563135960613892113254106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.rom_ctrl_kmac_err_chk.58926487312133187380660463308943080349783631916511223563135960613892113254106
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.91610518730900195349304632144470729038596061058262050542095667419168455950895
Short name T184
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.21 seconds
Started Nov 22 12:37:36 PM PST 23
Finished Nov 22 12:37:50 PM PST 23
Peak memory 211108 kb
Host smart-023f024a-0fa5-451a-9371-821a52790b2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91610518730900195349304632144470729038596061058262050542095667419168455950895 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.91610518730900195349304632144470729038596061058262050542095667419168455950895
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.23215706651344471521164963975767543402902556751281023466325571147188212700366
Short name T94
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.8 seconds
Started Nov 22 12:37:18 PM PST 23
Finished Nov 22 12:37:51 PM PST 23
Peak memory 212760 kb
Host smart-b3ce7379-b83c-4400-894d-72a69f79e0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23215706651344471521164963975767543402902556751281023466325571147188212700366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.rom_ctrl_smoke.23215706651344471521164963975767543402902556751281023466325571147188212700366
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.94415993325717260964037069850602223228692115961969830641220794168441504419134
Short name T296
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.21 seconds
Started Nov 22 12:37:18 PM PST 23
Finished Nov 22 12:38:05 PM PST 23
Peak memory 212848 kb
Host smart-cb4457e0-d1a1-4eb3-8378-f742b8b86ec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944159933257172609640370698506022232286921159619698306412207941
68441504419134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.94415993325717260964037069850602223228692115961969
830641220794168441504419134
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.91842028230888508279500044605046657538298112737711665035242485456659014666630
Short name T10
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Nov 22 12:37:31 PM PST 23
Finished Nov 22 12:37:44 PM PST 23
Peak memory 211096 kb
Host smart-d2359fb7-3d3f-476e-9a4e-f55db78ea525
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91842028230888508279500044605046657538298112737711665035242485456659014666630 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.91842028230888508279500044605046657538298112737711665035242485456659014666630
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.105822937958407823963329438419371492602089626898418346104852627072993834218389
Short name T275
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.34 seconds
Started Nov 22 12:37:32 PM PST 23
Finished Nov 22 12:43:18 PM PST 23
Peak memory 237712 kb
Host smart-7764d891-5b7d-4591-8e79-fd826ce1cae9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105822937958407823963329438419371492602089626898418346104852627072993834218389 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.10582293795840782396332943841937149260208962689841834610
4852627072993834218389
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.95693927991016561734296350492640255430382044387401148956500999914288153850606
Short name T319
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.8 seconds
Started Nov 22 12:37:20 PM PST 23
Finished Nov 22 12:37:52 PM PST 23
Peak memory 211520 kb
Host smart-18484c82-88f1-44ce-b020-a66aa56ece6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95693927991016561734296350492640255430382044387401148956500999914288153850606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.rom_ctrl_kmac_err_chk.95693927991016561734296350492640255430382044387401148956500999914288153850606
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.59647816263266266054777526239721482840883482554127466786491183042678998529947
Short name T220
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.44 seconds
Started Nov 22 12:37:16 PM PST 23
Finished Nov 22 12:37:34 PM PST 23
Peak memory 211076 kb
Host smart-406fb1c5-7b05-45d9-aba9-ef1d0417a3f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59647816263266266054777526239721482840883482554127466786491183042678998529947 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.59647816263266266054777526239721482840883482554127466786491183042678998529947
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.53001559772452202144294234445123671947217480682915955239073274182675798401057
Short name T352
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.83 seconds
Started Nov 22 12:37:20 PM PST 23
Finished Nov 22 12:37:55 PM PST 23
Peak memory 212756 kb
Host smart-6164b096-d31a-4ce1-925a-653c9ca5347b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53001559772452202144294234445123671947217480682915955239073274182675798401057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.rom_ctrl_smoke.53001559772452202144294234445123671947217480682915955239073274182675798401057
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.67151130928342118874050006117253423757509509822443910225778209120764688217795
Short name T132
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.74 seconds
Started Nov 22 12:37:23 PM PST 23
Finished Nov 22 12:38:11 PM PST 23
Peak memory 212948 kb
Host smart-89ca98d9-dc51-4cb9-a8c9-c7c955959f02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671511309283421188740500061172534237575095098224439102257782091
20764688217795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.67151130928342118874050006117253423757509509822443
910225778209120764688217795
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.114189829654119306498068855079334026025572190959257737881751935040435356575867
Short name T138
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.67 seconds
Started Nov 22 12:37:16 PM PST 23
Finished Nov 22 12:37:33 PM PST 23
Peak memory 211040 kb
Host smart-22089403-af9d-49be-97f0-3f71a518d32f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114189829654119306498068855079334026025572190959257737881751935040435356575867 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.114189829654119306498068855079334026025572190959257737881751935040435356575867
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2605508378711506702625269623372880111250431342788918467308662522589239126597
Short name T270
Test name
Test status
Simulation time 69854280986 ps
CPU time 348.1 seconds
Started Nov 22 12:37:15 PM PST 23
Finished Nov 22 12:43:09 PM PST 23
Peak memory 237588 kb
Host smart-4d1cae68-7f6e-4fae-916a-69cf5cd05b36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605508378711506702625269623372880111250431342788918467308662522589239126597 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.2605508378711506702625269623372880111250431342788918467308
662522589239126597
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.110977902563078797433369680747300070103452169013729355790985123995023703559127
Short name T2
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.74 seconds
Started Nov 22 12:37:18 PM PST 23
Finished Nov 22 12:37:48 PM PST 23
Peak memory 211616 kb
Host smart-5292c6ec-6271-4ea1-93e4-0f4796cfe079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110977902563078797433369680747300070103452169013729355790985123995023703559127 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.rom_ctrl_kmac_err_chk.110977902563078797433369680747300070103452169013729355790985123995023703559127
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.24414193246546784831287299389563700986770526712537542098745868057409532647174
Short name T161
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.47 seconds
Started Nov 22 12:37:16 PM PST 23
Finished Nov 22 12:37:34 PM PST 23
Peak memory 211100 kb
Host smart-f07a8921-6f5f-47a6-b88b-fd6e08eae0b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24414193246546784831287299389563700986770526712537542098745868057409532647174 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.24414193246546784831287299389563700986770526712537542098745868057409532647174
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.89961320598777095482174465925094908763655403020444422859864551349525830466914
Short name T359
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.13 seconds
Started Nov 22 12:37:33 PM PST 23
Finished Nov 22 12:38:03 PM PST 23
Peak memory 212728 kb
Host smart-e345e0c7-1f2e-400a-b858-d8b2926f4bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89961320598777095482174465925094908763655403020444422859864551349525830466914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.rom_ctrl_smoke.89961320598777095482174465925094908763655403020444422859864551349525830466914
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.99025034813235246660870149719067705345156121920980108618539875528950223320671
Short name T327
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.6 seconds
Started Nov 22 12:37:34 PM PST 23
Finished Nov 22 12:38:19 PM PST 23
Peak memory 212852 kb
Host smart-bd65e93a-558e-4444-a88f-cf4a5c1e7cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990250348132352466608701497190677053451561219209801086185398755
28950223320671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.99025034813235246660870149719067705345156121920980
108618539875528950223320671
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.44268967284628808321225144391094058602594364820661371504775651850063085092284
Short name T302
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.21 seconds
Started Nov 22 12:37:20 PM PST 23
Finished Nov 22 12:37:38 PM PST 23
Peak memory 210968 kb
Host smart-1ceb2289-384a-4c16-a3f7-5321c269a979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44268967284628808321225144391094058602594364820661371504775651850063085092284 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.44268967284628808321225144391094058602594364820661371504775651850063085092284
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.86474245742852671711719517937980342365664040093994719339870559571803805693921
Short name T7
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.52 seconds
Started Nov 22 12:37:10 PM PST 23
Finished Nov 22 12:43:01 PM PST 23
Peak memory 237664 kb
Host smart-f843f614-c2c2-4740-857f-18c9641766a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86474245742852671711719517937980342365664040093994719339870559571803805693921 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.864742457428526717117195179379803423656640400939947193398
70559571803805693921
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.65885192075583865864686498638535463023619325889822356091915420182392178044790
Short name T320
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.5 seconds
Started Nov 22 12:37:34 PM PST 23
Finished Nov 22 12:38:02 PM PST 23
Peak memory 211528 kb
Host smart-c16fbc73-6034-4e73-816c-cf06bfb2ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65885192075583865864686498638535463023619325889822356091915420182392178044790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.rom_ctrl_kmac_err_chk.65885192075583865864686498638535463023619325889822356091915420182392178044790
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.84075904698904920212076422060322830688548952641645122171675393886833326216963
Short name T274
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.58 seconds
Started Nov 22 12:37:15 PM PST 23
Finished Nov 22 12:37:34 PM PST 23
Peak memory 211100 kb
Host smart-6e3c02a4-b89f-467f-b13c-1006787ea568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84075904698904920212076422060322830688548952641645122171675393886833326216963 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.84075904698904920212076422060322830688548952641645122171675393886833326216963
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.99931358117124705088742407927181897712959119899229236796527745329734473020078
Short name T269
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.61 seconds
Started Nov 22 12:37:17 PM PST 23
Finished Nov 22 12:37:51 PM PST 23
Peak memory 212748 kb
Host smart-2a5b50d1-b14a-44e9-a782-c2fa2bed34af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99931358117124705088742407927181897712959119899229236796527745329734473020078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.rom_ctrl_smoke.99931358117124705088742407927181897712959119899229236796527745329734473020078
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.76640905211934982253265457520253226414977745090925291054289702227230614536461
Short name T233
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.45 seconds
Started Nov 22 12:37:16 PM PST 23
Finished Nov 22 12:38:04 PM PST 23
Peak memory 212796 kb
Host smart-1ae92acb-9273-4db1-8806-4cdad7ac6c16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766409052119349822532654575202532264149777450909252910542897022
27230614536461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.76640905211934982253265457520253226414977745090925
291054289702227230614536461
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.44978702819988076149094299074051559868752793647171206436326858732798323355488
Short name T218
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.51 seconds
Started Nov 22 12:37:11 PM PST 23
Finished Nov 22 12:37:33 PM PST 23
Peak memory 211076 kb
Host smart-3da4dd60-6ccf-46e0-ae2e-0d7db534e0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44978702819988076149094299074051559868752793647171206436326858732798323355488 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.44978702819988076149094299074051559868752793647171206436326858732798323355488
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.46346072904025268323942932068279596403305864587105697306222284857210409115155
Short name T45
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.11 seconds
Started Nov 22 12:37:14 PM PST 23
Finished Nov 22 12:43:01 PM PST 23
Peak memory 237700 kb
Host smart-c38f8f3c-3558-48f7-b4e2-c94ee0310c06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46346072904025268323942932068279596403305864587105697306222284857210409115155 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.463460729040252683239429320682795964033058645871056973062
22284857210409115155
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.95385878510281390716325196937963796153570769214934947965094288313744437065327
Short name T230
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.07 seconds
Started Nov 22 12:37:33 PM PST 23
Finished Nov 22 12:38:01 PM PST 23
Peak memory 211528 kb
Host smart-001f4e4d-ec54-4e38-951e-e3bafde23e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95385878510281390716325196937963796153570769214934947965094288313744437065327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.rom_ctrl_kmac_err_chk.95385878510281390716325196937963796153570769214934947965094288313744437065327
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.30785054208149214714220142716227461150496102022040871231916914170143166632465
Short name T210
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.97 seconds
Started Nov 22 12:37:20 PM PST 23
Finished Nov 22 12:37:39 PM PST 23
Peak memory 211080 kb
Host smart-e8d00c65-6c23-489b-a88b-c7e52ab07989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30785054208149214714220142716227461150496102022040871231916914170143166632465 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.30785054208149214714220142716227461150496102022040871231916914170143166632465
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.103073978711739669094781978122665911902477586885175445136838069528619438221520
Short name T93
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.5 seconds
Started Nov 22 12:37:26 PM PST 23
Finished Nov 22 12:37:57 PM PST 23
Peak memory 212768 kb
Host smart-8a84004a-c845-416d-9852-3d4c64e43855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103073978711739669094781978122665911902477586885175445136838069528619438221520 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.rom_ctrl_smoke.103073978711739669094781978122665911902477586885175445136838069528619438221520
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.78129253702135656822129454999264106868397796966508994731386642772955341065548
Short name T127
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.37 seconds
Started Nov 22 12:37:20 PM PST 23
Finished Nov 22 12:38:09 PM PST 23
Peak memory 212828 kb
Host smart-b5663ee1-949d-4fd6-9f1f-2c84cd52a57f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781292537021356568221294549992641068683977969665089947313866427
72955341065548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.78129253702135656822129454999264106868397796966508
994731386642772955341065548
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.90208871598274370245148892781549273136063814173006932179276387147502359999243
Short name T164
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.35 seconds
Started Nov 22 12:37:32 PM PST 23
Finished Nov 22 12:37:47 PM PST 23
Peak memory 211028 kb
Host smart-a270d22c-0014-406d-8114-218eff928d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90208871598274370245148892781549273136063814173006932179276387147502359999243 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.90208871598274370245148892781549273136063814173006932179276387147502359999243
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.33210321194156583399180525241345579567911357935923810188211806346683719262720
Short name T367
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.44 seconds
Started Nov 22 12:37:33 PM PST 23
Finished Nov 22 12:43:11 PM PST 23
Peak memory 237540 kb
Host smart-7712d129-87f9-4d12-b55d-b7e2d50c2096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210321194156583399180525241345579567911357935923810188211806346683719262720 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.332103211941565833991805252413455795679113579359238101882
11806346683719262720
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.8737919274226388844365762474936851095521314178646829809164032860637704103148
Short name T134
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.21 seconds
Started Nov 22 12:37:32 PM PST 23
Finished Nov 22 12:38:00 PM PST 23
Peak memory 211464 kb
Host smart-ada13840-bdd0-48da-bb76-d268fcb56ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8737919274226388844365762474936851095521314178646829809164032860637704103148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.rom_ctrl_kmac_err_chk.8737919274226388844365762474936851095521314178646829809164032860637704103148
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.104272147728516387262688060287352957173457639462775046663214956845255722101689
Short name T295
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.49 seconds
Started Nov 22 12:37:15 PM PST 23
Finished Nov 22 12:37:34 PM PST 23
Peak memory 211088 kb
Host smart-2b5e38ce-64e4-491d-b244-cd9fba666723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104272147728516387262688060287352957173457639462775046663214956845255722101689 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.104272147728516387262688060287352957173457639462775046663214956845255722101689
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.63240567442846185026117856657366259858178376617715003180510768843509813448517
Short name T124
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.6 seconds
Started Nov 22 12:37:23 PM PST 23
Finished Nov 22 12:37:56 PM PST 23
Peak memory 212744 kb
Host smart-71d5cf35-8c2e-4fbd-8000-9ea0e863faef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63240567442846185026117856657366259858178376617715003180510768843509813448517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.rom_ctrl_smoke.63240567442846185026117856657366259858178376617715003180510768843509813448517
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.71109371506643361435976281282681759085832209143755946864528589593068682469231
Short name T90
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.93 seconds
Started Nov 22 12:37:20 PM PST 23
Finished Nov 22 12:38:09 PM PST 23
Peak memory 212860 kb
Host smart-707a8048-fecf-4076-8ac0-9d9a322e4811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711093715066433614359762812826817590858322091437559468645285895
93068682469231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.71109371506643361435976281282681759085832209143755
946864528589593068682469231
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.73204698232704632165747396558668729387244914442956157686740869245939456300260
Short name T152
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.82 seconds
Started Nov 22 12:37:43 PM PST 23
Finished Nov 22 12:38:03 PM PST 23
Peak memory 211068 kb
Host smart-570ff1d2-0cc2-4577-ab25-3e79489b505a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73204698232704632165747396558668729387244914442956157686740869245939456300260 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.73204698232704632165747396558668729387244914442956157686740869245939456300260
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.93456310627436740083586544495020519642094221722621038162401663721499303680691
Short name T48
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.74 seconds
Started Nov 22 12:37:42 PM PST 23
Finished Nov 22 12:43:36 PM PST 23
Peak memory 237552 kb
Host smart-f311d99f-37ad-441c-b0df-c41f1fdbc08e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93456310627436740083586544495020519642094221722621038162401663721499303680691 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.934563106274367400835865444950205196420942217226210381624
01663721499303680691
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.25688938922731748355202217358598740145313998426272504137820193910831893992686
Short name T277
Test name
Test status
Simulation time 6233818126 ps
CPU time 26 seconds
Started Nov 22 12:37:42 PM PST 23
Finished Nov 22 12:38:14 PM PST 23
Peak memory 211456 kb
Host smart-85e8862a-1599-4fb5-80c0-a0109f503530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25688938922731748355202217358598740145313998426272504137820193910831893992686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.rom_ctrl_kmac_err_chk.25688938922731748355202217358598740145313998426272504137820193910831893992686
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.63748493634420311803363254154976635185514480171349814326558709922742496179000
Short name T171
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.79 seconds
Started Nov 22 12:37:40 PM PST 23
Finished Nov 22 12:37:57 PM PST 23
Peak memory 211100 kb
Host smart-74f6a3d0-b5a3-4dc2-8319-81f6c5324acc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=63748493634420311803363254154976635185514480171349814326558709922742496179000 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.63748493634420311803363254154976635185514480171349814326558709922742496179000
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.40441576675296594304084160559275951898042886958848240974632028921783355428033
Short name T325
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.4 seconds
Started Nov 22 12:37:45 PM PST 23
Finished Nov 22 12:38:25 PM PST 23
Peak memory 212732 kb
Host smart-409386e2-2bd6-4e8e-99a8-2ba26426ed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40441576675296594304084160559275951898042886958848240974632028921783355428033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.rom_ctrl_smoke.40441576675296594304084160559275951898042886958848240974632028921783355428033
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.15781930831344262862981691244152342446929763939931776794730258550462612458369
Short name T186
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.94 seconds
Started Nov 22 12:37:46 PM PST 23
Finished Nov 22 12:38:40 PM PST 23
Peak memory 212860 kb
Host smart-93cc68a5-eaa2-40b6-9ffa-b9415fb722c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157819308313442628629816912441523424469297639399317767947302585
50462612458369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.15781930831344262862981691244152342446929763939931
776794730258550462612458369
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.53906615462548506734374949225105461634210703218758169286088673223883064101420
Short name T235
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.54 seconds
Started Nov 22 12:37:42 PM PST 23
Finished Nov 22 12:38:01 PM PST 23
Peak memory 211116 kb
Host smart-2ec9aada-9639-457f-95b4-51aff5a550fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53906615462548506734374949225105461634210703218758169286088673223883064101420 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.53906615462548506734374949225105461634210703218758169286088673223883064101420
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.107712834847363138630810242240749428020678470523209766368250118360367743368448
Short name T287
Test name
Test status
Simulation time 69854280986 ps
CPU time 350.17 seconds
Started Nov 22 12:37:53 PM PST 23
Finished Nov 22 12:43:51 PM PST 23
Peak memory 237700 kb
Host smart-f8eae224-c9a0-4edc-9087-7dc6c050b672
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107712834847363138630810242240749428020678470523209766368250118360367743368448 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.10771283484736313863081024224074942802067847052320976636
8250118360367743368448
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.43208298353604645609427466209604064201046315349328058464208928897498576352675
Short name T15
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.98 seconds
Started Nov 22 12:37:45 PM PST 23
Finished Nov 22 12:38:22 PM PST 23
Peak memory 211536 kb
Host smart-4112af4e-71cc-483c-9549-3db291d86393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43208298353604645609427466209604064201046315349328058464208928897498576352675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.rom_ctrl_kmac_err_chk.43208298353604645609427466209604064201046315349328058464208928897498576352675
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.34725148700178298125393045479798647303917990788619949647632691340913426873331
Short name T300
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.63 seconds
Started Nov 22 12:37:44 PM PST 23
Finished Nov 22 12:38:09 PM PST 23
Peak memory 211084 kb
Host smart-093adba3-4f85-49d0-b6bf-c527e6aeb9e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34725148700178298125393045479798647303917990788619949647632691340913426873331 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.34725148700178298125393045479798647303917990788619949647632691340913426873331
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.79990137633134219018273010861463202318764553014688933350075414941233963718424
Short name T246
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.97 seconds
Started Nov 22 12:37:42 PM PST 23
Finished Nov 22 12:38:19 PM PST 23
Peak memory 212752 kb
Host smart-a52483ca-e8fe-4854-8145-557775fc0216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79990137633134219018273010861463202318764553014688933350075414941233963718424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.rom_ctrl_smoke.79990137633134219018273010861463202318764553014688933350075414941233963718424
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.47143467929068033795102612281235116262786782720934995014152732844931382140585
Short name T282
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.66 seconds
Started Nov 22 12:37:44 PM PST 23
Finished Nov 22 12:38:37 PM PST 23
Peak memory 212876 kb
Host smart-b8f65f7c-b087-46a6-b73c-947c0058db98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471434679290680337951026122812351162627867827209349950141527328
44931382140585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.47143467929068033795102612281235116262786782720934
995014152732844931382140585
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.109010214246284346233317723686893090192650563234642608191244196370528520792522
Short name T225
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.45 seconds
Started Nov 22 12:38:03 PM PST 23
Finished Nov 22 12:38:18 PM PST 23
Peak memory 211028 kb
Host smart-34c76ef9-2cf4-4ece-a816-4379d5fd94e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109010214246284346233317723686893090192650563234642608191244196370528520792522 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.109010214246284346233317723686893090192650563234642608191244196370528520792522
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.83090029987457652093595473641402335424857297525245488706676054169041927807879
Short name T163
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.83 seconds
Started Nov 22 12:37:43 PM PST 23
Finished Nov 22 12:43:40 PM PST 23
Peak memory 237652 kb
Host smart-f0aee232-b2db-4747-b11b-159d93610a66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83090029987457652093595473641402335424857297525245488706676054169041927807879 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.830900299874576520935954736414023354248572975252454887066
76054169041927807879
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.57911807363089460579689640833877114127730203395352020244336266080049657039457
Short name T208
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.29 seconds
Started Nov 22 12:37:43 PM PST 23
Finished Nov 22 12:38:20 PM PST 23
Peak memory 211544 kb
Host smart-4636d21a-0e71-4f37-8d3a-5cf0a0e7ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57911807363089460579689640833877114127730203395352020244336266080049657039457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.rom_ctrl_kmac_err_chk.57911807363089460579689640833877114127730203395352020244336266080049657039457
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.101182243873731108165589958005848628938913661324800108713313811360805130250678
Short name T216
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.52 seconds
Started Nov 22 12:37:44 PM PST 23
Finished Nov 22 12:38:10 PM PST 23
Peak memory 211116 kb
Host smart-b5a2425e-16f2-44ac-a90e-8c4bfe3bec97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101182243873731108165589958005848628938913661324800108713313811360805130250678 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.101182243873731108165589958005848628938913661324800108713313811360805130250678
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.10752641101890041856419264372984122037922757439719209780539888657279735483671
Short name T360
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.66 seconds
Started Nov 22 12:37:44 PM PST 23
Finished Nov 22 12:38:25 PM PST 23
Peak memory 212728 kb
Host smart-f94eb734-a2da-45c0-a68b-1a0f7478a87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10752641101890041856419264372984122037922757439719209780539888657279735483671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.rom_ctrl_smoke.10752641101890041856419264372984122037922757439719209780539888657279735483671
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.19780062906047067532698000460609175997740402548318329757740205441367740144371
Short name T125
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.1 seconds
Started Nov 22 12:37:49 PM PST 23
Finished Nov 22 12:38:40 PM PST 23
Peak memory 212780 kb
Host smart-512cb08e-d60f-46a1-8c40-a9ab624fa8b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197800629060470675326980004606091759977404025483183297577402054
41367740144371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.19780062906047067532698000460609175997740402548318
329757740205441367740144371
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.103476516579978225481930138387024678198282977076736816406858143657495069393821
Short name T339
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.5 seconds
Started Nov 22 12:36:30 PM PST 23
Finished Nov 22 12:36:44 PM PST 23
Peak memory 211096 kb
Host smart-1f386e19-31e4-4495-bf6d-3c5d6ecfd695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103476516579978225481930138387024678198282977076736816406858143657495069393821 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.103476516579978225481930138387024678198282977076736816406858143657495069393821
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.32354311527518282598757784998675759753015549174854777928187140720842921655010
Short name T353
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.99 seconds
Started Nov 22 12:36:25 PM PST 23
Finished Nov 22 12:42:09 PM PST 23
Peak memory 237596 kb
Host smart-b7af9c1c-394d-48ff-b8fc-c01c73a5dbc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32354311527518282598757784998675759753015549174854777928187140720842921655010 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.3235431152751828259875778499867575975301554917485477792818
7140720842921655010
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.31024975133487728974858666744317201480093298733151462619854687500125795058177
Short name T265
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.18 seconds
Started Nov 22 12:36:26 PM PST 23
Finished Nov 22 12:36:54 PM PST 23
Peak memory 211528 kb
Host smart-49e83bdd-1fa1-41e9-99d4-ac3391a05494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31024975133487728974858666744317201480093298733151462619854687500125795058177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.rom_ctrl_kmac_err_chk.31024975133487728974858666744317201480093298733151462619854687500125795058177
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.24970502676342411706102652984001679549653026694963554231708547147614416371162
Short name T89
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.29 seconds
Started Nov 22 12:36:28 PM PST 23
Finished Nov 22 12:36:43 PM PST 23
Peak memory 211072 kb
Host smart-e9c4503a-3c72-47af-b926-88547243869a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24970502676342411706102652984001679549653026694963554231708547147614416371162 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.24970502676342411706102652984001679549653026694963554231708547147614416371162
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.68633961948329414011011262364769629964390151780948854310836467259826964551819
Short name T27
Test name
Test status
Simulation time 3444857586 ps
CPU time 115.05 seconds
Started Nov 22 12:36:29 PM PST 23
Finished Nov 22 12:38:25 PM PST 23
Peak memory 236732 kb
Host smart-1813b19f-c15b-4f1f-8bbc-e9b450f7dc6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68633961948329414011011262364769629964390151780948854310836467259826964551819 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.68633961948329414011011262364769629964390151780948854310836467259826964551819
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.15686360639763738745406534584973233785133366619740991105654829706865234097639
Short name T204
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.08 seconds
Started Nov 22 12:36:27 PM PST 23
Finished Nov 22 12:36:57 PM PST 23
Peak memory 212716 kb
Host smart-543488ef-29fa-4d9d-9049-5ca35f20e081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15686360639763738745406534584973233785133366619740991105654829706865234097639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.rom_ctrl_smoke.15686360639763738745406534584973233785133366619740991105654829706865234097639
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.81674511221688756908588223479936398100962585185341762610756101797204259993099
Short name T279
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.16 seconds
Started Nov 22 12:36:23 PM PST 23
Finished Nov 22 12:37:07 PM PST 23
Peak memory 212824 kb
Host smart-04cb955f-964c-4255-9840-1fbbe47c2142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816745112216887569085882234799363981009625851853417626107561017
97204259993099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.816745112216887569085882234799363981009625851853417
62610756101797204259993099
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.61983725158696331687094685809509749444776066559744949796840898902571052149007
Short name T40
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.26 seconds
Started Nov 22 12:37:44 PM PST 23
Finished Nov 22 12:38:06 PM PST 23
Peak memory 211000 kb
Host smart-f208f90f-a8ba-410a-b36e-172145902ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61983725158696331687094685809509749444776066559744949796840898902571052149007 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.61983725158696331687094685809509749444776066559744949796840898902571052149007
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.19701904406578278789041411170701390915523087233404451388536538462658255117594
Short name T226
Test name
Test status
Simulation time 69854280986 ps
CPU time 352.97 seconds
Started Nov 22 12:37:48 PM PST 23
Finished Nov 22 12:43:49 PM PST 23
Peak memory 237676 kb
Host smart-4bb04bd8-5d28-4010-a552-1e426a5be1a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19701904406578278789041411170701390915523087233404451388536538462658255117594 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.197019044065782787890414111707013909155230872334044513885
36538462658255117594
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.45009208728555958609782940575859772237674686310953013892801636111700529507220
Short name T41
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.59 seconds
Started Nov 22 12:37:51 PM PST 23
Finished Nov 22 12:38:25 PM PST 23
Peak memory 211528 kb
Host smart-1fbc252f-b1ad-485e-8743-96e226802b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45009208728555958609782940575859772237674686310953013892801636111700529507220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.rom_ctrl_kmac_err_chk.45009208728555958609782940575859772237674686310953013892801636111700529507220
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.39846418563480027774811884656479893574823216088838392636584902886328267023379
Short name T196
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.29 seconds
Started Nov 22 12:37:42 PM PST 23
Finished Nov 22 12:38:02 PM PST 23
Peak memory 211072 kb
Host smart-9e16feaf-98a2-4252-902e-55f4680e5e5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39846418563480027774811884656479893574823216088838392636584902886328267023379 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.39846418563480027774811884656479893574823216088838392636584902886328267023379
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.75405575631129065675273215543454791552287878274184794973297123900017993772630
Short name T289
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.77 seconds
Started Nov 22 12:37:47 PM PST 23
Finished Nov 22 12:38:25 PM PST 23
Peak memory 212752 kb
Host smart-01b4bea3-cad8-4170-b864-1296163bc2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75405575631129065675273215543454791552287878274184794973297123900017993772630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.rom_ctrl_smoke.75405575631129065675273215543454791552287878274184794973297123900017993772630
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.49261025268052810987007990320974348749915380320544573153518853953458130043077
Short name T115
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.98 seconds
Started Nov 22 12:37:45 PM PST 23
Finished Nov 22 12:38:39 PM PST 23
Peak memory 212840 kb
Host smart-f5679375-0548-42c5-bed7-6098f95a2e38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492610252680528109870079903209743487499153803205445731535188539
53458130043077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.49261025268052810987007990320974348749915380320544
573153518853953458130043077
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.64927615807480753802702685534957051674522477310893620696871398093649656449075
Short name T121
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.79 seconds
Started Nov 22 12:37:47 PM PST 23
Finished Nov 22 12:38:09 PM PST 23
Peak memory 211068 kb
Host smart-9d9c1e87-01a8-4400-9e91-3828e0809045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64927615807480753802702685534957051674522477310893620696871398093649656449075 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.64927615807480753802702685534957051674522477310893620696871398093649656449075
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.16426382950155814155918650899920727406216932479969243500895479439670609876910
Short name T280
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.06 seconds
Started Nov 22 12:37:51 PM PST 23
Finished Nov 22 12:43:40 PM PST 23
Peak memory 237648 kb
Host smart-37e92dd8-4cf6-4b54-b29a-24741b044a17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426382950155814155918650899920727406216932479969243500895479439670609876910 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.164263829501558141559186508999207274062169324799692435008
95479439670609876910
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.81978221736959744003665207338583822112389786138055545239300505944645903000663
Short name T336
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.98 seconds
Started Nov 22 12:37:57 PM PST 23
Finished Nov 22 12:38:29 PM PST 23
Peak memory 211552 kb
Host smart-2e62ac39-ee2b-450c-954c-b201d17a053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81978221736959744003665207338583822112389786138055545239300505944645903000663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.rom_ctrl_kmac_err_chk.81978221736959744003665207338583822112389786138055545239300505944645903000663
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.48620840863957022060413035678387702345686600604871257821441597109001355014651
Short name T299
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.23 seconds
Started Nov 22 12:37:51 PM PST 23
Finished Nov 22 12:38:13 PM PST 23
Peak memory 211056 kb
Host smart-fd481aa4-d926-4303-81cc-098c7ff24882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48620840863957022060413035678387702345686600604871257821441597109001355014651 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.48620840863957022060413035678387702345686600604871257821441597109001355014651
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.83189062883038904465206651983687754652911997605767034661448294136265526329212
Short name T223
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.05 seconds
Started Nov 22 12:37:43 PM PST 23
Finished Nov 22 12:38:22 PM PST 23
Peak memory 212760 kb
Host smart-60003809-954d-4301-986f-197dd44af6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83189062883038904465206651983687754652911997605767034661448294136265526329212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.rom_ctrl_smoke.83189062883038904465206651983687754652911997605767034661448294136265526329212
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.30378289347727424979984467170185322678027321771352916091424381083176958390041
Short name T261
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.05 seconds
Started Nov 22 12:37:50 PM PST 23
Finished Nov 22 12:38:42 PM PST 23
Peak memory 212832 kb
Host smart-fb272372-048d-4461-9e0b-c03798cdf865
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303782893477274249799844671701853226780273217713529160914243810
83176958390041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.30378289347727424979984467170185322678027321771352
916091424381083176958390041
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.19043403146781221291666330223365018138385844788043323524237893601018632554597
Short name T285
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.74 seconds
Started Nov 22 12:37:49 PM PST 23
Finished Nov 22 12:38:09 PM PST 23
Peak memory 211100 kb
Host smart-f26bb063-b213-4492-89ca-a3391be812a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19043403146781221291666330223365018138385844788043323524237893601018632554597 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.19043403146781221291666330223365018138385844788043323524237893601018632554597
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.71482486517580638204356239210080774818460532064827609596349322445261865651069
Short name T44
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.39 seconds
Started Nov 22 12:37:49 PM PST 23
Finished Nov 22 12:43:32 PM PST 23
Peak memory 237752 kb
Host smart-6b712a98-d683-411e-9a35-01e1beb4a3fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71482486517580638204356239210080774818460532064827609596349322445261865651069 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.714824865175806382043562392100807748184605320648276095963
49322445261865651069
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.111431908725962170748280308056107860533677057784058302605920913468917924813062
Short name T312
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.48 seconds
Started Nov 22 12:37:47 PM PST 23
Finished Nov 22 12:38:21 PM PST 23
Peak memory 211544 kb
Host smart-709de7cf-5963-4145-964a-5f5a4a2fba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111431908725962170748280308056107860533677057784058302605920913468917924813062 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.rom_ctrl_kmac_err_chk.111431908725962170748280308056107860533677057784058302605920913468917924813062
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.99152423376094347758641347448005562229706282499704103015993255709188985021779
Short name T150
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.38 seconds
Started Nov 22 12:37:47 PM PST 23
Finished Nov 22 12:38:09 PM PST 23
Peak memory 211104 kb
Host smart-e1b426a2-17c1-4a07-a40f-fd3642cef6e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99152423376094347758641347448005562229706282499704103015993255709188985021779 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.99152423376094347758641347448005562229706282499704103015993255709188985021779
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.13200090577651864415230107953407894295701715337051482009043697058376622961351
Short name T330
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.97 seconds
Started Nov 22 12:37:46 PM PST 23
Finished Nov 22 12:38:25 PM PST 23
Peak memory 212732 kb
Host smart-c2f1df67-1b0e-40aa-8c82-3cb6badf29ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13200090577651864415230107953407894295701715337051482009043697058376622961351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.rom_ctrl_smoke.13200090577651864415230107953407894295701715337051482009043697058376622961351
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.80512578015835039564207498606064647868024622662662852016737929034220694185583
Short name T203
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.64 seconds
Started Nov 22 12:37:47 PM PST 23
Finished Nov 22 12:38:39 PM PST 23
Peak memory 212852 kb
Host smart-d8553f91-26a1-4835-a45c-7de617ea7f08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805125780158350395642074986060646478680246226626628520167379290
34220694185583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.80512578015835039564207498606064647868024622662662
852016737929034220694185583
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.66952096314777097077473015159349655388000465943868640934927699832923780469996
Short name T348
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.79 seconds
Started Nov 22 12:37:54 PM PST 23
Finished Nov 22 12:38:15 PM PST 23
Peak memory 211100 kb
Host smart-52d975ed-f00f-4d03-ac53-39e9a0476157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66952096314777097077473015159349655388000465943868640934927699832923780469996 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.66952096314777097077473015159349655388000465943868640934927699832923780469996
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.18847342651323360834400254572311457416913365289374067033483895390815262582257
Short name T39
Test name
Test status
Simulation time 69854280986 ps
CPU time 349.88 seconds
Started Nov 22 12:37:53 PM PST 23
Finished Nov 22 12:43:51 PM PST 23
Peak memory 237588 kb
Host smart-80e5c26f-d40f-4e69-873e-72f87967b31b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18847342651323360834400254572311457416913365289374067033483895390815262582257 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.188473426513233608344002545723114574169133652893740670334
83895390815262582257
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.75472557513228236178385376603994979337643692449981723966140315304913716835192
Short name T351
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.12 seconds
Started Nov 22 12:37:44 PM PST 23
Finished Nov 22 12:38:22 PM PST 23
Peak memory 211484 kb
Host smart-e99b6a6f-7491-4af7-84a1-7b315982ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75472557513228236178385376603994979337643692449981723966140315304913716835192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.rom_ctrl_kmac_err_chk.75472557513228236178385376603994979337643692449981723966140315304913716835192
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.69678886907760837318596344812493918609265924821340581235618067879668145699741
Short name T92
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.09 seconds
Started Nov 22 12:39:07 PM PST 23
Finished Nov 22 12:39:22 PM PST 23
Peak memory 211064 kb
Host smart-78f445c9-2241-4bde-be75-120c020e88ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69678886907760837318596344812493918609265924821340581235618067879668145699741 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.69678886907760837318596344812493918609265924821340581235618067879668145699741
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.49233852791515470171038332296546908102875742435692307750595841167940160741041
Short name T343
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.71 seconds
Started Nov 22 12:37:53 PM PST 23
Finished Nov 22 12:38:30 PM PST 23
Peak memory 212616 kb
Host smart-7698c712-7afe-4d1a-a0bb-720a350a45f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49233852791515470171038332296546908102875742435692307750595841167940160741041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.rom_ctrl_smoke.49233852791515470171038332296546908102875742435692307750595841167940160741041
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.115039496894218677362919338255844898903967012890169949979746704312828842834891
Short name T284
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.58 seconds
Started Nov 22 12:37:50 PM PST 23
Finished Nov 22 12:38:43 PM PST 23
Peak memory 212940 kb
Host smart-fa3873e5-aa6d-4713-828f-56f73a27e317
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115039496894218677362919338255844898903967012890169949979746704
312828842834891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.1150394968942186773629193382558448989039670128901
69949979746704312828842834891
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.57287945710495431888834241399186865938129282151040561419394470722117874723357
Short name T200
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.42 seconds
Started Nov 22 12:38:50 PM PST 23
Finished Nov 22 12:39:06 PM PST 23
Peak memory 210248 kb
Host smart-e97e098e-3ff8-44dc-9fa3-7999ffc32e56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57287945710495431888834241399186865938129282151040561419394470722117874723357 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.57287945710495431888834241399186865938129282151040561419394470722117874723357
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.46288743566096087048636459295639579052191905833876994350323084832021077576537
Short name T242
Test name
Test status
Simulation time 69854280986 ps
CPU time 348.68 seconds
Started Nov 22 12:37:59 PM PST 23
Finished Nov 22 12:43:52 PM PST 23
Peak memory 237496 kb
Host smart-4066e8e6-4f42-43e6-a669-4a436bdc41f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46288743566096087048636459295639579052191905833876994350323084832021077576537 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.462887435660960870486364592956395790521919058338769943503
23084832021077576537
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.17593700057392095676847772042072907067913213568376783315918103655845434268118
Short name T151
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.58 seconds
Started Nov 22 12:37:50 PM PST 23
Finished Nov 22 12:38:22 PM PST 23
Peak memory 211564 kb
Host smart-eb3aad35-483c-4dab-828f-a6217177f292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17593700057392095676847772042072907067913213568376783315918103655845434268118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.rom_ctrl_kmac_err_chk.17593700057392095676847772042072907067913213568376783315918103655845434268118
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.55171199546672813737323586874915104489943459755894918936644417536603764149535
Short name T146
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Nov 22 12:37:47 PM PST 23
Finished Nov 22 12:38:09 PM PST 23
Peak memory 211108 kb
Host smart-1ea653ab-d564-4c68-9365-0e48682a6902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55171199546672813737323586874915104489943459755894918936644417536603764149535 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.55171199546672813737323586874915104489943459755894918936644417536603764149535
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.28343490829231629309972587343133509374477929968843213636549190654424265663405
Short name T103
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.27 seconds
Started Nov 22 12:37:54 PM PST 23
Finished Nov 22 12:38:31 PM PST 23
Peak memory 212732 kb
Host smart-bfc54967-18ba-4388-aa8a-4ee74f5846cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28343490829231629309972587343133509374477929968843213636549190654424265663405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.rom_ctrl_smoke.28343490829231629309972587343133509374477929968843213636549190654424265663405
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.74814633752527945151170211244475120799964145730406497316736366695251402833021
Short name T347
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.29 seconds
Started Nov 22 12:37:55 PM PST 23
Finished Nov 22 12:38:45 PM PST 23
Peak memory 212856 kb
Host smart-7a21ff06-2c89-4935-95d0-25c96a61078f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748146337525279451511702112444751207999641457304064973167363666
95251402833021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.74814633752527945151170211244475120799964145730406
497316736366695251402833021
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.63067636743051487864664790121437580832296609589067995348845743992449183014701
Short name T361
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.38 seconds
Started Nov 22 12:38:53 PM PST 23
Finished Nov 22 12:39:07 PM PST 23
Peak memory 210640 kb
Host smart-5d7d8d96-707e-447b-a00f-14e120743cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63067636743051487864664790121437580832296609589067995348845743992449183014701 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.63067636743051487864664790121437580832296609589067995348845743992449183014701
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.11883959368331168900644837558414394962993453396107627445755072613297378308873
Short name T240
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.33 seconds
Started Nov 22 12:37:50 PM PST 23
Finished Nov 22 12:43:41 PM PST 23
Peak memory 237704 kb
Host smart-47446b27-8bab-4969-b9a5-ca4b7375468c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11883959368331168900644837558414394962993453396107627445755072613297378308873 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.118839593683311689006448375584143949629934533961076274457
55072613297378308873
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.46299383005586879510581460586355032086819433653611962661628451685255686357536
Short name T189
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.34 seconds
Started Nov 22 12:38:56 PM PST 23
Finished Nov 22 12:39:22 PM PST 23
Peak memory 211240 kb
Host smart-af241c6e-1aab-4125-8345-d76abb3de7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46299383005586879510581460586355032086819433653611962661628451685255686357536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.rom_ctrl_kmac_err_chk.46299383005586879510581460586355032086819433653611962661628451685255686357536
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.101027968897490315262721602092582009795387435813773701231894107804363110001732
Short name T341
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Nov 22 12:37:59 PM PST 23
Finished Nov 22 12:38:16 PM PST 23
Peak memory 211000 kb
Host smart-0a553abb-ea40-41ce-92f6-432cdd4846f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101027968897490315262721602092582009795387435813773701231894107804363110001732 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.101027968897490315262721602092582009795387435813773701231894107804363110001732
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.54358003198325119708760138943177209521634278658718395194853502647266005242986
Short name T143
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.86 seconds
Started Nov 22 12:37:59 PM PST 23
Finished Nov 22 12:38:32 PM PST 23
Peak memory 212648 kb
Host smart-94e253bb-a79f-4250-a59f-0a734fe6b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54358003198325119708760138943177209521634278658718395194853502647266005242986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.rom_ctrl_smoke.54358003198325119708760138943177209521634278658718395194853502647266005242986
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.62078208361009077629006335709736304724076532162078704837474973556188686557978
Short name T137
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.71 seconds
Started Nov 22 12:37:59 PM PST 23
Finished Nov 22 12:38:46 PM PST 23
Peak memory 212732 kb
Host smart-3358f2e3-8147-46f6-9af2-9ef5ca043372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620782083610090776290063357097363047240765321620787048374749735
56188686557978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.62078208361009077629006335709736304724076532162078
704837474973556188686557978
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.13619070609035243812399134696502546777372570332824956610673701511613527294700
Short name T135
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.67 seconds
Started Nov 22 12:37:48 PM PST 23
Finished Nov 22 12:38:09 PM PST 23
Peak memory 211192 kb
Host smart-219aca42-f8be-468b-8811-16e84cda22a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13619070609035243812399134696502546777372570332824956610673701511613527294700 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.13619070609035243812399134696502546777372570332824956610673701511613527294700
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.113178433165682625985835187788937893800783981747168012611760593824340658709051
Short name T231
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.69 seconds
Started Nov 22 12:37:47 PM PST 23
Finished Nov 22 12:43:41 PM PST 23
Peak memory 237680 kb
Host smart-936d06b6-fe17-4dca-b172-34d6d0836530
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113178433165682625985835187788937893800783981747168012611760593824340658709051 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.11317843316568262598583518778893789380078398174716801261
1760593824340658709051
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.89330752020887252084279963985907206196874788595793217264350502450975211918782
Short name T291
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.41 seconds
Started Nov 22 12:37:45 PM PST 23
Finished Nov 22 12:38:22 PM PST 23
Peak memory 211624 kb
Host smart-2336156e-e21c-4957-b620-bf83e11663c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89330752020887252084279963985907206196874788595793217264350502450975211918782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.rom_ctrl_kmac_err_chk.89330752020887252084279963985907206196874788595793217264350502450975211918782
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.111824658064200624731081802256428752915502995450288621601575817768757403493000
Short name T260
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.64 seconds
Started Nov 22 12:37:44 PM PST 23
Finished Nov 22 12:38:07 PM PST 23
Peak memory 211080 kb
Host smart-529434d2-0dd8-4a7e-9557-645e6f029fce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111824658064200624731081802256428752915502995450288621601575817768757403493000 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.111824658064200624731081802256428752915502995450288621601575817768757403493000
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.109368358946260183203718025882259848384942089669301903325727457630088631857070
Short name T194
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.84 seconds
Started Nov 22 12:37:47 PM PST 23
Finished Nov 22 12:38:25 PM PST 23
Peak memory 212740 kb
Host smart-6892f6a2-f4b6-4cb7-aa65-3c30de71f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109368358946260183203718025882259848384942089669301903325727457630088631857070 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.rom_ctrl_smoke.109368358946260183203718025882259848384942089669301903325727457630088631857070
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.18330280171393669284040916171610725896922221730648136011287764679355872609497
Short name T197
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.83 seconds
Started Nov 22 12:37:44 PM PST 23
Finished Nov 22 12:38:40 PM PST 23
Peak memory 212876 kb
Host smart-3c45671b-6a17-44ae-95fd-3e4feb0f2eec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183302801713936692840409161716107258969222217306481360112877646
79355872609497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.18330280171393669284040916171610725896922221730648
136011287764679355872609497
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.40712872564667567551349532785982155169256485026119405520415178203255462923821
Short name T129
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.65 seconds
Started Nov 22 12:38:15 PM PST 23
Finished Nov 22 12:38:30 PM PST 23
Peak memory 211084 kb
Host smart-2d951043-c4bc-48cf-a805-d57325c82ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40712872564667567551349532785982155169256485026119405520415178203255462923821 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.40712872564667567551349532785982155169256485026119405520415178203255462923821
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.10397560065021707836688212991603020294173987277721436163025392491915041934157
Short name T188
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.96 seconds
Started Nov 22 12:37:43 PM PST 23
Finished Nov 22 12:43:41 PM PST 23
Peak memory 237528 kb
Host smart-bb6039bd-4475-4eee-9f9a-b6841ace35d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10397560065021707836688212991603020294173987277721436163025392491915041934157 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.103975600650217078366882129916030202941739872777214361630
25392491915041934157
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.74265067835486406224787060237596179612969089980920690913845409155450163852669
Short name T323
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.43 seconds
Started Nov 22 12:38:11 PM PST 23
Finished Nov 22 12:38:37 PM PST 23
Peak memory 211508 kb
Host smart-873cbfc1-e7ae-41f9-9305-fe3053d5adf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74265067835486406224787060237596179612969089980920690913845409155450163852669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.rom_ctrl_kmac_err_chk.74265067835486406224787060237596179612969089980920690913845409155450163852669
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.53500820802068218415823123010026623518388512551980343422880812115196750427029
Short name T362
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Nov 22 12:37:43 PM PST 23
Finished Nov 22 12:38:07 PM PST 23
Peak memory 210980 kb
Host smart-b79a683b-9057-43e4-8681-df7d059799a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53500820802068218415823123010026623518388512551980343422880812115196750427029 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.53500820802068218415823123010026623518388512551980343422880812115196750427029
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.6755288428809288979674426250932486760296019477794355060243908218417293768095
Short name T191
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.47 seconds
Started Nov 22 12:38:03 PM PST 23
Finished Nov 22 12:38:34 PM PST 23
Peak memory 212680 kb
Host smart-f78a42f5-d22b-4202-9655-759596bc0e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6755288428809288979674426250932486760296019477794355060243908218417293768095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.rom_ctrl_smoke.6755288428809288979674426250932486760296019477794355060243908218417293768095
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.72383282918852541167443610555811892209409978537071717627745615003956048955263
Short name T215
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.62 seconds
Started Nov 22 12:37:48 PM PST 23
Finished Nov 22 12:38:40 PM PST 23
Peak memory 212840 kb
Host smart-35ae6411-4b6b-4430-8580-2aeb962e063c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723832829188525411674436105558118922094099785370717176277456150
03956048955263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.72383282918852541167443610555811892209409978537071
717627745615003956048955263
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.94656429478899144321871305653813313279752383896490499299522408066469142964511
Short name T257
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.56 seconds
Started Nov 22 12:38:16 PM PST 23
Finished Nov 22 12:38:31 PM PST 23
Peak memory 211192 kb
Host smart-febef448-ac9e-41b8-abed-cee940caffb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94656429478899144321871305653813313279752383896490499299522408066469142964511 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.94656429478899144321871305653813313279752383896490499299522408066469142964511
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.27268890709546515295900669704721628802343771647771505436059691854395444410134
Short name T158
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.17 seconds
Started Nov 22 12:38:19 PM PST 23
Finished Nov 22 12:44:09 PM PST 23
Peak memory 237620 kb
Host smart-9da3dd4a-eb1b-4e84-87e6-962e1f0f1c91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27268890709546515295900669704721628802343771647771505436059691854395444410134 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.272688907095465152959006697047216288023437716477715054360
59691854395444410134
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.23707826974918551613035651652393186080451668127387623432439443378470175267398
Short name T344
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.82 seconds
Started Nov 22 12:38:08 PM PST 23
Finished Nov 22 12:38:35 PM PST 23
Peak memory 211572 kb
Host smart-1a52aaaf-c407-43cf-a9ca-801ca7afb93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23707826974918551613035651652393186080451668127387623432439443378470175267398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.rom_ctrl_kmac_err_chk.23707826974918551613035651652393186080451668127387623432439443378470175267398
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.96197416055177040672207838317668532116665563873867919656518201232587121324501
Short name T12
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.36 seconds
Started Nov 22 12:38:17 PM PST 23
Finished Nov 22 12:38:32 PM PST 23
Peak memory 211088 kb
Host smart-2bc8da86-e6db-4f43-ae67-206ae044bb75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96197416055177040672207838317668532116665563873867919656518201232587121324501 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.96197416055177040672207838317668532116665563873867919656518201232587121324501
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.54406689807120031439915990409215988153157771614597518824612690249618122550436
Short name T142
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.03 seconds
Started Nov 22 12:38:10 PM PST 23
Finished Nov 22 12:38:40 PM PST 23
Peak memory 212860 kb
Host smart-8d385b24-3c4d-4894-bcef-2f2e396d65f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54406689807120031439915990409215988153157771614597518824612690249618122550436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.rom_ctrl_smoke.54406689807120031439915990409215988153157771614597518824612690249618122550436
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.90877019884583614603204681190096019977379776554291377336542186160268645643867
Short name T268
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.01 seconds
Started Nov 22 12:38:15 PM PST 23
Finished Nov 22 12:39:00 PM PST 23
Peak memory 212856 kb
Host smart-a21119a1-3982-40e9-9ec1-86d38769b8c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908770198845836146032046811900960199773797765542913773365421861
60268645643867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.90877019884583614603204681190096019977379776554291
377336542186160268645643867
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.24778379954325492041757416458238496913726475766092860616916445005608050045677
Short name T201
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.77 seconds
Started Nov 22 12:38:11 PM PST 23
Finished Nov 22 12:38:25 PM PST 23
Peak memory 211116 kb
Host smart-f9b630c5-a59b-457f-a298-9329f243ff48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24778379954325492041757416458238496913726475766092860616916445005608050045677 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.24778379954325492041757416458238496913726475766092860616916445005608050045677
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.71040379601794913540503052846054711659319641869810793662067302243053850464949
Short name T247
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.55 seconds
Started Nov 22 12:38:16 PM PST 23
Finished Nov 22 12:44:06 PM PST 23
Peak memory 237652 kb
Host smart-7043dc20-98f6-4e2b-bf01-d2ca0a692b95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71040379601794913540503052846054711659319641869810793662067302243053850464949 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.710403796017949135405030528460547116593196418698107936620
67302243053850464949
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.64381880174119408289654098049838315457970520475417338244067239673926967980190
Short name T217
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.26 seconds
Started Nov 22 12:38:13 PM PST 23
Finished Nov 22 12:38:42 PM PST 23
Peak memory 211496 kb
Host smart-db3a82ec-41ab-4fd9-88db-b280d14bc261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64381880174119408289654098049838315457970520475417338244067239673926967980190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.rom_ctrl_kmac_err_chk.64381880174119408289654098049838315457970520475417338244067239673926967980190
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.34266985515065055706689841056831888826574625741356735310547434101723127849129
Short name T340
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.31 seconds
Started Nov 22 12:38:12 PM PST 23
Finished Nov 22 12:38:26 PM PST 23
Peak memory 211104 kb
Host smart-b033b9dd-60a2-404c-9413-22db9fd2020f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34266985515065055706689841056831888826574625741356735310547434101723127849129 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.34266985515065055706689841056831888826574625741356735310547434101723127849129
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.114707586642630072224292827546399422434839927580900806785762916680374153865500
Short name T245
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.26 seconds
Started Nov 22 12:38:14 PM PST 23
Finished Nov 22 12:38:44 PM PST 23
Peak memory 212720 kb
Host smart-64aad26e-de94-4814-9777-103e35fb7c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114707586642630072224292827546399422434839927580900806785762916680374153865500 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.rom_ctrl_smoke.114707586642630072224292827546399422434839927580900806785762916680374153865500
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.67234939016660362800117408526595069596749664263580939299697219770568628890480
Short name T117
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.32 seconds
Started Nov 22 12:38:15 PM PST 23
Finished Nov 22 12:39:01 PM PST 23
Peak memory 212936 kb
Host smart-9c9464cc-076b-447b-a551-5f336804821e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672349390166603628001174085265950695967496642635809392996972197
70568628890480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.67234939016660362800117408526595069596749664263580
939299697219770568628890480
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.26990826096768534433196517305024384399855588409901264454073698797043371018996
Short name T179
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.56 seconds
Started Nov 22 12:36:30 PM PST 23
Finished Nov 22 12:36:43 PM PST 23
Peak memory 211040 kb
Host smart-01dfe8b1-9746-435b-aea4-fe2c0e3c4fe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26990826096768534433196517305024384399855588409901264454073698797043371018996 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.26990826096768534433196517305024384399855588409901264454073698797043371018996
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.23514643061897233234567550357489964138049315768892667250042800621079555259684
Short name T345
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.16 seconds
Started Nov 22 12:36:30 PM PST 23
Finished Nov 22 12:42:16 PM PST 23
Peak memory 237576 kb
Host smart-9a478e80-20cb-42be-9c2b-b5f24d8c6773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23514643061897233234567550357489964138049315768892667250042800621079555259684 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.2351464306189723323456755035748996413804931576889266725004
2800621079555259684
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.100368316329160304924280921130423755239022692670155389132867745999195912318087
Short name T206
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.3 seconds
Started Nov 22 12:36:40 PM PST 23
Finished Nov 22 12:37:07 PM PST 23
Peak memory 211496 kb
Host smart-a234c812-1871-40fc-b70f-7913d8d1bef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100368316329160304924280921130423755239022692670155389132867745999195912318087 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.rom_ctrl_kmac_err_chk.100368316329160304924280921130423755239022692670155389132867745999195912318087
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.81532219561287262769100227157658289230001696131959529260496041165140814716141
Short name T166
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.09 seconds
Started Nov 22 12:36:50 PM PST 23
Finished Nov 22 12:37:06 PM PST 23
Peak memory 211132 kb
Host smart-485a790d-b5e9-401a-aa3c-9b283f9f0804
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81532219561287262769100227157658289230001696131959529260496041165140814716141 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.81532219561287262769100227157658289230001696131959529260496041165140814716141
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.31581170759867600082071491184864674436013190163361954096316087052244271013910
Short name T301
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.22 seconds
Started Nov 22 12:37:13 PM PST 23
Finished Nov 22 12:37:49 PM PST 23
Peak memory 211460 kb
Host smart-46d2a3ce-304a-4e93-871c-ca00d151a452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31581170759867600082071491184864674436013190163361954096316087052244271013910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.rom_ctrl_smoke.31581170759867600082071491184864674436013190163361954096316087052244271013910
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.98082938430322283654434270424663728828796176993394488181315867113052892216596
Short name T139
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.92 seconds
Started Nov 22 12:36:24 PM PST 23
Finished Nov 22 12:37:08 PM PST 23
Peak memory 212864 kb
Host smart-f915aa75-7eca-4b06-a0fc-b7dd881b58c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980829384303222836544342704246637288287961769933944881813158671
13052892216596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.980829384303222836544342704246637288287961769933944
88181315867113052892216596
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.73518909461865109135458518873503278280622171673059570618314091369764277870336
Short name T332
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.34 seconds
Started Nov 22 12:36:36 PM PST 23
Finished Nov 22 12:36:50 PM PST 23
Peak memory 211072 kb
Host smart-f71eb696-9c83-4c8b-b9aa-4719f3a926a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73518909461865109135458518873503278280622171673059570618314091369764277870336 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.73518909461865109135458518873503278280622171673059570618314091369764277870336
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.46002970520672241769088911794099743969483790533520637534465838886333968692032
Short name T46
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.57 seconds
Started Nov 22 12:36:40 PM PST 23
Finished Nov 22 12:42:16 PM PST 23
Peak memory 237668 kb
Host smart-e7268d1d-1256-48e8-98df-4b6ab3d426fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46002970520672241769088911794099743969483790533520637534465838886333968692032 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.4600297052067224176908891179409974396948379053352063753446
5838886333968692032
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.32500564899542377708731761166884218366178946304924270549047324195189577457149
Short name T328
Test name
Test status
Simulation time 6233818126 ps
CPU time 27.09 seconds
Started Nov 22 12:36:27 PM PST 23
Finished Nov 22 12:36:55 PM PST 23
Peak memory 211528 kb
Host smart-f5690d9d-24ac-429c-8a86-7d05f981cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32500564899542377708731761166884218366178946304924270549047324195189577457149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.rom_ctrl_kmac_err_chk.32500564899542377708731761166884218366178946304924270549047324195189577457149
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.45655998139791229612781541820993335567403907458962504176885221568607124222566
Short name T155
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.55 seconds
Started Nov 22 12:36:25 PM PST 23
Finished Nov 22 12:36:40 PM PST 23
Peak memory 211136 kb
Host smart-db90c3ce-dc22-4234-b06b-a56a17f54b70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45655998139791229612781541820993335567403907458962504176885221568607124222566 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.45655998139791229612781541820993335567403907458962504176885221568607124222566
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1105543762000922767161303037936034633582410836910776748145162660592904679412
Short name T120
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.87 seconds
Started Nov 22 12:36:27 PM PST 23
Finished Nov 22 12:36:57 PM PST 23
Peak memory 212736 kb
Host smart-85943e04-9341-4d72-8a8d-9105a0b1bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105543762000922767161303037936034633582410836910776748145162660592904679412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.rom_ctrl_smoke.1105543762000922767161303037936034633582410836910776748145162660592904679412
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.100891271246002373702389574468931066510762237109693529937388288436793546710898
Short name T227
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.93 seconds
Started Nov 22 12:36:39 PM PST 23
Finished Nov 22 12:37:22 PM PST 23
Peak memory 212832 kb
Host smart-b08f8ee0-f6f1-4898-b178-2c7083c0bd6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100891271246002373702389574468931066510762237109693529937388288
436793546710898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.10089127124600237370238957446893106651076223710969
3529937388288436793546710898
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.51865801732824588158525170865307188766378779374303332279228160736487321157334
Short name T337
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.14 seconds
Started Nov 22 12:36:30 PM PST 23
Finished Nov 22 12:36:43 PM PST 23
Peak memory 211084 kb
Host smart-97d00248-164f-4479-a83c-335587d0ed23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51865801732824588158525170865307188766378779374303332279228160736487321157334 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.51865801732824588158525170865307188766378779374303332279228160736487321157334
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.92446779486897427520921185262834837246508481196802324611649661639167020915425
Short name T170
Test name
Test status
Simulation time 69854280986 ps
CPU time 350.16 seconds
Started Nov 22 12:36:34 PM PST 23
Finished Nov 22 12:42:25 PM PST 23
Peak memory 237484 kb
Host smart-9b83fb70-d911-4050-a0da-4eadd3a65b76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92446779486897427520921185262834837246508481196802324611649661639167020915425 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.9244677948689742752092118526283483724650848119680232461164
9661639167020915425
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.24460545756438979189212151736340409786044156751157425988062239948037577201360
Short name T271
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.35 seconds
Started Nov 22 12:36:27 PM PST 23
Finished Nov 22 12:36:55 PM PST 23
Peak memory 211556 kb
Host smart-5f7264a8-5b1a-4ae7-99ae-2d8d4601372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24460545756438979189212151736340409786044156751157425988062239948037577201360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.rom_ctrl_kmac_err_chk.24460545756438979189212151736340409786044156751157425988062239948037577201360
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.81750189144813050098745325971813446811305174180888268010618937553762626902969
Short name T228
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.69 seconds
Started Nov 22 12:36:34 PM PST 23
Finished Nov 22 12:36:49 PM PST 23
Peak memory 211068 kb
Host smart-01db4aad-c268-454d-a1da-5e3e122fa17f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81750189144813050098745325971813446811305174180888268010618937553762626902969 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.81750189144813050098745325971813446811305174180888268010618937553762626902969
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.68682408019738487612672315396442147994231338384482973047668741377800923285400
Short name T234
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.81 seconds
Started Nov 22 12:36:24 PM PST 23
Finished Nov 22 12:36:55 PM PST 23
Peak memory 212760 kb
Host smart-3d701839-1a5d-453a-a45b-cff063dc6ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68682408019738487612672315396442147994231338384482973047668741377800923285400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.rom_ctrl_smoke.68682408019738487612672315396442147994231338384482973047668741377800923285400
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.107019717121242091010265507093896587870349330346276908611794688767955352917804
Short name T232
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.41 seconds
Started Nov 22 12:36:29 PM PST 23
Finished Nov 22 12:37:14 PM PST 23
Peak memory 212804 kb
Host smart-c949e94c-2ff5-4678-b116-44bc45cf9d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107019717121242091010265507093896587870349330346276908611794688
767955352917804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.10701971712124209101026550709389658787034933034627
6908611794688767955352917804
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.69639497777983797338413316679783976063460960242834321249497674974900089448855
Short name T213
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.73 seconds
Started Nov 22 12:36:26 PM PST 23
Finished Nov 22 12:36:40 PM PST 23
Peak memory 211080 kb
Host smart-82a87f58-52ec-4d67-9916-cb93b0edbc2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69639497777983797338413316679783976063460960242834321249497674974900089448855 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.69639497777983797338413316679783976063460960242834321249497674974900089448855
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.60641234724147594727654301993503996532336744988820948429939130386071912656932
Short name T333
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.59 seconds
Started Nov 22 12:36:31 PM PST 23
Finished Nov 22 12:42:17 PM PST 23
Peak memory 237648 kb
Host smart-1d040fdf-6b2c-4567-a7ff-1188312c4625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60641234724147594727654301993503996532336744988820948429939130386071912656932 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.6064123472414759472765430199350399653233674498882094842993
9130386071912656932
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.46878634707367041059070877788202297672613990131107342067876995996887227500151
Short name T195
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.07 seconds
Started Nov 22 12:36:34 PM PST 23
Finished Nov 22 12:37:01 PM PST 23
Peak memory 211440 kb
Host smart-1b8cc600-f4b0-4e16-a3e6-a73bbd4bae65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46878634707367041059070877788202297672613990131107342067876995996887227500151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.rom_ctrl_kmac_err_chk.46878634707367041059070877788202297672613990131107342067876995996887227500151
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.115682122937746882702795697665609107842765306498005787146179565399388898376604
Short name T130
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.47 seconds
Started Nov 22 12:36:30 PM PST 23
Finished Nov 22 12:36:44 PM PST 23
Peak memory 211092 kb
Host smart-c1ea60a5-572b-4eaa-94be-423a5f42d9fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115682122937746882702795697665609107842765306498005787146179565399388898376604 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.115682122937746882702795697665609107842765306498005787146179565399388898376604
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.21696080942003913548611692251725806498752622010919559381829312620498892723909
Short name T221
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.72 seconds
Started Nov 22 12:36:25 PM PST 23
Finished Nov 22 12:36:55 PM PST 23
Peak memory 212724 kb
Host smart-a2a3df11-4dd3-4dad-9eb0-adc151079761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21696080942003913548611692251725806498752622010919559381829312620498892723909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.rom_ctrl_smoke.21696080942003913548611692251725806498752622010919559381829312620498892723909
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.38929164330385160386987887183007558513440996316720154781859236981771524935581
Short name T122
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.36 seconds
Started Nov 22 12:36:32 PM PST 23
Finished Nov 22 12:37:15 PM PST 23
Peak memory 212880 kb
Host smart-84370c0b-43b9-4b35-a267-f8ad16939435
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389291643303851603869878871830075585134409963167201547818592369
81771524935581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.389291643303851603869878871830075585134409963167201
54781859236981771524935581
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.105613947983513618479449003742542295343164879092809935608040279891114134793150
Short name T342
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.39 seconds
Started Nov 22 12:36:30 PM PST 23
Finished Nov 22 12:36:44 PM PST 23
Peak memory 211076 kb
Host smart-6bda55dc-349a-4df1-9801-67288b2946c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105613947983513618479449003742542295343164879092809935608040279891114134793150 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.105613947983513618479449003742542295343164879092809935608040279891114134793150
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.51035411385014879981698774986489396313769762525817595405142222606282408565274
Short name T9
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.5 seconds
Started Nov 22 12:36:30 PM PST 23
Finished Nov 22 12:42:19 PM PST 23
Peak memory 237640 kb
Host smart-bd1d5ac7-07a8-474a-8959-bf66cc59b4fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51035411385014879981698774986489396313769762525817595405142222606282408565274 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.5103541138501487998169877498648939631376976252581759540514
2222606282408565274
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.76077780997691024923951141727469544917578832983181121091943824548370175317581
Short name T322
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.34 seconds
Started Nov 22 12:37:11 PM PST 23
Finished Nov 22 12:37:46 PM PST 23
Peak memory 210144 kb
Host smart-6355a647-a0e7-41a3-a734-5af896e9d522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76077780997691024923951141727469544917578832983181121091943824548370175317581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.rom_ctrl_kmac_err_chk.76077780997691024923951141727469544917578832983181121091943824548370175317581
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.100611658913658336140572823221596677777754674923564568506442969163996474632934
Short name T97
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.22 seconds
Started Nov 22 12:36:41 PM PST 23
Finished Nov 22 12:36:55 PM PST 23
Peak memory 211144 kb
Host smart-5f64da2b-cdaa-45d5-b95a-ad0713e53852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100611658913658336140572823221596677777754674923564568506442969163996474632934 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.100611658913658336140572823221596677777754674923564568506442969163996474632934
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.84444626298310007509077287740630472523413618702697026542663300621670366886346
Short name T281
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.66 seconds
Started Nov 22 12:36:28 PM PST 23
Finished Nov 22 12:36:58 PM PST 23
Peak memory 212748 kb
Host smart-da300434-81ad-4abb-bf32-dfb7beb6b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84444626298310007509077287740630472523413618702697026542663300621670366886346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.rom_ctrl_smoke.84444626298310007509077287740630472523413618702697026542663300621670366886346
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.107201068344283857145871352392395333970638325854571900406985104742710773982418
Short name T318
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.65 seconds
Started Nov 22 12:37:15 PM PST 23
Finished Nov 22 12:38:02 PM PST 23
Peak memory 212164 kb
Host smart-b28174bd-6d09-4551-8957-929ead93cc16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107201068344283857145871352392395333970638325854571900406985104
742710773982418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.10720106834428385714587135239239533397063832585457
1900406985104742710773982418
Directory /workspace/9.rom_ctrl_stress_all/latest
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