Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	229944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2407819

1

T20

103

T21

347

T22

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	656974	1			T20	23		T21	134		T22	8
values[0x0]	918744	1			T20	31		T21	174		T22	11
values[0x1]	1062045	1			T20	51		T21	191		T22	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	101875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2535888

1

T20

105

T21

394

T22

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9348	1			T20	42		T21	2		T23	1
valid_sources[0x01]	10267	1			T21	3		T23	2		T25	2
valid_sources[0x02]	9543	1			T23	10		T24	2		T66	9
valid_sources[0x03]	9542	1			T21	2		T23	1		T24	3
valid_sources[0x04]	10402	1			T21	2		T26	4		T59	1
valid_sources[0x05]	10621	1			T21	1		T23	4		T26	4
valid_sources[0x06]	9704	1			T21	3		T23	9		T59	2
valid_sources[0x07]	10419	1			T21	2		T24	4		T28	1
valid_sources[0x08]	9480	1			T21	4		T24	3		T28	1
valid_sources[0x09]	11440	1			T21	1		T24	5		T26	3
valid_sources[0x0a]	11234	1			T23	2		T28	2		T59	6
valid_sources[0x0b]	11134	1			T28	2		T60	1		T53	3
valid_sources[0x0c]	9767	1			T21	1		T23	5		T24	6
valid_sources[0x0d]	11079	1			T21	4		T23	10		T60	1
valid_sources[0x0e]	10753	1			T21	1		T59	2		T60	1
valid_sources[0x0f]	9424	1			T21	1		T25	3		T26	2
valid_sources[0x10]	10569	1			T23	1		T26	15		T52	1
valid_sources[0x11]	9785	1			T21	1		T26	2		T28	1
valid_sources[0x12]	11148	1			T25	1		T60	1		T74	1
valid_sources[0x13]	9709	1			T21	5		T23	6		T26	1
valid_sources[0x14]	10842	1			T21	2		T24	1		T26	4
valid_sources[0x15]	9851	1			T23	2		T24	2		T59	3
valid_sources[0x16]	10983	1			T26	3		T52	1		T60	1
valid_sources[0x17]	9993	1			T21	2		T23	5		T25	11
valid_sources[0x18]	9962	1			T21	3		T23	1		T25	1
valid_sources[0x19]	9635	1			T21	4		T23	2		T24	5
valid_sources[0x1a]	11505	1			T21	7		T23	2		T26	4
valid_sources[0x1b]	9816	1			T23	3		T59	1		T66	20
valid_sources[0x1c]	9498	1			T21	1		T22	1		T23	5
valid_sources[0x1d]	10708	1			T21	3		T24	3		T26	1
valid_sources[0x1e]	9620	1			T21	1		T23	16		T24	6
valid_sources[0x1f]	9543	1			T21	1		T23	1		T24	6
valid_sources[0x20]	10110	1			T21	1		T23	4		T25	3
valid_sources[0x21]	10733	1			T20	28		T21	5		T25	4
valid_sources[0x22]	10838	1			T21	3		T25	2		T26	15
valid_sources[0x23]	9719	1			T21	3		T23	4		T26	3
valid_sources[0x24]	9618	1			T21	1		T23	9		T26	1
valid_sources[0x25]	10138	1			T21	3		T26	1		T60	1
valid_sources[0x26]	10633	1			T21	2		T24	5		T25	2
valid_sources[0x27]	9728	1			T23	2		T24	2		T26	1
valid_sources[0x28]	9990	1			T21	4		T23	1		T26	3
valid_sources[0x29]	9562	1			T21	4		T23	3		T60	3
valid_sources[0x2a]	11513	1			T21	2		T59	4		T74	1
valid_sources[0x2b]	11091	1			T24	11		T28	2		T59	3
valid_sources[0x2c]	11442	1			T21	3		T23	5		T90	1
valid_sources[0x2d]	9949	1			T21	3		T22	4		T24	7
valid_sources[0x2e]	11267	1			T21	1		T23	5		T62	4
valid_sources[0x2f]	9792	1			T23	1		T26	5		T52	1
valid_sources[0x30]	10027	1			T21	2		T24	21		T25	1
valid_sources[0x31]	9798	1			T21	2		T24	1		T26	2
valid_sources[0x32]	11006	1			T21	3		T26	10		T55	1
valid_sources[0x33]	9933	1			T21	1		T26	1		T28	2
valid_sources[0x34]	10462	1			T21	1		T23	2		T24	6
valid_sources[0x35]	9832	1			T21	3		T26	2		T52	1
valid_sources[0x36]	10137	1			T21	5		T24	1		T26	4
valid_sources[0x37]	9777	1			T21	1		T26	1		T59	1
valid_sources[0x38]	9595	1			T21	1		T23	4		T24	1
valid_sources[0x39]	9693	1			T21	2		T27	2		T28	1
valid_sources[0x3a]	9019	1			T21	1		T23	3		T25	6
valid_sources[0x3b]	10429	1			T21	4		T28	1		T62	2
valid_sources[0x3c]	11204	1			T21	3		T26	6		T56	1
valid_sources[0x3d]	10687	1			T21	2		T29	10		T52	1
valid_sources[0x3e]	9601	1			T21	2		T23	2		T25	5
valid_sources[0x3f]	9689	1			T21	1		T23	13		T25	7
valid_sources[0x40]	10232	1			T21	3		T53	3		T67	1
valid_sources[0x41]	10833	1			T25	7		T26	2		T28	1
valid_sources[0x42]	10303	1			T21	1		T28	1		T59	1
valid_sources[0x43]	10906	1			T66	3		T74	1		T90	1
valid_sources[0x44]	10234	1			T23	6		T60	2		T90	1
valid_sources[0x45]	10883	1			T21	5		T23	3		T26	2
valid_sources[0x46]	11136	1			T21	3		T24	6		T26	8
valid_sources[0x47]	9585	1			T26	5		T59	1		T90	1
valid_sources[0x48]	10538	1			T28	1		T52	2		T60	1
valid_sources[0x49]	10582	1			T21	3		T25	15		T28	1
valid_sources[0x4a]	10661	1			T24	2		T59	3		T52	1
valid_sources[0x4b]	10718	1			T21	3		T23	1		T24	12
valid_sources[0x4c]	9679	1			T21	1		T24	2		T59	2
valid_sources[0x4d]	11445	1			T21	2		T23	1		T26	6
valid_sources[0x4e]	10628	1			T21	1		T55	1		T56	3
valid_sources[0x4f]	10950	1			T60	1		T53	1		T57	2
valid_sources[0x50]	9666	1			T21	1		T23	1		T28	3
valid_sources[0x51]	10161	1			T21	1		T23	1		T26	3
valid_sources[0x52]	9030	1			T21	4		T23	2		T24	9
valid_sources[0x53]	10407	1			T21	1		T60	1		T90	1
valid_sources[0x54]	9405	1			T23	1		T24	2		T59	2
valid_sources[0x55]	10662	1			T21	3		T23	4		T24	1
valid_sources[0x56]	10996	1			T23	3		T24	3		T25	17
valid_sources[0x57]	10988	1			T21	2		T26	1		T28	1
valid_sources[0x58]	9904	1			T21	3		T59	1		T55	4
valid_sources[0x59]	9879	1			T21	1		T23	2		T24	3
valid_sources[0x5a]	10611	1			T21	1		T23	3		T25	2
valid_sources[0x5b]	10858	1			T21	3		T26	1		T28	1
valid_sources[0x5c]	10720	1			T21	1		T23	3		T24	2
valid_sources[0x5d]	9563	1			T21	5		T23	3		T28	1
valid_sources[0x5e]	12023	1			T21	2		T23	3		T25	7
valid_sources[0x5f]	10483	1			T21	4		T24	2		T28	1
valid_sources[0x60]	9992	1			T21	1		T26	6		T60	3
valid_sources[0x61]	12020	1			T21	1		T25	5		T90	1
valid_sources[0x62]	10514	1			T21	1		T60	2		T74	2
valid_sources[0x63]	10088	1			T21	2		T60	5		T68	2
valid_sources[0x64]	10208	1			T21	1		T23	9		T26	11
valid_sources[0x65]	9621	1			T21	6		T24	4		T25	5
valid_sources[0x66]	10437	1			T24	3		T28	1		T90	1
valid_sources[0x67]	9418	1			T24	1		T62	2		T95	2
valid_sources[0x68]	9099	1			T21	1		T24	1		T26	22
valid_sources[0x69]	10371	1			T21	1		T26	5		T90	2
valid_sources[0x6a]	10000	1			T21	3		T24	5		T28	1
valid_sources[0x6b]	10311	1			T21	2		T25	11		T52	1
valid_sources[0x6c]	8916	1			T21	1		T23	7		T24	3
valid_sources[0x6d]	10238	1			T21	3		T24	3		T25	18
valid_sources[0x6e]	10325	1			T21	3		T23	8		T90	1
valid_sources[0x6f]	11102	1			T21	1		T26	4		T52	1
valid_sources[0x70]	9388	1			T21	2		T23	6		T52	1
valid_sources[0x71]	10973	1			T21	2		T23	2		T59	1
valid_sources[0x72]	10305	1			T21	1		T23	5		T24	2
valid_sources[0x73]	9163	1			T21	1		T23	3		T27	1
valid_sources[0x74]	10428	1			T23	5		T24	1		T25	4
valid_sources[0x75]	10267	1			T21	1		T23	1		T25	5
valid_sources[0x76]	10041	1			T23	3		T26	2		T28	1
valid_sources[0x77]	9967	1			T21	1		T23	1		T25	6
valid_sources[0x78]	9745	1			T21	3		T26	2		T60	1
valid_sources[0x79]	10270	1			T21	2		T24	3		T26	5
valid_sources[0x7a]	11467	1			T21	3		T28	2		T74	1
valid_sources[0x7b]	9745	1			T20	24		T21	6		T23	9
valid_sources[0x7c]	9823	1			T21	3		T23	1		T24	2
valid_sources[0x7d]	11242	1			T21	4		T23	4		T66	3
valid_sources[0x7e]	10443	1			T22	4		T26	1		T28	1
valid_sources[0x7f]	11188	1			T21	1		T66	6		T74	1
valid_sources[0x80]	9269	1			T23	8		T60	1		T56	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

608362

1

T20

23

T21

9

T22

6

values[0x0]

all_enables

biggest_size

900527

1

T20

31

T21

161

T22

11

values[0x1]

all_enables

biggest_size

898930

1

T20

49

T21

177

T22

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	533408	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2365100

1

T20

267

T21

1

T22

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	647336	1			T20	70		T21	11		T22	1
values[0x0]	930409	1			T20	106		T21	2		T23	3
values[0x1]	1320763	1			T20	138		T21	4		T22	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202094	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2696414

1

T20

302

T21

6

T22

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10695	1			T52	5		T55	1		T53	2
valid_sources[0x01]	11634	1			T20	1		T21	1		T111	2
valid_sources[0x02]	11433	1			T52	3		T55	1		T53	1
valid_sources[0x03]	11515	1			T20	2		T53	1		T61	1
valid_sources[0x04]	10607	1			T20	1		T52	3		T53	2
valid_sources[0x05]	10860	1			T52	1		T54	1		T62	2
valid_sources[0x06]	10992	1			T20	2		T52	3		T55	4
valid_sources[0x07]	11539	1			T20	1		T52	1		T54	2
valid_sources[0x08]	11682	1			T20	1		T55	2		T64	1
valid_sources[0x09]	11581	1			T20	1		T61	1		T112	1
valid_sources[0x0a]	10467	1			T20	1		T54	1		T64	1
valid_sources[0x0b]	11019	1			T53	1		T103	1		T112	2
valid_sources[0x0c]	12773	1			T20	2		T52	1		T53	1
valid_sources[0x0d]	12634	1			T52	2		T54	1		T57	1
valid_sources[0x0e]	10658	1			T20	1		T52	5		T53	4
valid_sources[0x0f]	10783	1			T20	4		T55	1		T53	1
valid_sources[0x10]	11320	1			T20	2		T52	7		T54	2
valid_sources[0x11]	11298	1			T20	1		T55	1		T61	2
valid_sources[0x12]	10259	1			T20	3		T55	1		T113	14
valid_sources[0x13]	11072	1			T20	2		T55	1		T53	1
valid_sources[0x14]	11433	1			T54	2		T64	1		T112	1
valid_sources[0x15]	11526	1			T20	2		T55	1		T54	1
valid_sources[0x16]	12022	1			T52	10		T64	3		T112	2
valid_sources[0x17]	12709	1			T20	1		T52	2		T54	1
valid_sources[0x18]	10563	1			T20	2		T25	6		T56	1
valid_sources[0x19]	10847	1			T20	2		T52	3		T62	2
valid_sources[0x1a]	11634	1			T25	1		T55	1		T53	1
valid_sources[0x1b]	11634	1			T20	1		T52	1		T55	1
valid_sources[0x1c]	11748	1			T20	2		T53	2		T54	1
valid_sources[0x1d]	10792	1			T52	7		T53	1		T57	1
valid_sources[0x1e]	12186	1			T20	3		T54	1		T64	3
valid_sources[0x1f]	12113	1			T20	1		T53	1		T54	1
valid_sources[0x20]	10703	1			T20	1		T55	1		T53	1
valid_sources[0x21]	11786	1			T52	2		T54	2		T57	1
valid_sources[0x22]	12364	1			T52	1		T55	1		T62	2
valid_sources[0x23]	11497	1			T52	3		T55	1		T54	1
valid_sources[0x24]	10965	1			T20	3		T55	1		T112	2
valid_sources[0x25]	11872	1			T20	1		T21	1		T54	1
valid_sources[0x26]	10872	1			T20	1		T55	1		T53	1
valid_sources[0x27]	10885	1			T20	1		T55	1		T61	1
valid_sources[0x28]	11962	1			T55	2		T54	1		T62	1
valid_sources[0x29]	10686	1			T20	1		T55	1		T53	1
valid_sources[0x2a]	10810	1			T20	1		T55	1		T61	1
valid_sources[0x2b]	11361	1			T52	2		T53	1		T54	2
valid_sources[0x2c]	10432	1			T53	2		T112	2		T114	4
valid_sources[0x2d]	12003	1			T52	13		T55	1		T54	2
valid_sources[0x2e]	11776	1			T53	1		T54	1		T64	1
valid_sources[0x2f]	10267	1			T20	1		T54	1		T112	1
valid_sources[0x30]	10794	1			T55	1		T53	3		T64	1
valid_sources[0x31]	11862	1			T20	1		T53	2		T54	1
valid_sources[0x32]	10670	1			T20	2		T52	7		T53	1
valid_sources[0x33]	10529	1			T20	1		T56	1		T64	1
valid_sources[0x34]	10653	1			T20	1		T64	1		T112	1
valid_sources[0x35]	11085	1			T20	1		T52	4		T53	1
valid_sources[0x36]	11592	1			T20	2		T52	7		T55	2
valid_sources[0x37]	11176	1			T20	2		T22	1		T64	2
valid_sources[0x38]	11809	1			T20	3		T55	2		T53	1
valid_sources[0x39]	11402	1			T20	1		T52	12		T54	1
valid_sources[0x3a]	10527	1			T20	3		T53	1		T54	1
valid_sources[0x3b]	11580	1			T52	5		T58	2		T64	1
valid_sources[0x3c]	13008	1			T20	2		T54	2		T64	3
valid_sources[0x3d]	11843	1			T20	2		T55	1		T54	2
valid_sources[0x3e]	10693	1			T20	2		T25	5		T54	1
valid_sources[0x3f]	12491	1			T64	1		T115	1		T112	1
valid_sources[0x40]	11518	1			T20	2		T52	6		T54	1
valid_sources[0x41]	10765	1			T20	1		T52	1		T55	1
valid_sources[0x42]	9937	1			T20	1		T55	2		T54	1
valid_sources[0x43]	11738	1			T20	4		T55	1		T62	1
valid_sources[0x44]	10577	1			T20	3		T52	1		T53	1
valid_sources[0x45]	11347	1			T20	2		T55	1		T57	2
valid_sources[0x46]	11832	1			T20	1		T52	3		T53	1
valid_sources[0x47]	10519	1			T25	5		T52	1		T55	1
valid_sources[0x48]	11026	1			T20	1		T112	1		T116	3
valid_sources[0x49]	12162	1			T20	1		T52	2		T54	2
valid_sources[0x4a]	12303	1			T52	5		T57	1		T58	1
valid_sources[0x4b]	10495	1			T20	1		T53	2		T64	1
valid_sources[0x4c]	10637	1			T53	2		T56	1		T54	1
valid_sources[0x4d]	11162	1			T20	1		T52	1		T53	1
valid_sources[0x4e]	10959	1			T20	1		T52	1		T53	1
valid_sources[0x4f]	10781	1			T20	2		T64	1		T69	1
valid_sources[0x50]	11635	1			T20	1		T54	2		T58	1
valid_sources[0x51]	13044	1			T20	1		T52	5		T53	1
valid_sources[0x52]	10934	1			T20	3		T26	40		T52	1
valid_sources[0x53]	11624	1			T20	2		T55	2		T54	2
valid_sources[0x54]	11508	1			T52	21		T55	1		T54	1
valid_sources[0x55]	10574	1			T20	1		T55	2		T53	1
valid_sources[0x56]	11330	1			T20	2		T53	1		T54	1
valid_sources[0x57]	10926	1			T20	1		T111	3		T115	1
valid_sources[0x58]	11468	1			T55	2		T64	1		T69	1
valid_sources[0x59]	12548	1			T20	1		T52	2		T54	4
valid_sources[0x5a]	12267	1			T52	3		T54	1		T62	2
valid_sources[0x5b]	10734	1			T20	3		T53	1		T64	2
valid_sources[0x5c]	11435	1			T20	1		T55	1		T54	1
valid_sources[0x5d]	11705	1			T20	2		T52	1		T64	2
valid_sources[0x5e]	10897	1			T20	2		T52	7		T53	1
valid_sources[0x5f]	11162	1			T20	1		T52	3		T64	2
valid_sources[0x60]	10542	1			T53	2		T54	2		T112	2
valid_sources[0x61]	12126	1			T20	3		T54	1		T61	1
valid_sources[0x62]	10349	1			T20	1		T55	1		T54	1
valid_sources[0x63]	11476	1			T20	2		T54	2		T112	1
valid_sources[0x64]	10652	1			T20	1		T52	1		T53	1
valid_sources[0x65]	10965	1			T52	2		T55	1		T53	1
valid_sources[0x66]	10856	1			T20	1		T55	1		T54	1
valid_sources[0x67]	12999	1			T53	1		T54	2		T61	1
valid_sources[0x68]	12173	1			T20	3		T53	1		T72	1
valid_sources[0x69]	10934	1			T20	2		T54	3		T61	1
valid_sources[0x6a]	11789	1			T20	3		T53	2		T54	2
valid_sources[0x6b]	12079	1			T54	1		T69	1		T112	1
valid_sources[0x6c]	10911	1			T20	1		T54	1		T57	4
valid_sources[0x6d]	11617	1			T52	2		T53	1		T64	5
valid_sources[0x6e]	11361	1			T20	1		T54	1		T64	3
valid_sources[0x6f]	11338	1			T55	1		T53	1		T54	1
valid_sources[0x70]	11418	1			T20	1		T55	1		T54	2
valid_sources[0x71]	11249	1			T20	3		T25	4		T52	9
valid_sources[0x72]	12188	1			T20	1		T52	2		T55	1
valid_sources[0x73]	11614	1			T52	1		T54	1		T57	1
valid_sources[0x74]	11865	1			T20	2		T52	5		T53	1
valid_sources[0x75]	10540	1			T20	1		T52	1		T54	1
valid_sources[0x76]	10839	1			T52	12		T61	2		T64	2
valid_sources[0x77]	11482	1			T20	2		T117	1		T70	1
valid_sources[0x78]	11851	1			T52	2		T55	1		T54	2
valid_sources[0x79]	10968	1			T52	5		T55	1		T54	2
valid_sources[0x7a]	11400	1			T20	1		T53	1		T54	1
valid_sources[0x7b]	11568	1			T52	5		T53	2		T64	1
valid_sources[0x7c]	10292	1			T54	1		T64	2		T112	2
valid_sources[0x7d]	12102	1			T55	1		T53	1		T54	2
valid_sources[0x7e]	11148	1			T20	1		T52	3		T61	1
valid_sources[0x7f]	12235	1			T55	2		T53	1		T64	2
valid_sources[0x80]	12142	1			T52	2		T55	1		T53	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

596191

1

T20

70

T21

1

T22

1

values[0x0]

all_enables

biggest_size

884707

1

T20

102

T23

1

T52

164

values[0x1]

all_enables

biggest_size

884202

1

T20

95

T22

1

T52

157