Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6595551

1

T20

539

T21

18

T22

12

full_word

2837148

1

T20

308

T21

2

T22

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	9432379	1			T20	847		T22	14		T24	40
auto[TlIntgErrCmd]	102	1			T21	6		T23	8		T58	6
auto[TlIntgErrData]	116	1			T21	8		T23	7		T58	6
auto[TlIntgErrBoth]	102	1			T21	6		T23	5		T58	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1132497

1

T20

96

T21

12

T22

2

auto[1]

8300202

1

T20

751

T21

8

T22

12

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	478230	1			T20	16		T22	1		T52	50
auto[TlIntgErrNone]	partial	auto[1]	6117026	1			T20	523		T22	11		T52	465
auto[TlIntgErrNone]	full_word	auto[0]	654111	1			T20	80		T22	1		T24	40
auto[TlIntgErrNone]	full_word	auto[1]	2183012	1			T20	228		T22	1		T52	356
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T21	3		T23	2		T58	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T21	2		T23	5		T58	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T21	1		T23	1		T106	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T62	1		T73	1		T103	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T21	4		T23	3		T58	4
auto[TlIntgErrData]	partial	auto[1]	54	1			T21	3		T23	4		T62	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T21	1		T58	2		T62	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T73	1		T107	1		T108	2
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T21	3		T23	1		T58	4
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T21	3		T23	2		T58	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T106	1		T109	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T23	2		T107	1		-	-