Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.53	97.11	93.27	97.88	100.00	99.02	97.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	98.21	92.86		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_rom_top	100.00	100.00				100.00	100.00
u_tl_adapter_rom	94.26	91.56	84.30	99.07		96.39	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	453	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
117	1	1
122	1	1
123	1	1
124	1	1
125	1	1
128	1	1
222	1	1
268	1	1
323	1	1
425	8	8
426	8	8
428	8	8
429	8	8
431	8	8
432	8	8
436	1	1
438	1	1
441	1	1
442	1	1
443	1	1
444	1	1
449	1	1
453	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       222
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       268
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T10
1	1	Covered	T3,T4,T5

 LINE       429
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       436
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T35,T36,T37
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       438
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T10
1	0	Covered	T2,T4,T7

 LINE       449
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T9

 LINE       453
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T8,T10
0	1	0	Covered	T2,T4,T7
1	0	0	Covered	T35,T36,T37

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rst_ni	Yes	Yes	T21,T22,T23	Yes	T20,T21,T22	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_i.a_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rom_tl_o.a_ready	Yes	Yes	T21,T22,T23	Yes	T20,T21,T22	OUTPUT
rom_tl_o.d_error	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T20,T22,T24	Yes	T20,T22,T24	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_i.a_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
regs_tl_o.a_ready	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
regs_tl_o.d_error	Yes	Yes	T21,T22,T23	Yes	T20,T21,T22	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T20,T21,*T22	Yes	T20,T21,T22	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T21,T22,T23	Yes	T20,T21,T22	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T20,T21,T23	Yes	T20,T21,T23	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T21,T23,T24	Yes	T21,T23,T24	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T21,T23,T24	Yes	T21,T23,T24	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T20,T21,T22	Yes	T24,T25,T26	OUTPUT
keymgr_data_o.valid	Yes	Yes	T24,T25,T26	Yes	T20,T21,T22	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T24,T25,T26	Yes	T20,T21,T22	OUTPUT
kmac_data_i.error	No	Yes	T2,T7,T11	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
kmac_data_i.done	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
kmac_data_i.ready	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
kmac_data_o.last	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	222	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	222	(tl_rom_h2d_upstream.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	284904017	284718959	0	0
BusRomIndicesMatch_A	284884606	284706398	0	0
FpvSecCmFifoRptrCheck_A	284904017	0	0	0
FpvSecCmFifoWptrCheck_A	284904017	0	0	0
FpvSecCmRegWeOnehotCheck_A	284904017	70	0	0
KeymgrDataODataKnown_A	284904017	123580419	0	0
KeymgrDataODataKnown_AKnownEnable	284904017	284718959	0	0
KeymgrDataOValidKnown_A	284904017	284718959	0	0
KeymgrValidChk_A	284904017	0	0	340
KmacDataODataKnown_A	284904017	160995249	0	0
KmacDataODataKnown_AKnownEnable	284904017	284718959	0	0
KmacDataOValidKnown_A	284904017	284718959	0	0
PwrmgrDataChk_A	284904017	0	0	340
PwrmgrDataOKnown_A	284904017	284718959	0	0
RegsTlOAReadyKnown_A	284904017	284718959	0	0
RegsTlODDataKnown_A	284904017	20707081	0	0
RegsTlODDataKnown_AKnownEnable	284904017	284718959	0	0
RegsTlODValidKnown_A	284904017	284718959	0	0
RomTlOAReadyKnown_A	284904017	284718959	0	0
RomTlODDataKnown_A	284904017	17942997	0	0
RomTlODDataKnown_AKnownEnable	284904017	284718959	0	0
RomTlODValidKnown_A	284904017	284718959	0	0
StabilityChkKmac_A	284904017	160992555	0	0
StabilityChkkeymgr_A	284904017	123579085	0	0
TlAccessChk_A	284904017	161138540	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	284904017	70	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	284904017	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	284904017	543	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	284904017	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284884606	284706398	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251286	251078	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	530688	528625	0	0
T9	16703	16630	0	0
T10	154344	154161	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	70	0	0
T35	14057	10	0	0
T36	24837	20	0	0
T37	0	10	0	0
T39	0	10	0	0
T40	0	20	0	0
T41	181747	0	0	0
T42	676350	0	0	0
T43	505824	0	0	0
T44	27768	0	0	0
T45	228045	0	0	0
T46	17418	0	0	0
T47	207358	0	0	0
T48	199065	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	123580419	0	0
T1	8310	51	0	0
T2	115090	260	0	0
T3	9122	846	0	0
T4	251337	13419	0	0
T5	9973	1689	0	0
T6	8314	51	0	0
T7	16646	53	0	0
T8	531099	230	0	0
T9	16703	275	0	0
T10	154383	24155	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	0	0	340

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	160995249	0	0
T1	8310	8184	0	0
T2	115090	114581	0	0
T3	9122	8184	0	0
T4	251337	249629	0	0
T5	9973	8184	0	0
T6	8314	8184	0	0
T7	16646	16368	0	0
T8	531099	527089	0	0
T9	16703	16334	0	0
T10	154383	151592	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	0	0	340

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	20707081	0	0
T1	8310	12	0	0
T2	115090	3	0	0
T3	9122	0	0	0
T4	251337	25	0	0
T5	9973	0	0	0
T6	8314	39	0	0
T7	16646	1	0	0
T8	531099	25	0	0
T9	16703	1	0	0
T10	154383	96	0	0
T11	0	1	0	0
T15	0	32	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	17942997	0	0
T3	9122	219	0	0
T4	251337	9	0	0
T5	9973	380	0	0
T6	8314	0	0	0
T7	16646	0	0	0
T8	531099	12	0	0
T9	16703	0	0	0
T10	154383	6	0	0
T11	16649	0	0	0
T12	0	653280	0	0
T15	330859	411	0	0
T16	0	886	0	0
T17	0	200	0	0
T19	0	9	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	284718959	0	0
T1	8310	8256	0	0
T2	115090	114983	0	0
T3	9122	9051	0	0
T4	251337	251110	0	0
T5	9973	9894	0	0
T6	8314	8256	0	0
T7	16646	16478	0	0
T8	531099	528751	0	0
T9	16703	16630	0	0
T10	154383	154185	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	160992555	0	0
T1	8310	8183	0	0
T2	115090	114579	0	0
T3	9122	8183	0	0
T4	251337	249626	0	0
T5	9973	8183	0	0
T6	8314	8183	0	0
T7	16646	16366	0	0
T8	531099	527058	0	0
T9	16703	16333	0	0
T10	154383	151589	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	123579085	0	0
T1	8310	50	0	0
T2	115090	259	0	0
T3	9122	845	0	0
T4	251337	13407	0	0
T5	9973	1688	0	0
T6	8314	50	0	0
T7	16646	52	0	0
T8	531099	222	0	0
T9	16703	274	0	0
T10	154383	24142	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	161138540	0	0
T1	8310	8205	0	0
T2	115090	114723	0	0
T3	9122	8205	0	0
T4	251337	249768	0	0
T5	9973	8205	0	0
T6	8314	8205	0	0
T7	16646	16425	0	0
T8	531099	528521	0	0
T9	16703	16355	0	0
T10	154383	151770	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	70	0	0
T35	14057	10	0	0
T36	24837	20	0	0
T37	0	10	0	0
T39	0	10	0	0
T40	0	20	0	0
T41	181747	0	0	0
T42	676350	0	0	0
T43	505824	0	0	0
T44	27768	0	0	0
T45	228045	0	0	0
T46	17418	0	0	0
T47	207358	0	0	0
T48	199065	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	543	0	0
T4	251337	5	0	0
T5	9973	0	0	0
T6	8314	0	0	0
T7	16646	0	0	0
T8	531099	6	0	0
T9	16703	0	0	0
T10	154383	5	0	0
T11	16649	0	0	0
T15	330859	0	0	0
T19	208071	5	0	0
T35	0	10	0	0
T36	0	20	0	0
T47	0	10	0	0
T49	0	10	0	0
T50	0	5	0	0
T51	0	21	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	284904017	0	0	0