Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2072694

1

T25

18

T26

61

T27

119

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	566116	1			T25	2		T26	11		T27	13
values[0x0]	790750	1			T25	10		T26	26		T27	58
values[0x1]	916937	1			T25	8		T26	27		T27	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	89280	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2184523

1

T25

18

T26

61

T27

119

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8702	1			T28	8		T30	3		T56	1
valid_sources[0x01]	7765	1			T34	1		T58	2		T69	1
valid_sources[0x02]	9524	1			T30	5		T34	1		T58	2
valid_sources[0x03]	8570	1			T30	2		T34	3		T58	2
valid_sources[0x04]	9680	1			T26	1		T30	2		T33	2
valid_sources[0x05]	9142	1			T26	2		T29	4		T30	4
valid_sources[0x06]	8385	1			T26	1		T27	4		T30	2
valid_sources[0x07]	9156	1			T30	1		T34	4		T56	1
valid_sources[0x08]	8461	1			T30	1		T56	1		T57	1
valid_sources[0x09]	10028	1			T27	23		T30	3		T33	2
valid_sources[0x0a]	8934	1			T30	5		T34	2		T57	2
valid_sources[0x0b]	9222	1			T30	3		T34	2		T56	2
valid_sources[0x0c]	9130	1			T26	1		T30	4		T34	2
valid_sources[0x0d]	8120	1			T30	3		T33	1		T58	1
valid_sources[0x0e]	8721	1			T27	20		T30	3		T34	1
valid_sources[0x0f]	8714	1			T30	6		T34	2		T57	1
valid_sources[0x10]	8732	1			T30	5		T34	2		T56	1
valid_sources[0x11]	9519	1			T30	4		T33	2		T34	2
valid_sources[0x12]	8607	1			T30	3		T33	2		T34	1
valid_sources[0x13]	9176	1			T30	8		T34	1		T56	2
valid_sources[0x14]	9575	1			T30	1		T56	1		T57	6
valid_sources[0x15]	9253	1			T26	1		T30	4		T57	1
valid_sources[0x16]	8422	1			T26	3		T30	3		T34	1
valid_sources[0x17]	8187	1			T30	2		T34	1		T57	1
valid_sources[0x18]	10265	1			T29	1		T30	3		T34	1
valid_sources[0x19]	8445	1			T33	2		T56	1		T57	3
valid_sources[0x1a]	9569	1			T30	2		T34	1		T56	2
valid_sources[0x1b]	9075	1			T30	4		T34	2		T56	4
valid_sources[0x1c]	8616	1			T26	1		T30	1		T58	1
valid_sources[0x1d]	8773	1			T58	1		T69	1		T64	1
valid_sources[0x1e]	8280	1			T30	4		T57	1		T58	3
valid_sources[0x1f]	9744	1			T30	3		T34	1		T57	1
valid_sources[0x20]	8755	1			T26	2		T30	7		T34	1
valid_sources[0x21]	8192	1			T30	2		T32	74		T34	1
valid_sources[0x22]	8192	1			T30	2		T34	1		T56	3
valid_sources[0x23]	8328	1			T30	2		T34	5		T57	3
valid_sources[0x24]	8954	1			T30	4		T33	1		T34	3
valid_sources[0x25]	8211	1			T26	1		T30	2		T33	1
valid_sources[0x26]	9054	1			T30	3		T34	2		T57	1
valid_sources[0x27]	9406	1			T34	2		T57	1		T68	1
valid_sources[0x28]	8330	1			T30	4		T33	2		T34	1
valid_sources[0x29]	8656	1			T30	4		T31	108		T33	3
valid_sources[0x2a]	9149	1			T30	6		T33	1		T56	1
valid_sources[0x2b]	8841	1			T29	2		T30	2		T56	1
valid_sources[0x2c]	9621	1			T30	5		T33	1		T57	1
valid_sources[0x2d]	8521	1			T30	3		T57	1		T58	2
valid_sources[0x2e]	8459	1			T26	2		T30	1		T56	1
valid_sources[0x2f]	8427	1			T30	2		T57	2		T68	1
valid_sources[0x30]	9600	1			T27	5		T30	4		T34	1
valid_sources[0x31]	9145	1			T26	2		T33	2		T34	2
valid_sources[0x32]	9202	1			T33	3		T56	1		T68	1
valid_sources[0x33]	8294	1			T25	10		T26	1		T30	4
valid_sources[0x34]	9285	1			T26	1		T30	3		T57	2
valid_sources[0x35]	9380	1			T30	4		T32	1		T57	1
valid_sources[0x36]	9412	1			T26	1		T27	2		T30	4
valid_sources[0x37]	8905	1			T30	8		T33	1		T57	1
valid_sources[0x38]	8694	1			T30	4		T34	1		T56	1
valid_sources[0x39]	8557	1			T30	5		T34	1		T72	1
valid_sources[0x3a]	8145	1			T26	1		T30	4		T34	1
valid_sources[0x3b]	8244	1			T30	2		T68	1		T58	3
valid_sources[0x3c]	9383	1			T29	4		T30	2		T34	1
valid_sources[0x3d]	8110	1			T27	8		T30	2		T56	3
valid_sources[0x3e]	9225	1			T30	3		T31	10		T34	1
valid_sources[0x3f]	8519	1			T30	4		T57	2		T58	2
valid_sources[0x40]	9633	1			T30	5		T69	1		T77	8
valid_sources[0x41]	9112	1			T27	4		T30	6		T31	10
valid_sources[0x42]	8907	1			T26	2		T29	4		T30	8
valid_sources[0x43]	8310	1			T30	1		T34	1		T68	2
valid_sources[0x44]	8613	1			T29	1		T30	3		T34	1
valid_sources[0x45]	9211	1			T29	1		T30	2		T34	2
valid_sources[0x46]	8769	1			T29	4		T30	5		T34	2
valid_sources[0x47]	8463	1			T33	2		T34	2		T56	1
valid_sources[0x48]	9326	1			T27	1		T30	1		T68	1
valid_sources[0x49]	8496	1			T30	4		T33	1		T34	1
valid_sources[0x4a]	8989	1			T30	1		T56	2		T57	1
valid_sources[0x4b]	9356	1			T30	3		T33	1		T56	2
valid_sources[0x4c]	8683	1			T30	2		T33	1		T34	1
valid_sources[0x4d]	8774	1			T26	1		T30	1		T34	1
valid_sources[0x4e]	9250	1			T30	3		T34	1		T58	1
valid_sources[0x4f]	8975	1			T27	1		T30	2		T34	1
valid_sources[0x50]	9082	1			T30	4		T33	3		T34	2
valid_sources[0x51]	10370	1			T26	2		T30	1		T34	1
valid_sources[0x52]	8686	1			T26	2		T34	1		T58	4
valid_sources[0x53]	8165	1			T30	3		T56	1		T57	2
valid_sources[0x54]	8389	1			T30	3		T33	1		T34	1
valid_sources[0x55]	9299	1			T30	6		T33	2		T34	1
valid_sources[0x56]	7937	1			T30	6		T34	3		T57	1
valid_sources[0x57]	8244	1			T30	1		T33	2		T34	1
valid_sources[0x58]	8493	1			T30	4		T33	1		T34	1
valid_sources[0x59]	8964	1			T30	2		T33	2		T34	1
valid_sources[0x5a]	7966	1			T30	2		T34	1		T56	10
valid_sources[0x5b]	9087	1			T30	3		T33	2		T41	1
valid_sources[0x5c]	8465	1			T26	1		T30	2		T34	1
valid_sources[0x5d]	9872	1			T30	4		T34	1		T56	3
valid_sources[0x5e]	9067	1			T30	4		T34	1		T57	1
valid_sources[0x5f]	8431	1			T30	5		T56	3		T69	1
valid_sources[0x60]	9085	1			T30	5		T68	1		T58	2
valid_sources[0x61]	8963	1			T30	2		T34	1		T57	3
valid_sources[0x62]	8628	1			T29	1		T30	3		T31	10
valid_sources[0x63]	8809	1			T30	3		T56	3		T57	2
valid_sources[0x64]	9551	1			T30	2		T31	10		T34	1
valid_sources[0x65]	8725	1			T25	10		T30	2		T57	2
valid_sources[0x66]	8584	1			T30	5		T34	1		T58	2
valid_sources[0x67]	8222	1			T34	1		T56	1		T57	1
valid_sources[0x68]	8229	1			T30	2		T56	1		T58	2
valid_sources[0x69]	8473	1			T30	2		T34	1		T68	1
valid_sources[0x6a]	8481	1			T27	2		T29	3		T30	3
valid_sources[0x6b]	9240	1			T29	1		T30	1		T34	1
valid_sources[0x6c]	8639	1			T26	1		T30	2		T34	2
valid_sources[0x6d]	8954	1			T30	3		T58	1		T60	1
valid_sources[0x6e]	9324	1			T30	4		T56	3		T58	1
valid_sources[0x6f]	9230	1			T30	1		T57	1		T58	2
valid_sources[0x70]	8727	1			T30	2		T33	1		T34	1
valid_sources[0x71]	9076	1			T30	3		T33	2		T34	1
valid_sources[0x72]	8426	1			T30	7		T33	1		T56	2
valid_sources[0x73]	8432	1			T26	2		T29	2		T30	1
valid_sources[0x74]	9205	1			T29	1		T30	2		T56	1
valid_sources[0x75]	8941	1			T26	1		T30	3		T33	1
valid_sources[0x76]	9349	1			T30	3		T60	3		T69	1
valid_sources[0x77]	8498	1			T26	1		T30	4		T34	2
valid_sources[0x78]	8964	1			T29	1		T30	3		T57	1
valid_sources[0x79]	9746	1			T30	4		T56	1		T57	2
valid_sources[0x7a]	9651	1			T26	1		T33	1		T56	4
valid_sources[0x7b]	8463	1			T30	6		T58	2		T77	5
valid_sources[0x7c]	9050	1			T30	3		T57	1		T58	1
valid_sources[0x7d]	8888	1			T30	3		T34	2		T69	1
valid_sources[0x7e]	8570	1			T30	1		T58	1		T69	1
valid_sources[0x7f]	8135	1			T30	4		T33	1		T56	4
valid_sources[0x80]	9879	1			T30	5		T33	3		T34	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

523649

1

T25

1

T26

8

T27

13

values[0x0]

all_enables

biggest_size

774806

1

T25

9

T26

26

T27

58

values[0x1]

all_enables

biggest_size

774239

1

T25

8

T26

27

T27

48

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	457456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2065777

1

T26

38

T28

16

T29

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	566329	1			T26	10		T28	3		T29	13
values[0x0]	812271	1			T26	16		T28	6		T29	16
values[0x1]	1144633	1			T26	14		T28	8		T29	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173929	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2349304

1

T26

39

T28

17

T29

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9659	1			T61	1		T62	1		T67	2
valid_sources[0x01]	9727	1			T30	1		T62	1		T108	3
valid_sources[0x02]	9871	1			T67	2		T113	1		T124	2
valid_sources[0x03]	8993	1			T30	1		T61	1		T62	2
valid_sources[0x04]	9497	1			T30	2		T62	3		T125	8
valid_sources[0x05]	9539	1			T26	1		T30	2		T31	1
valid_sources[0x06]	11048	1			T30	3		T62	2		T72	1
valid_sources[0x07]	9476	1			T29	27		T30	2		T62	1
valid_sources[0x08]	10259	1			T26	1		T108	2		T125	2
valid_sources[0x09]	9814	1			T30	2		T62	2		T67	2
valid_sources[0x0a]	10586	1			T30	4		T62	2		T108	6
valid_sources[0x0b]	9830	1			T30	1		T62	2		T67	3
valid_sources[0x0c]	9619	1			T26	2		T30	1		T64	1
valid_sources[0x0d]	9915	1			T26	1		T62	2		T67	1
valid_sources[0x0e]	10862	1			T30	1		T108	4		T125	3
valid_sources[0x0f]	9660	1			T62	1		T63	1		T123	2
valid_sources[0x10]	11198	1			T30	3		T61	2		T62	1
valid_sources[0x11]	9051	1			T32	1		T56	113		T58	1
valid_sources[0x12]	10539	1			T62	1		T63	1		T125	3
valid_sources[0x13]	10059	1			T32	1		T62	2		T63	2
valid_sources[0x14]	9758	1			T30	2		T62	3		T63	3
valid_sources[0x15]	9372	1			T62	2		T67	2		T108	1
valid_sources[0x16]	9267	1			T30	3		T58	1		T64	1
valid_sources[0x17]	10130	1			T26	1		T62	2		T108	1
valid_sources[0x18]	8737	1			T30	2		T31	2		T32	1
valid_sources[0x19]	9857	1			T26	1		T61	2		T126	2
valid_sources[0x1a]	10537	1			T58	1		T62	3		T67	2
valid_sources[0x1b]	9561	1			T30	1		T72	1		T67	2
valid_sources[0x1c]	9605	1			T30	2		T62	1		T108	4
valid_sources[0x1d]	11390	1			T30	1		T56	126		T62	2
valid_sources[0x1e]	9255	1			T32	1		T62	3		T66	3
valid_sources[0x1f]	9811	1			T30	3		T64	1		T62	2
valid_sources[0x20]	9696	1			T30	2		T62	1		T67	1
valid_sources[0x21]	10245	1			T30	1		T62	2		T63	2
valid_sources[0x22]	9301	1			T28	1		T30	1		T62	1
valid_sources[0x23]	9753	1			T26	1		T30	4		T62	1
valid_sources[0x24]	9032	1			T61	1		T62	2		T72	1
valid_sources[0x25]	9455	1			T63	2		T125	3		T124	7
valid_sources[0x26]	10026	1			T30	3		T123	1		T113	2
valid_sources[0x27]	10840	1			T30	1		T63	1		T73	1
valid_sources[0x28]	9407	1			T30	1		T62	1		T63	1
valid_sources[0x29]	9711	1			T62	1		T63	1		T72	1
valid_sources[0x2a]	9158	1			T30	1		T31	1		T72	1
valid_sources[0x2b]	9610	1			T30	1		T108	3		T125	2
valid_sources[0x2c]	9230	1			T30	1		T62	1		T67	2
valid_sources[0x2d]	9812	1			T26	1		T62	5		T108	1
valid_sources[0x2e]	8874	1			T62	3		T63	1		T125	2
valid_sources[0x2f]	10216	1			T30	3		T62	2		T63	1
valid_sources[0x30]	9517	1			T62	1		T63	1		T125	1
valid_sources[0x31]	9234	1			T30	3		T32	4		T62	4
valid_sources[0x32]	9251	1			T30	3		T31	1		T61	1
valid_sources[0x33]	9967	1			T62	3		T63	1		T72	1
valid_sources[0x34]	10863	1			T30	2		T62	2		T108	2
valid_sources[0x35]	10678	1			T26	2		T28	6		T31	1
valid_sources[0x36]	9578	1			T30	1		T61	1		T63	1
valid_sources[0x37]	10003	1			T26	2		T30	3		T61	3
valid_sources[0x38]	9300	1			T30	1		T31	1		T62	2
valid_sources[0x39]	9756	1			T30	2		T62	2		T123	1
valid_sources[0x3a]	9641	1			T61	2		T62	2		T67	2
valid_sources[0x3b]	10024	1			T30	2		T62	1		T79	1
valid_sources[0x3c]	9139	1			T26	1		T30	1		T61	2
valid_sources[0x3d]	10040	1			T31	2		T62	2		T67	2
valid_sources[0x3e]	9427	1			T62	1		T63	1		T108	1
valid_sources[0x3f]	11127	1			T30	2		T58	2		T62	3
valid_sources[0x40]	8575	1			T30	1		T72	1		T67	1
valid_sources[0x41]	9368	1			T30	2		T62	2		T123	2
valid_sources[0x42]	10659	1			T30	2		T62	2		T63	1
valid_sources[0x43]	9301	1			T30	1		T62	1		T67	1
valid_sources[0x44]	10341	1			T30	2		T62	1		T67	1
valid_sources[0x45]	10195	1			T26	3		T30	3		T62	1
valid_sources[0x46]	10474	1			T30	2		T61	1		T64	1
valid_sources[0x47]	9820	1			T30	1		T64	1		T62	1
valid_sources[0x48]	9809	1			T30	1		T62	1		T63	1
valid_sources[0x49]	10359	1			T30	1		T34	20		T62	1
valid_sources[0x4a]	9824	1			T58	1		T63	2		T72	1
valid_sources[0x4b]	9860	1			T30	1		T62	3		T66	1
valid_sources[0x4c]	9093	1			T30	1		T62	2		T125	3
valid_sources[0x4d]	9832	1			T30	1		T62	3		T113	1
valid_sources[0x4e]	9739	1			T30	2		T62	1		T127	1
valid_sources[0x4f]	10179	1			T64	1		T63	1		T108	3
valid_sources[0x50]	10021	1			T30	2		T31	1		T61	2
valid_sources[0x51]	10154	1			T30	1		T62	1		T123	1
valid_sources[0x52]	9313	1			T30	3		T62	2		T63	1
valid_sources[0x53]	9663	1			T30	3		T62	1		T66	2
valid_sources[0x54]	9844	1			T30	1		T67	3		T125	2
valid_sources[0x55]	9279	1			T30	2		T62	5		T67	4
valid_sources[0x56]	10333	1			T30	1		T125	5		T126	2
valid_sources[0x57]	10230	1			T32	4		T64	1		T62	1
valid_sources[0x58]	9725	1			T30	1		T31	1		T62	1
valid_sources[0x59]	9617	1			T30	3		T64	1		T67	1
valid_sources[0x5a]	9731	1			T30	1		T62	1		T63	1
valid_sources[0x5b]	9449	1			T62	4		T63	1		T79	1
valid_sources[0x5c]	9551	1			T61	1		T67	1		T108	4
valid_sources[0x5d]	9237	1			T30	2		T61	1		T62	1
valid_sources[0x5e]	11392	1			T66	5		T123	1		T108	2
valid_sources[0x5f]	9403	1			T30	1		T62	2		T72	1
valid_sources[0x60]	9302	1			T30	1		T62	6		T67	1
valid_sources[0x61]	8646	1			T63	2		T67	1		T113	1
valid_sources[0x62]	11024	1			T30	2		T58	1		T62	2
valid_sources[0x63]	10480	1			T26	1		T30	2		T61	1
valid_sources[0x64]	9167	1			T63	1		T67	1		T126	2
valid_sources[0x65]	9852	1			T30	1		T61	1		T63	1
valid_sources[0x66]	9552	1			T30	2		T62	2		T125	1
valid_sources[0x67]	10222	1			T62	1		T63	1		T125	2
valid_sources[0x68]	9874	1			T29	23		T67	1		T123	3
valid_sources[0x69]	9155	1			T28	6		T58	3		T63	2
valid_sources[0x6a]	10202	1			T30	2		T63	4		T66	7
valid_sources[0x6b]	8907	1			T28	1		T30	2		T57	6
valid_sources[0x6c]	9004	1			T30	2		T62	1		T67	1
valid_sources[0x6d]	11148	1			T62	2		T63	2		T108	3
valid_sources[0x6e]	11708	1			T30	1		T63	2		T108	3
valid_sources[0x6f]	11266	1			T30	1		T62	1		T63	2
valid_sources[0x70]	9855	1			T30	1		T62	2		T63	2
valid_sources[0x71]	8927	1			T30	2		T63	1		T108	3
valid_sources[0x72]	9764	1			T30	2		T62	3		T108	2
valid_sources[0x73]	9717	1			T30	3		T31	4		T62	2
valid_sources[0x74]	9446	1			T30	1		T61	1		T67	4
valid_sources[0x75]	9384	1			T30	3		T32	2		T62	2
valid_sources[0x76]	9680	1			T30	2		T62	2		T113	1
valid_sources[0x77]	9579	1			T30	2		T61	1		T66	7
valid_sources[0x78]	8894	1			T30	1		T32	12		T56	75
valid_sources[0x79]	10222	1			T26	3		T30	1		T62	1
valid_sources[0x7a]	10237	1			T30	1		T62	1		T67	1
valid_sources[0x7b]	9824	1			T30	1		T67	1		T108	3
valid_sources[0x7c]	9990	1			T30	2		T62	1		T67	2
valid_sources[0x7d]	9668	1			T62	2		T123	1		T108	1
valid_sources[0x7e]	11479	1			T30	1		T108	2		T125	1
valid_sources[0x7f]	10079	1			T62	1		T108	5		T125	5
valid_sources[0x80]	9509	1			T30	1		T62	3		T63	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

520635

1

T26

10

T28

3

T29

13

values[0x0]

all_enables

biggest_size

773350

1

T26

16

T28

6

T29

16

values[0x1]

all_enables

biggest_size

771792

1

T26

12

T28

7

T29

19