Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5646497

1

T26

28

T28

41

T29

80

full_word

2470633

1

T26

42

T28

17

T29

51

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8116850	1			T26	70		T28	58		T29	131
auto[TlIntgErrCmd]	95	1			T57	5		T58	8		T60	2
auto[TlIntgErrData]	105	1			T57	3		T58	9		T60	3
auto[TlIntgErrBoth]	80	1			T57	2		T58	3		T60	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

980645

1

T26

12

T28

8

T29

19

auto[1]

7136485

1

T26

58

T28

50

T29

112

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	410164	1			T26	2		T28	4		T29	6
auto[TlIntgErrNone]	partial	auto[1]	5236086	1			T26	26		T28	37		T29	74
auto[TlIntgErrNone]	full_word	auto[0]	570354	1			T26	10		T28	4		T29	13
auto[TlIntgErrNone]	full_word	auto[1]	1900246	1			T26	32		T28	13		T29	38
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T57	2		T58	3		T60	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T57	2		T58	4		T60	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T57	1		T118	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T58	1		T116	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T57	1		T58	1		T77	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T57	1		T58	5		T77	3
auto[TlIntgErrData]	full_word	auto[0]	9	1			T57	1		T58	2		T60	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T58	1		T60	2		T78	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T58	2		T60	2		T77	2
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T57	2		T58	1		T60	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T114	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T120	1		T111	1		T121	1