Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2037257

1

T32

544

T33

104

T34

175

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	556116	1			T32	132		T33	22		T34	68
values[0x0]	776340	1			T32	214		T33	49		T34	93
values[0x1]	901693	1			T32	217		T33	39		T34	92

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	86949	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2147200

1

T32

558

T33

107

T34

208

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8582	1			T32	6		T34	1		T36	1
valid_sources[0x01]	8939	1			T32	2		T33	1		T36	6
valid_sources[0x02]	9225	1			T32	9		T36	1		T38	1
valid_sources[0x03]	7935	1			T32	2		T36	2		T38	3
valid_sources[0x04]	8874	1			T36	1		T38	1		T61	3
valid_sources[0x05]	8706	1			T32	2		T34	4		T35	1
valid_sources[0x06]	9140	1			T32	8		T34	3		T36	2
valid_sources[0x07]	9440	1			T32	2		T36	1		T38	1
valid_sources[0x08]	8758	1			T32	4		T39	1		T61	1
valid_sources[0x09]	8311	1			T34	1		T36	7		T38	2
valid_sources[0x0a]	8999	1			T32	2		T33	1		T36	3
valid_sources[0x0b]	8956	1			T32	1		T34	2		T39	3
valid_sources[0x0c]	8661	1			T32	1		T33	2		T36	1
valid_sources[0x0d]	8110	1			T32	3		T34	2		T36	5
valid_sources[0x0e]	8528	1			T32	4		T38	1		T39	2
valid_sources[0x0f]	8142	1			T33	1		T34	1		T36	1
valid_sources[0x10]	8913	1			T33	1		T34	1		T36	4
valid_sources[0x11]	8533	1			T36	6		T38	1		T63	1
valid_sources[0x12]	8680	1			T32	1		T36	2		T38	2
valid_sources[0x13]	8252	1			T32	1		T34	2		T36	5
valid_sources[0x14]	8299	1			T36	1		T38	1		T69	1
valid_sources[0x15]	8168	1			T32	1		T34	1		T36	3
valid_sources[0x16]	8829	1			T34	2		T61	2		T60	4
valid_sources[0x17]	8215	1			T32	7		T34	1		T36	3
valid_sources[0x18]	8500	1			T32	1		T33	2		T34	1
valid_sources[0x19]	9380	1			T32	1		T34	1		T36	1
valid_sources[0x1a]	9060	1			T32	7		T36	3		T61	9
valid_sources[0x1b]	8734	1			T32	1		T34	2		T36	1
valid_sources[0x1c]	9502	1			T34	1		T36	2		T38	2
valid_sources[0x1d]	9166	1			T33	1		T34	2		T36	2
valid_sources[0x1e]	8491	1			T33	1		T34	5		T36	3
valid_sources[0x1f]	7680	1			T32	1		T33	2		T39	3
valid_sources[0x20]	9473	1			T34	2		T36	1		T38	1
valid_sources[0x21]	9083	1			T34	1		T39	1		T61	1
valid_sources[0x22]	9004	1			T32	3		T34	2		T36	2
valid_sources[0x23]	8977	1			T36	1		T60	2		T73	7
valid_sources[0x24]	8826	1			T61	2		T63	1		T64	1
valid_sources[0x25]	9880	1			T34	1		T36	4		T38	2
valid_sources[0x26]	8391	1			T33	1		T35	3		T36	2
valid_sources[0x27]	8681	1			T32	1		T34	1		T39	4
valid_sources[0x28]	8262	1			T34	1		T36	1		T38	1
valid_sources[0x29]	8288	1			T32	3		T34	3		T36	4
valid_sources[0x2a]	8398	1			T32	6		T33	1		T34	1
valid_sources[0x2b]	7867	1			T32	2		T33	1		T36	1
valid_sources[0x2c]	8282	1			T32	5		T34	1		T36	2
valid_sources[0x2d]	9086	1			T34	1		T36	2		T40	2
valid_sources[0x2e]	8823	1			T32	1		T34	1		T36	2
valid_sources[0x2f]	8672	1			T34	1		T38	3		T39	1
valid_sources[0x30]	8890	1			T32	4		T33	1		T36	1
valid_sources[0x31]	8703	1			T36	3		T37	31		T39	3
valid_sources[0x32]	7402	1			T32	2		T34	3		T36	2
valid_sources[0x33]	8754	1			T34	2		T36	3		T61	3
valid_sources[0x34]	8924	1			T32	3		T35	2		T60	3
valid_sources[0x35]	9291	1			T32	13		T36	2		T38	1
valid_sources[0x36]	7955	1			T32	2		T34	1		T36	3
valid_sources[0x37]	8991	1			T32	3		T34	1		T36	2
valid_sources[0x38]	9478	1			T32	1		T33	3		T34	3
valid_sources[0x39]	8956	1			T32	1		T33	1		T34	1
valid_sources[0x3a]	8280	1			T33	1		T34	1		T36	1
valid_sources[0x3b]	8120	1			T32	1		T33	1		T36	3
valid_sources[0x3c]	8567	1			T32	3		T38	1		T39	1
valid_sources[0x3d]	7951	1			T32	5		T36	2		T39	1
valid_sources[0x3e]	8991	1			T32	6		T33	1		T36	2
valid_sources[0x3f]	8985	1			T32	1		T33	1		T36	1
valid_sources[0x40]	8110	1			T32	9		T33	1		T39	1
valid_sources[0x41]	8869	1			T32	9		T33	1		T35	2
valid_sources[0x42]	8293	1			T32	1		T34	2		T35	10
valid_sources[0x43]	9300	1			T33	2		T36	1		T64	3
valid_sources[0x44]	8795	1			T32	4		T34	2		T37	10
valid_sources[0x45]	8365	1			T32	10		T33	1		T36	2
valid_sources[0x46]	9401	1			T32	2		T34	1		T36	1
valid_sources[0x47]	9215	1			T32	4		T34	5		T39	2
valid_sources[0x48]	9512	1			T32	7		T34	1		T35	4
valid_sources[0x49]	8774	1			T32	2		T34	1		T35	12
valid_sources[0x4a]	9031	1			T32	1		T36	3		T38	1
valid_sources[0x4b]	9547	1			T32	3		T33	1		T34	1
valid_sources[0x4c]	8014	1			T36	1		T61	2		T63	1
valid_sources[0x4d]	8096	1			T32	1		T33	1		T36	2
valid_sources[0x4e]	8513	1			T32	5		T34	2		T36	2
valid_sources[0x4f]	9799	1			T32	4		T34	1		T38	1
valid_sources[0x50]	9770	1			T32	2		T35	10		T36	5
valid_sources[0x51]	9003	1			T33	1		T34	1		T36	6
valid_sources[0x52]	8814	1			T32	1		T36	2		T60	3
valid_sources[0x53]	8934	1			T32	4		T34	4		T36	3
valid_sources[0x54]	7926	1			T34	2		T35	9		T36	1
valid_sources[0x55]	8979	1			T32	1		T33	2		T39	1
valid_sources[0x56]	7965	1			T32	2		T34	4		T35	4
valid_sources[0x57]	10030	1			T32	2		T33	2		T34	1
valid_sources[0x58]	9036	1			T32	4		T36	2		T38	1
valid_sources[0x59]	8221	1			T34	1		T39	1		T60	3
valid_sources[0x5a]	7942	1			T32	1		T34	3		T36	3
valid_sources[0x5b]	8283	1			T32	2		T36	1		T38	2
valid_sources[0x5c]	8631	1			T32	3		T34	1		T36	2
valid_sources[0x5d]	7342	1			T32	2		T34	4		T61	3
valid_sources[0x5e]	8805	1			T32	4		T61	1		T60	8
valid_sources[0x5f]	7938	1			T32	2		T36	1		T38	1
valid_sources[0x60]	8657	1			T32	4		T34	2		T35	1
valid_sources[0x61]	8911	1			T34	1		T38	2		T63	1
valid_sources[0x62]	8527	1			T32	2		T33	1		T61	1
valid_sources[0x63]	8699	1			T34	1		T38	2		T61	2
valid_sources[0x64]	9375	1			T32	3		T38	2		T39	1
valid_sources[0x65]	8815	1			T34	1		T37	31		T39	5
valid_sources[0x66]	7952	1			T32	4		T36	1		T38	2
valid_sources[0x67]	8079	1			T32	4		T33	1		T34	1
valid_sources[0x68]	7692	1			T36	1		T61	1		T60	1
valid_sources[0x69]	8099	1			T33	1		T34	2		T38	2
valid_sources[0x6a]	7849	1			T33	1		T34	1		T39	1
valid_sources[0x6b]	9815	1			T32	1		T34	3		T36	1
valid_sources[0x6c]	7998	1			T34	1		T61	4		T69	1
valid_sources[0x6d]	7818	1			T32	4		T34	1		T36	1
valid_sources[0x6e]	8249	1			T32	2		T33	1		T34	1
valid_sources[0x6f]	9348	1			T32	1		T34	2		T38	1
valid_sources[0x70]	9345	1			T32	1		T33	2		T34	1
valid_sources[0x71]	8703	1			T32	1		T33	2		T36	3
valid_sources[0x72]	9054	1			T36	2		T61	3		T60	2
valid_sources[0x73]	9309	1			T33	1		T34	2		T36	1
valid_sources[0x74]	9087	1			T32	3		T34	1		T38	2
valid_sources[0x75]	8564	1			T36	1		T61	1		T60	3
valid_sources[0x76]	8482	1			T32	8		T35	23		T36	6
valid_sources[0x77]	8073	1			T32	3		T33	1		T34	1
valid_sources[0x78]	7628	1			T32	3		T33	1		T37	10
valid_sources[0x79]	8799	1			T32	1		T38	1		T39	1
valid_sources[0x7a]	8273	1			T32	7		T34	1		T36	1
valid_sources[0x7b]	8629	1			T32	4		T34	2		T36	2
valid_sources[0x7c]	9528	1			T33	1		T35	2		T36	1
valid_sources[0x7d]	8557	1			T32	3		T34	1		T38	1
valid_sources[0x7e]	9002	1			T34	1		T38	1		T40	1
valid_sources[0x7f]	8537	1			T32	3		T36	2		T39	1
valid_sources[0x80]	8803	1			T32	2		T34	1		T36	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

514179

1

T32

129

T33

17

T34

4

values[0x0]

all_enables

biggest_size

760998

1

T32

212

T33

49

T34

88

values[0x1]

all_enables

biggest_size

762080

1

T32

203

T33

38

T34

83

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	449690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2020884

1

T32

386

T33

19

T35

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	555550	1			T32	102		T33	6		T34	4
values[0x0]	794067	1			T32	145		T33	7		T34	1
values[0x1]	1120957	1			T32	179		T33	11		T34	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	170863	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2299711

1

T32

414

T33

22

T34

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8776	1			T32	5		T63	1		T67	1
valid_sources[0x01]	9190	1			T33	1		T67	1		T66	1
valid_sources[0x02]	8952	1			T32	1		T63	1		T67	1
valid_sources[0x03]	11210	1			T32	4		T67	1		T66	2
valid_sources[0x04]	11566	1			T32	5		T67	1		T66	3
valid_sources[0x05]	9273	1			T67	2		T68	1		T85	10
valid_sources[0x06]	8524	1			T32	2		T38	9		T64	1
valid_sources[0x07]	9228	1			T32	5		T35	1		T38	1
valid_sources[0x08]	9260	1			T32	2		T38	8		T63	1
valid_sources[0x09]	9080	1			T33	1		T38	15		T67	1
valid_sources[0x0a]	10384	1			T65	1		T67	2		T66	2
valid_sources[0x0b]	9360	1			T38	6		T63	1		T68	3
valid_sources[0x0c]	9255	1			T32	2		T33	2		T65	1
valid_sources[0x0d]	8749	1			T32	2		T63	1		T85	4
valid_sources[0x0e]	11601	1			T38	1		T63	1		T66	2
valid_sources[0x0f]	10103	1			T32	7		T63	1		T64	1
valid_sources[0x10]	11036	1			T63	1		T65	1		T67	1
valid_sources[0x11]	9755	1			T32	1		T33	1		T35	2
valid_sources[0x12]	8363	1			T32	1		T38	3		T63	1
valid_sources[0x13]	9523	1			T32	1		T66	2		T96	1
valid_sources[0x14]	9464	1			T32	5		T38	1		T63	1
valid_sources[0x15]	11317	1			T32	1		T38	9		T63	1
valid_sources[0x16]	8984	1			T33	1		T65	1		T67	1
valid_sources[0x17]	9814	1			T32	5		T65	1		T66	1
valid_sources[0x18]	8613	1			T66	1		T110	2		T121	2
valid_sources[0x19]	9900	1			T33	1		T38	2		T65	2
valid_sources[0x1a]	8360	1			T63	1		T65	1		T67	1
valid_sources[0x1b]	9731	1			T32	4		T63	1		T65	1
valid_sources[0x1c]	9102	1			T32	4		T34	7		T67	1
valid_sources[0x1d]	9561	1			T32	5		T65	1		T67	2
valid_sources[0x1e]	9028	1			T38	6		T63	1		T67	3
valid_sources[0x1f]	9006	1			T32	1		T65	1		T67	5
valid_sources[0x20]	9761	1			T32	8		T35	1		T38	1
valid_sources[0x21]	9421	1			T65	1		T67	1		T96	1
valid_sources[0x22]	9550	1			T32	4		T38	1		T63	1
valid_sources[0x23]	11183	1			T32	3		T65	3		T67	3
valid_sources[0x24]	9095	1			T32	4		T35	5		T63	2
valid_sources[0x25]	11091	1			T32	3		T36	40		T44	1
valid_sources[0x26]	10138	1			T32	4		T38	1		T63	1
valid_sources[0x27]	9479	1			T67	2		T66	1		T76	1
valid_sources[0x28]	9488	1			T32	1		T35	5		T66	1
valid_sources[0x29]	9008	1			T67	1		T76	1		T110	3
valid_sources[0x2a]	11287	1			T65	2		T67	2		T76	1
valid_sources[0x2b]	11022	1			T63	1		T68	1		T66	1
valid_sources[0x2c]	9765	1			T67	3		T68	1		T66	1
valid_sources[0x2d]	9186	1			T66	2		T85	6		T110	9
valid_sources[0x2e]	8648	1			T38	1		T67	1		T66	1
valid_sources[0x2f]	9988	1			T32	4		T67	1		T77	20
valid_sources[0x30]	9957	1			T38	13		T63	2		T67	1
valid_sources[0x31]	10019	1			T38	1		T63	1		T67	1
valid_sources[0x32]	8914	1			T32	1		T79	4		T110	2
valid_sources[0x33]	8747	1			T32	5		T63	1		T65	2
valid_sources[0x34]	11585	1			T38	10		T67	1		T74	1
valid_sources[0x35]	8845	1			T38	4		T65	1		T67	1
valid_sources[0x36]	8790	1			T67	2		T110	1		T121	1
valid_sources[0x37]	9530	1			T32	5		T65	2		T67	1
valid_sources[0x38]	9279	1			T32	1		T33	1		T63	1
valid_sources[0x39]	9127	1			T32	5		T38	4		T65	1
valid_sources[0x3a]	9609	1			T38	2		T63	2		T67	1
valid_sources[0x3b]	9901	1			T38	2		T67	1		T68	1
valid_sources[0x3c]	9880	1			T32	6		T35	1		T38	3
valid_sources[0x3d]	9083	1			T38	1		T65	1		T67	2
valid_sources[0x3e]	10623	1			T67	1		T68	2		T66	1
valid_sources[0x3f]	9559	1			T38	2		T62	3		T63	1
valid_sources[0x40]	9405	1			T32	3		T38	2		T63	2
valid_sources[0x41]	10189	1			T32	5		T38	1		T63	1
valid_sources[0x42]	9158	1			T32	4		T67	1		T82	2
valid_sources[0x43]	9625	1			T63	2		T65	1		T66	1
valid_sources[0x44]	10674	1			T32	1		T38	2		T63	1
valid_sources[0x45]	9651	1			T32	1		T33	2		T38	2
valid_sources[0x46]	10203	1			T32	3		T38	1		T64	1
valid_sources[0x47]	9709	1			T63	1		T67	2		T110	1
valid_sources[0x48]	9730	1			T38	1		T63	1		T67	1
valid_sources[0x49]	10387	1			T38	4		T63	1		T64	1
valid_sources[0x4a]	9181	1			T67	1		T84	156		T85	4
valid_sources[0x4b]	9394	1			T32	1		T38	4		T65	1
valid_sources[0x4c]	9287	1			T38	4		T62	1		T63	1
valid_sources[0x4d]	9303	1			T63	1		T67	2		T66	1
valid_sources[0x4e]	9029	1			T32	8		T63	1		T85	26
valid_sources[0x4f]	9783	1			T63	1		T64	1		T65	1
valid_sources[0x50]	8935	1			T38	9		T63	2		T67	3
valid_sources[0x51]	8630	1			T32	3		T35	4		T38	1
valid_sources[0x52]	8940	1			T32	3		T63	1		T67	1
valid_sources[0x53]	8850	1			T63	1		T67	2		T66	2
valid_sources[0x54]	9789	1			T32	1		T67	4		T117	1
valid_sources[0x55]	8581	1			T32	3		T65	1		T96	1
valid_sources[0x56]	9644	1			T32	6		T65	1		T66	1
valid_sources[0x57]	10202	1			T63	1		T65	1		T67	2
valid_sources[0x58]	9434	1			T33	1		T38	23		T64	1
valid_sources[0x59]	11362	1			T63	2		T65	1		T67	1
valid_sources[0x5a]	8808	1			T32	2		T35	2		T63	1
valid_sources[0x5b]	9199	1			T38	6		T62	1		T63	1
valid_sources[0x5c]	9365	1			T63	1		T66	1		T74	1
valid_sources[0x5d]	9110	1			T33	1		T67	1		T66	2
valid_sources[0x5e]	9478	1			T67	1		T110	1		T80	1
valid_sources[0x5f]	8899	1			T32	2		T38	3		T63	1
valid_sources[0x60]	10217	1			T32	5		T64	1		T44	18
valid_sources[0x61]	9469	1			T32	2		T67	1		T82	3
valid_sources[0x62]	9403	1			T38	1		T65	3		T67	1
valid_sources[0x63]	9973	1			T38	4		T63	2		T96	1
valid_sources[0x64]	10706	1			T63	2		T67	2		T110	4
valid_sources[0x65]	11620	1			T65	1		T68	1		T83	1
valid_sources[0x66]	9230	1			T63	1		T64	1		T67	1
valid_sources[0x67]	9185	1			T63	1		T65	1		T117	1
valid_sources[0x68]	9883	1			T32	2		T38	17		T65	1
valid_sources[0x69]	10970	1			T63	1		T66	1		T76	1
valid_sources[0x6a]	9441	1			T33	1		T63	2		T67	2
valid_sources[0x6b]	10247	1			T32	4		T65	1		T83	1
valid_sources[0x6c]	9577	1			T32	1		T33	1		T65	1
valid_sources[0x6d]	9378	1			T35	1		T65	1		T67	4
valid_sources[0x6e]	10858	1			T32	11		T38	3		T63	1
valid_sources[0x6f]	9045	1			T32	1		T38	4		T65	2
valid_sources[0x70]	8866	1			T32	3		T35	1		T85	13
valid_sources[0x71]	9460	1			T67	2		T96	1		T110	2
valid_sources[0x72]	12153	1			T32	3		T35	7		T68	3
valid_sources[0x73]	9964	1			T66	1		T83	1		T85	2
valid_sources[0x74]	9974	1			T64	1		T65	2		T66	2
valid_sources[0x75]	10178	1			T32	7		T38	5		T63	1
valid_sources[0x76]	8693	1			T38	2		T67	1		T68	3
valid_sources[0x77]	10150	1			T32	12		T63	1		T67	3
valid_sources[0x78]	10159	1			T38	3		T65	1		T66	2
valid_sources[0x79]	9228	1			T32	1		T38	4		T110	4
valid_sources[0x7a]	9833	1			T32	1		T63	1		T66	2
valid_sources[0x7b]	9430	1			T38	8		T63	1		T65	1
valid_sources[0x7c]	10108	1			T67	2		T110	2		T121	1
valid_sources[0x7d]	9402	1			T38	4		T65	1		T67	2
valid_sources[0x7e]	8667	1			T67	1		T76	1		T110	1
valid_sources[0x7f]	9686	1			T32	3		T65	1		T67	5
valid_sources[0x80]	10751	1			T38	4		T63	1		T65	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

510270

1

T32

102

T33

6

T35

12

values[0x0]

all_enables

biggest_size

755587

1

T32

141

T33

7

T35

16

values[0x1]

all_enables

biggest_size

755027

1

T32

143

T33

6

T35

21