Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5547587

1

T32

459

T33

104

T34

10

full_word

2417486

1

T32

415

T33

27

T35

56

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7964743	1			T32	874		T33	131		T35	198
auto[TlIntgErrCmd]	100	1			T34	1		T61	5		T60	6
auto[TlIntgErrData]	115	1			T34	4		T61	9		T60	8
auto[TlIntgErrBoth]	115	1			T34	5		T61	6		T60	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961898

1

T32

118

T33

15

T34

5

auto[1]

7003175

1

T32

756

T33

116

T34

5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	403097	1			T32	14		T33	7		T35	16
auto[TlIntgErrNone]	partial	auto[1]	5144181	1			T32	445		T33	97		T35	126
auto[TlIntgErrNone]	full_word	auto[0]	558655	1			T32	104		T33	8		T35	12
auto[TlIntgErrNone]	full_word	auto[1]	1858810	1			T32	311		T33	19		T35	44
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T61	2		T60	2		T82	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T34	1		T61	1		T60	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T61	1		T82	1		T118	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T61	1		T60	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T34	2		T61	5		T60	4
auto[TlIntgErrData]	partial	auto[1]	50	1			T34	2		T61	4		T60	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T60	1		T115	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T118	1		T119	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T34	3		T61	1		T82	2
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T34	2		T61	4		T60	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T82	1		T116	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T61	1		T96	1		T117	1