Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.32	97.11	92.68	97.88	100.00	98.37	97.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	98.21	92.86		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.18	100.00				100.00	97.55
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_rom_top	100.00	100.00				100.00	100.00
u_tl_adapter_rom	93.77	91.56	83.06	99.07		95.18	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	453	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
117	1	1
122	1	1
123	1	1
124	1	1
125	1	1
128	1	1
222	1	1
268	1	1
323	1	1
425	8	8
426	8	8
428	8	8
429	8	8
431	8	8
432	8	8
436	1	1
438	1	1
441	1	1
442	1	1
443	1	1
444	1	1
449	1	1
453	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       222
 EXPRESSION (tl_rom_h2d_upstream.a_valid ? tl_rom_h2d_upstream.a_address[2+:RomIndexWidth] : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       268
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T11
1	1	Covered	T2,T3,T4

 LINE       429
 EXPRESSION (exp_digest_de && (0[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (0[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (1[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (1[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (2[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (2[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (3[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (3[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (4[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (4[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (5[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (5[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (6[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (6[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (exp_digest_de && (7[2:0] == exp_digest_idx))
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (7[2:0] == exp_digest_idx)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       436
 EXPRESSION (rom_reg_integrity_error | rom_integrity_error | reg_integrity_error)
             -----------1-----------   ---------2---------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T31,T42,T43
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       438
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T3,T6,T31

 LINE       449
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T21

 LINE       453
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T6,T11
0	1	0	Covered	T3,T6,T31
1	0	0	Covered	T31,T42,T43

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rst_ni	Yes	Yes	T33,T34,T35	Yes	T32,T33,T34	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_i.a_valid	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
rom_tl_o.a_ready	Yes	Yes	T33,T34,T35	Yes	T32,T33,T34	OUTPUT
rom_tl_o.d_error	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T36,T37,T44	Yes	T36,T37,T44	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T32,T33,T35	Yes	T32,T33,T35	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T32,T33,T35	Yes	T32,T33,T35	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T32,*T33,*T34	Yes	T32,T33,T34	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_i.a_valid	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
regs_tl_o.a_ready	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
regs_tl_o.d_error	Yes	Yes	T33,T34,T35	Yes	T32,T33,T34	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T32,T33,T34	Yes	T32,T33,T34	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T33,T34,T35	Yes	T32,T33,T34	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T32,*T33,*T34	Yes	T32,T33,T34	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T32,T33,T34	Yes	T36,T37,T44	OUTPUT
keymgr_data_o.valid	Yes	Yes	T36,T37,T44	Yes	T32,T33,T34	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T36,T37,T44	Yes	T32,T33,T34	OUTPUT
kmac_data_i.error	No	Yes	T22,T23,T27	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T36,T37,T44	Yes	T36,T37,T44	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T36,T37,T44	Yes	T36,T37,T44	INPUT
kmac_data_i.done	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
kmac_data_i.ready	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
kmac_data_o.last	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	222	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	222	(tl_rom_h2d_upstream.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	289680523	289497280	0	0
BusRomIndicesMatch_A	289661789	289486752	0	0
FpvSecCmFifoRptrCheck_A	289680523	0	0	0
FpvSecCmFifoWptrCheck_A	289680523	0	0	0
FpvSecCmRegWeOnehotCheck_A	289680523	70	0	0
KeymgrDataODataKnown_A	289680523	106198691	0	0
KeymgrDataODataKnown_AKnownEnable	289680523	289497280	0	0
KeymgrDataOValidKnown_A	289680523	289497280	0	0
KeymgrValidChk_A	289680523	0	0	338
KmacDataODataKnown_A	289680523	183145246	0	0
KmacDataODataKnown_AKnownEnable	289680523	289497280	0	0
KmacDataOValidKnown_A	289680523	289497280	0	0
PwrmgrDataChk_A	289680523	0	0	338
PwrmgrDataOKnown_A	289680523	289497280	0	0
RegsTlOAReadyKnown_A	289680523	289497280	0	0
RegsTlODDataKnown_A	289680523	16942174	0	0
RegsTlODDataKnown_AKnownEnable	289680523	289497280	0	0
RegsTlODValidKnown_A	289680523	289497280	0	0
RomTlOAReadyKnown_A	289680523	289497280	0	0
RomTlODDataKnown_A	289680523	19450029	0	0
RomTlODDataKnown_AKnownEnable	289680523	289497280	0	0
RomTlODValidKnown_A	289680523	289497280	0	0
StabilityChkKmac_A	289680523	183142607	0	0
StabilityChkkeymgr_A	289680523	106197348	0	0
TlAccessChk_A	289680523	183298589	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	289680523	70	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	289680523	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	289680523	595	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	289680523	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289661789	289486752	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171505	169267	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637832	635657	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	70	0	0
T11	137842	0	0	0
T31	238682	20	0	0
T42	207290	10	0	0
T43	0	20	0	0
T45	0	10	0	0
T46	0	10	0	0
T47	62036	0	0	0
T48	8581	0	0	0
T49	28492	0	0	0
T50	376539	0	0	0
T51	421219	0	0	0
T52	126403	0	0	0
T53	123524	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	106198691	0	0
T1	180001	64	0	0
T2	132576	129140	0	0
T3	171708	9553	0	0
T4	237444	3827	0	0
T5	100327	1344	0	0
T6	637915	9464	0	0
T7	195517	277	0	0
T8	207654	1154	0	0
T9	34685	1711	0	0
T10	163474	1090	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	0	0	338

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	183145246	0	0
T1	180001	179758	0	0
T2	132576	34173	0	0
T3	171708	158636	0	0
T4	237444	233164	0	0
T5	100327	98811	0	0
T6	637915	624666	0	0
T7	195517	195069	0	0
T8	207654	206426	0	0
T9	34685	32730	0	0
T10	163474	162273	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	0	0	338

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	16942174	0	0
T1	180001	64	0	0
T2	132576	77140	0	0
T3	171708	115	0	0
T4	237444	96	0	0
T5	100327	32	0	0
T6	637915	108	0	0
T7	195517	21	0	0
T8	207654	0	0	0
T9	34685	32	0	0
T10	163474	0	0	0
T19	0	128	0	0
T21	0	10	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	19450029	0	0
T2	132576	90865	0	0
T3	171708	26	0	0
T4	237444	226	0	0
T5	100327	306	0	0
T6	637915	3	0	0
T7	195517	0	0	0
T8	207654	285	0	0
T9	34685	90	0	0
T10	163474	378	0	0
T19	0	72	0	0
T20	0	74	0	0
T21	41352	0	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	289497280	0	0
T1	180001	179918	0	0
T2	132576	132566	0	0
T3	171708	169305	0	0
T4	237444	237148	0	0
T5	100327	100197	0	0
T6	637915	635675	0	0
T7	195517	195445	0	0
T8	207654	207601	0	0
T9	34685	34524	0	0
T10	163474	163409	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	183142607	0	0
T1	180001	179757	0	0
T2	132576	34167	0	0
T3	171708	158603	0	0
T4	237444	233160	0	0
T5	100327	98809	0	0
T6	637915	624637	0	0
T7	195517	195068	0	0
T8	207654	206425	0	0
T9	34685	32728	0	0
T10	163474	162272	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	106197348	0	0
T1	180001	63	0	0
T2	132576	129140	0	0
T3	171708	9540	0	0
T4	237444	3824	0	0
T5	100327	1342	0	0
T6	637915	9451	0	0
T7	195517	276	0	0
T8	207654	1153	0	0
T9	34685	1709	0	0
T10	163474	1089	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	183298589	0	0
T1	180001	179854	0	0
T2	132576	34261	0	0
T3	171708	159752	0	0
T4	237444	233321	0	0
T5	100327	98853	0	0
T6	637915	626211	0	0
T7	195517	195168	0	0
T8	207654	206447	0	0
T9	34685	32813	0	0
T10	163474	162319	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	70	0	0
T11	137842	0	0	0
T31	238682	20	0	0
T42	207290	10	0	0
T43	0	20	0	0
T45	0	10	0	0
T46	0	10	0	0
T47	62036	0	0	0
T48	8581	0	0	0
T49	28492	0	0	0
T50	376539	0	0	0
T51	421219	0	0	0
T52	126403	0	0	0
T53	123524	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	595	0	0
T3	171708	10	0	0
T4	237444	0	0	0
T5	100327	0	0	0
T6	637915	10	0	0
T7	195517	0	0	0
T8	207654	0	0	0
T9	34685	0	0	0
T10	163474	0	0	0
T21	41352	0	0	0
T25	0	11	0	0
T30	0	15	0	0
T31	0	20	0	0
T54	0	11	0	0
T55	0	10	0	0
T56	0	20	0	0
T57	0	5	0	0
T58	0	5	0	0
T59	51649	0	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289680523	0	0	0