Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	205005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2103397

1

T21

33

T22

336

T23

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	576191	1			T21	6		T22	48		T23	8
values[0x0]	802747	1			T21	14		T22	169		T23	20
values[0x1]	929464	1			T21	22		T22	178		T23	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90830	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2217572

1

T21

37

T22

354

T23

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9088	1			T27	1		T55	1		T64	2
valid_sources[0x01]	8509	1			T23	1		T27	3		T28	1
valid_sources[0x02]	8826	1			T24	1		T27	2		T51	1
valid_sources[0x03]	9436	1			T27	1		T28	1		T54	1
valid_sources[0x04]	9650	1			T24	1		T27	1		T28	1
valid_sources[0x05]	8794	1			T24	3		T27	1		T42	10
valid_sources[0x06]	9293	1			T23	2		T24	9		T27	2
valid_sources[0x07]	9135	1			T21	1		T27	3		T29	1
valid_sources[0x08]	8733	1			T55	1		T64	1		T65	1
valid_sources[0x09]	8583	1			T28	1		T64	1		T57	1
valid_sources[0x0a]	8831	1			T24	10		T25	11		T27	1
valid_sources[0x0b]	8087	1			T27	2		T28	1		T54	1
valid_sources[0x0c]	8925	1			T24	7		T54	1		T79	2
valid_sources[0x0d]	8329	1			T24	6		T28	2		T29	2
valid_sources[0x0e]	8272	1			T27	3		T28	1		T64	1
valid_sources[0x0f]	10278	1			T23	1		T24	2		T26	1
valid_sources[0x10]	8877	1			T23	2		T28	1		T80	1
valid_sources[0x11]	9496	1			T22	4		T51	1		T62	2
valid_sources[0x12]	9171	1			T27	2		T28	1		T51	1
valid_sources[0x13]	8836	1			T23	1		T24	5		T27	2
valid_sources[0x14]	8484	1			T28	3		T54	1		T55	1
valid_sources[0x15]	9265	1			T28	1		T55	1		T57	2
valid_sources[0x16]	8547	1			T22	17		T28	1		T55	1
valid_sources[0x17]	8369	1			T24	1		T27	1		T51	1
valid_sources[0x18]	8673	1			T51	1		T55	1		T79	1
valid_sources[0x19]	7013	1			T22	27		T28	2		T103	2
valid_sources[0x1a]	9640	1			T79	1		T103	1		T93	1
valid_sources[0x1b]	9599	1			T24	6		T27	3		T52	23
valid_sources[0x1c]	8418	1			T24	3		T27	5		T64	2
valid_sources[0x1d]	9282	1			T24	2		T27	1		T28	2
valid_sources[0x1e]	8447	1			T21	4		T23	1		T25	11
valid_sources[0x1f]	9009	1			T22	15		T51	1		T58	2
valid_sources[0x20]	9094	1			T24	5		T28	1		T54	1
valid_sources[0x21]	9517	1			T24	3		T28	1		T55	1
valid_sources[0x22]	8475	1			T22	11		T28	2		T103	1
valid_sources[0x23]	7957	1			T22	19		T25	14		T27	1
valid_sources[0x24]	9353	1			T27	2		T103	3		T66	2
valid_sources[0x25]	8855	1			T24	5		T27	3		T42	31
valid_sources[0x26]	8925	1			T24	5		T27	2		T30	1
valid_sources[0x27]	8432	1			T24	2		T28	1		T57	4
valid_sources[0x28]	10439	1			T23	3		T27	1		T28	4
valid_sources[0x29]	9180	1			T21	1		T27	5		T28	1
valid_sources[0x2a]	8498	1			T25	26		T27	1		T28	1
valid_sources[0x2b]	8413	1			T27	1		T28	2		T30	1
valid_sources[0x2c]	8564	1			T28	1		T51	1		T64	2
valid_sources[0x2d]	9287	1			T27	2		T30	1		T64	1
valid_sources[0x2e]	8599	1			T55	1		T79	1		T57	2
valid_sources[0x2f]	8452	1			T22	3		T24	9		T25	54
valid_sources[0x30]	9619	1			T22	23		T24	14		T28	1
valid_sources[0x31]	9358	1			T25	11		T26	47		T27	2
valid_sources[0x32]	9259	1			T27	1		T28	1		T103	3
valid_sources[0x33]	9475	1			T22	13		T23	1		T27	2
valid_sources[0x34]	9717	1			T21	1		T22	10		T24	7
valid_sources[0x35]	8845	1			T21	2		T24	6		T27	1
valid_sources[0x36]	8885	1			T27	1		T28	2		T30	2
valid_sources[0x37]	8938	1			T28	3		T79	1		T80	1
valid_sources[0x38]	9130	1			T22	5		T28	1		T55	1
valid_sources[0x39]	9356	1			T24	3		T28	3		T29	1
valid_sources[0x3a]	8758	1			T22	6		T25	11		T29	1
valid_sources[0x3b]	8934	1			T27	1		T30	1		T55	3
valid_sources[0x3c]	8883	1			T24	10		T27	2		T29	1
valid_sources[0x3d]	9030	1			T28	1		T55	2		T64	1
valid_sources[0x3e]	9169	1			T28	1		T51	1		T54	1
valid_sources[0x3f]	9010	1			T29	1		T42	10		T55	2
valid_sources[0x40]	9051	1			T24	12		T28	2		T42	62
valid_sources[0x41]	8937	1			T24	1		T27	1		T28	1
valid_sources[0x42]	8479	1			T23	1		T24	3		T55	1
valid_sources[0x43]	9779	1			T24	1		T27	3		T28	1
valid_sources[0x44]	8540	1			T30	1		T79	1		T59	1
valid_sources[0x45]	8775	1			T24	5		T28	2		T65	1
valid_sources[0x46]	9175	1			T24	3		T27	2		T51	1
valid_sources[0x47]	8826	1			T23	2		T28	1		T51	1
valid_sources[0x48]	8306	1			T24	2		T27	2		T28	1
valid_sources[0x49]	7759	1			T24	2		T27	2		T28	1
valid_sources[0x4a]	9116	1			T21	3		T27	1		T30	4
valid_sources[0x4b]	9424	1			T24	4		T27	2		T51	1
valid_sources[0x4c]	10001	1			T23	1		T27	1		T29	1
valid_sources[0x4d]	9470	1			T27	2		T29	1		T30	2
valid_sources[0x4e]	9712	1			T23	1		T27	1		T28	1
valid_sources[0x4f]	9310	1			T23	1		T63	4		T79	1
valid_sources[0x50]	10120	1			T27	3		T28	1		T79	1
valid_sources[0x51]	8648	1			T27	2		T28	4		T55	1
valid_sources[0x52]	8600	1			T27	2		T28	2		T64	1
valid_sources[0x53]	8706	1			T23	1		T25	11		T42	20
valid_sources[0x54]	8899	1			T25	11		T27	1		T28	1
valid_sources[0x55]	9947	1			T21	1		T51	1		T52	31
valid_sources[0x56]	9977	1			T79	2		T103	4		T97	5
valid_sources[0x57]	8839	1			T51	1		T60	1		T61	2
valid_sources[0x58]	9246	1			T23	1		T28	1		T54	3
valid_sources[0x59]	8781	1			T23	1		T24	1		T27	1
valid_sources[0x5a]	9040	1			T28	1		T63	2		T55	2
valid_sources[0x5b]	8665	1			T21	1		T24	7		T28	1
valid_sources[0x5c]	9461	1			T21	1		T22	31		T28	2
valid_sources[0x5d]	9045	1			T25	10		T28	1		T64	1
valid_sources[0x5e]	10605	1			T24	1		T42	10		T64	1
valid_sources[0x5f]	10901	1			T23	1		T27	3		T28	2
valid_sources[0x60]	8983	1			T27	2		T28	2		T42	20
valid_sources[0x61]	9528	1			T24	2		T27	1		T28	1
valid_sources[0x62]	8817	1			T23	1		T24	15		T27	1
valid_sources[0x63]	8387	1			T24	1		T27	1		T28	1
valid_sources[0x64]	10607	1			T25	68		T27	1		T51	1
valid_sources[0x65]	9675	1			T51	2		T55	2		T79	1
valid_sources[0x66]	8404	1			T27	1		T54	1		T57	2
valid_sources[0x67]	8886	1			T23	1		T24	12		T28	1
valid_sources[0x68]	9188	1			T27	1		T51	2		T55	2
valid_sources[0x69]	9485	1			T24	2		T28	3		T103	1
valid_sources[0x6a]	9165	1			T25	40		T27	1		T29	1
valid_sources[0x6b]	8561	1			T28	1		T51	1		T93	1
valid_sources[0x6c]	9042	1			T27	1		T55	1		T65	1
valid_sources[0x6d]	8522	1			T23	1		T24	1		T27	1
valid_sources[0x6e]	9682	1			T27	2		T28	1		T51	1
valid_sources[0x6f]	8687	1			T22	9		T28	2		T55	5
valid_sources[0x70]	9126	1			T22	33		T28	1		T103	2
valid_sources[0x71]	9143	1			T21	1		T22	6		T54	1
valid_sources[0x72]	8946	1			T22	10		T27	1		T28	2
valid_sources[0x73]	8367	1			T51	1		T52	11		T79	1
valid_sources[0x74]	9131	1			T24	4		T80	1		T103	2
valid_sources[0x75]	9263	1			T21	1		T23	1		T24	2
valid_sources[0x76]	8680	1			T21	2		T28	1		T29	1
valid_sources[0x77]	9514	1			T22	40		T28	1		T51	1
valid_sources[0x78]	8686	1			T24	2		T28	1		T79	1
valid_sources[0x79]	8963	1			T55	1		T65	2		T79	1
valid_sources[0x7a]	8864	1			T42	43		T55	2		T64	1
valid_sources[0x7b]	8323	1			T22	1		T23	2		T27	3
valid_sources[0x7c]	8217	1			T22	2		T24	7		T55	1
valid_sources[0x7d]	8824	1			T24	7		T28	3		T29	1
valid_sources[0x7e]	9132	1			T24	1		T51	1		T55	1
valid_sources[0x7f]	9183	1			T24	11		T27	2		T28	2
valid_sources[0x80]	9420	1			T27	1		T28	2		T103	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

532104

1

T21

1

T22

10

T23

6

values[0x0]

all_enables

biggest_size

786408

1

T21

12

T22

161

T23

18

values[0x1]

all_enables

biggest_size

784885

1

T21

20

T22

165

T23

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	468617	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2092281

1

T22

40

T23

17

T24

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	575197	1			T22	40		T23	3		T24	40
values[0x0]	822615	1			T23	7		T26	8		T28	50
values[0x1]	1163086	1			T23	8		T25	8		T26	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	178111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2382787

1

T22

40

T23

18

T24

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9623	1			T23	1		T28	1		T51	1
valid_sources[0x01]	10110	1			T23	2		T28	3		T55	2
valid_sources[0x02]	9950	1			T28	1		T55	2		T56	1
valid_sources[0x03]	10815	1			T28	2		T51	1		T42	1
valid_sources[0x04]	9939	1			T28	1		T56	4		T61	5
valid_sources[0x05]	10930	1			T28	1		T55	4		T60	2
valid_sources[0x06]	9526	1			T28	2		T42	1		T55	1
valid_sources[0x07]	9938	1			T24	1		T51	1		T55	1
valid_sources[0x08]	10623	1			T28	2		T55	3		T56	5
valid_sources[0x09]	9934	1			T28	2		T51	1		T55	1
valid_sources[0x0a]	10975	1			T28	2		T55	2		T59	1
valid_sources[0x0b]	9689	1			T28	1		T56	1		T60	1
valid_sources[0x0c]	10022	1			T51	1		T56	4		T59	12
valid_sources[0x0d]	10647	1			T55	2		T61	3		T73	2
valid_sources[0x0e]	10591	1			T28	2		T42	2		T54	2
valid_sources[0x0f]	10097	1			T28	2		T51	2		T55	1
valid_sources[0x10]	10038	1			T28	2		T55	2		T56	1
valid_sources[0x11]	9720	1			T55	1		T73	1		T113	1
valid_sources[0x12]	9678	1			T24	2		T28	1		T55	2
valid_sources[0x13]	10629	1			T28	2		T55	2		T56	3
valid_sources[0x14]	10157	1			T26	1		T51	1		T60	4
valid_sources[0x15]	9762	1			T51	1		T56	2		T60	2
valid_sources[0x16]	10449	1			T24	1		T28	1		T51	1
valid_sources[0x17]	9454	1			T24	1		T42	1		T55	2
valid_sources[0x18]	9877	1			T26	1		T51	1		T56	2
valid_sources[0x19]	9569	1			T28	1		T55	3		T56	1
valid_sources[0x1a]	9862	1			T26	1		T28	2		T51	2
valid_sources[0x1b]	10652	1			T51	1		T56	1		T60	2
valid_sources[0x1c]	9665	1			T28	3		T51	1		T56	1
valid_sources[0x1d]	9587	1			T24	1		T28	1		T55	1
valid_sources[0x1e]	9704	1			T51	1		T55	3		T56	1
valid_sources[0x1f]	9694	1			T26	1		T28	2		T55	1
valid_sources[0x20]	10835	1			T28	2		T51	1		T56	1
valid_sources[0x21]	9660	1			T56	2		T103	9		T60	7
valid_sources[0x22]	10194	1			T28	2		T51	1		T42	1
valid_sources[0x23]	9515	1			T28	2		T51	2		T55	1
valid_sources[0x24]	10117	1			T28	1		T51	1		T56	7
valid_sources[0x25]	10379	1			T28	2		T56	3		T60	6
valid_sources[0x26]	10429	1			T28	1		T55	1		T56	2
valid_sources[0x27]	10231	1			T24	1		T28	1		T56	2
valid_sources[0x28]	10617	1			T23	1		T28	2		T51	1
valid_sources[0x29]	9757	1			T51	1		T56	3		T61	1
valid_sources[0x2a]	10506	1			T51	1		T55	4		T56	2
valid_sources[0x2b]	9940	1			T28	1		T51	2		T56	1
valid_sources[0x2c]	9933	1			T51	2		T55	1		T56	2
valid_sources[0x2d]	9571	1			T55	1		T60	6		T73	5
valid_sources[0x2e]	9519	1			T28	1		T55	1		T56	1
valid_sources[0x2f]	9718	1			T26	1		T51	1		T59	1
valid_sources[0x30]	9642	1			T26	1		T28	1		T56	3
valid_sources[0x31]	10189	1			T55	1		T56	2		T60	2
valid_sources[0x32]	10735	1			T51	2		T56	6		T60	1
valid_sources[0x33]	10044	1			T24	1		T51	1		T55	1
valid_sources[0x34]	10834	1			T51	1		T55	2		T56	1
valid_sources[0x35]	9874	1			T26	1		T51	1		T56	3
valid_sources[0x36]	9810	1			T28	2		T51	2		T55	2
valid_sources[0x37]	9924	1			T28	1		T60	7		T61	4
valid_sources[0x38]	9746	1			T28	2		T51	1		T55	2
valid_sources[0x39]	9568	1			T51	2		T55	3		T56	4
valid_sources[0x3a]	10169	1			T24	1		T51	1		T55	3
valid_sources[0x3b]	10241	1			T28	1		T42	1		T60	2
valid_sources[0x3c]	10221	1			T28	1		T51	1		T55	1
valid_sources[0x3d]	10852	1			T24	1		T28	2		T56	1
valid_sources[0x3e]	10135	1			T28	3		T51	1		T56	1
valid_sources[0x3f]	9474	1			T55	1		T56	1		T60	1
valid_sources[0x40]	10133	1			T60	2		T61	1		T73	4
valid_sources[0x41]	9873	1			T26	1		T60	3		T61	1
valid_sources[0x42]	10872	1			T28	3		T60	3		T61	1
valid_sources[0x43]	9771	1			T28	2		T55	2		T56	1
valid_sources[0x44]	9883	1			T28	1		T51	1		T55	1
valid_sources[0x45]	9404	1			T51	1		T54	1		T55	3
valid_sources[0x46]	9876	1			T55	3		T56	5		T59	6
valid_sources[0x47]	9572	1			T56	2		T61	2		T73	1
valid_sources[0x48]	9835	1			T28	1		T51	1		T54	1
valid_sources[0x49]	9606	1			T28	2		T51	1		T42	1
valid_sources[0x4a]	10363	1			T28	2		T29	37		T55	2
valid_sources[0x4b]	11058	1			T24	1		T55	3		T56	1
valid_sources[0x4c]	9715	1			T42	2		T60	1		T61	2
valid_sources[0x4d]	9898	1			T28	1		T51	1		T55	1
valid_sources[0x4e]	10916	1			T28	1		T55	2		T56	1
valid_sources[0x4f]	10439	1			T28	1		T55	2		T56	6
valid_sources[0x50]	9458	1			T25	17		T28	3		T51	1
valid_sources[0x51]	9461	1			T42	1		T55	2		T56	1
valid_sources[0x52]	10000	1			T55	1		T56	2		T60	3
valid_sources[0x53]	9425	1			T28	1		T55	2		T56	2
valid_sources[0x54]	10292	1			T51	1		T55	1		T59	1
valid_sources[0x55]	10177	1			T28	1		T56	1		T60	6
valid_sources[0x56]	9884	1			T28	1		T55	1		T56	1
valid_sources[0x57]	9654	1			T28	2		T51	2		T60	3
valid_sources[0x58]	9712	1			T55	1		T56	2		T57	1
valid_sources[0x59]	9868	1			T26	2		T28	1		T51	1
valid_sources[0x5a]	9927	1			T26	1		T28	1		T56	2
valid_sources[0x5b]	9918	1			T55	1		T60	3		T69	7
valid_sources[0x5c]	10462	1			T28	1		T55	1		T56	3
valid_sources[0x5d]	9654	1			T55	2		T56	3		T114	2
valid_sources[0x5e]	10368	1			T28	1		T55	1		T56	3
valid_sources[0x5f]	9581	1			T28	3		T54	1		T55	1
valid_sources[0x60]	10467	1			T28	1		T56	2		T59	1
valid_sources[0x61]	9484	1			T51	2		T55	1		T56	3
valid_sources[0x62]	9968	1			T28	1		T51	3		T73	6
valid_sources[0x63]	9886	1			T51	2		T60	3		T61	1
valid_sources[0x64]	9549	1			T51	2		T55	3		T56	3
valid_sources[0x65]	9965	1			T28	1		T56	1		T60	2
valid_sources[0x66]	9589	1			T24	3		T28	2		T42	2
valid_sources[0x67]	10237	1			T60	3		T61	2		T73	3
valid_sources[0x68]	9449	1			T28	1		T55	1		T56	4
valid_sources[0x69]	9680	1			T23	1		T28	1		T51	1
valid_sources[0x6a]	9076	1			T51	2		T55	1		T56	1
valid_sources[0x6b]	10103	1			T23	1		T28	1		T51	1
valid_sources[0x6c]	9998	1			T23	1		T24	1		T28	2
valid_sources[0x6d]	10105	1			T24	1		T28	2		T56	3
valid_sources[0x6e]	9333	1			T24	1		T28	1		T51	2
valid_sources[0x6f]	10207	1			T52	9		T56	3		T60	3
valid_sources[0x70]	9884	1			T55	1		T56	3		T60	7
valid_sources[0x71]	11316	1			T28	1		T55	3		T56	2
valid_sources[0x72]	10564	1			T28	2		T55	2		T59	1
valid_sources[0x73]	9649	1			T23	1		T28	2		T51	1
valid_sources[0x74]	9623	1			T28	1		T55	1		T60	4
valid_sources[0x75]	10453	1			T28	2		T56	2		T60	3
valid_sources[0x76]	10103	1			T60	2		T61	2		T115	1
valid_sources[0x77]	9542	1			T56	2		T60	2		T73	1
valid_sources[0x78]	9696	1			T55	1		T56	1		T60	4
valid_sources[0x79]	10527	1			T55	1		T56	2		T60	2
valid_sources[0x7a]	9686	1			T55	2		T56	1		T60	3
valid_sources[0x7b]	10088	1			T23	1		T54	1		T55	3
valid_sources[0x7c]	9799	1			T23	1		T26	1		T28	2
valid_sources[0x7d]	10320	1			T28	2		T51	2		T55	4
valid_sources[0x7e]	9677	1			T28	1		T42	1		T60	5
valid_sources[0x7f]	9882	1			T28	2		T42	1		T55	1
valid_sources[0x80]	9997	1			T28	1		T56	2		T60	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

526962

1

T22

40

T23

3

T24

40

values[0x0]

all_enables

biggest_size

782763

1

T23

7

T26

8

T28

46

values[0x1]

all_enables

biggest_size

782556

1

T23

7

T26

9

T28

56