Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5742310

1

T23

28

T25

17

T26

68

full_word

2502498

1

T22

40

T23

22

T24

40

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8244468	1			T22	40		T23	50		T24	40
auto[TlIntgErrCmd]	105	1			T25	5		T52	5		T57	3
auto[TlIntgErrData]	128	1			T25	9		T52	4		T57	4
auto[TlIntgErrBoth]	107	1			T25	6		T52	1		T57	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995357

1

T22

40

T23

4

T24

40

auto[1]

7249451

1

T23

46

T25

10

T26

86

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	417958	1			T23	1		T26	3		T28	50
auto[TlIntgErrNone]	partial	auto[1]	5324044	1			T23	27		T26	65		T28	627
auto[TlIntgErrNone]	full_word	auto[0]	577242	1			T22	40		T23	3		T24	40
auto[TlIntgErrNone]	full_word	auto[1]	1925224	1			T23	19		T26	21		T28	138
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T25	1		T52	1		T57	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T25	3		T52	3		T57	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T25	1		T110	1		T111	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T52	1		T103	1		T108	2
auto[TlIntgErrData]	partial	auto[0]	68	1			T25	3		T52	3		T57	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T25	4		T52	1		T57	2
auto[TlIntgErrData]	full_word	auto[0]	9	1			T25	2		T106	2		T109	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T57	1		T76	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T25	3		T57	1		T103	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T25	3		T52	1		T57	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T108	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T57	1		T105	1		T76	2