Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	167411	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1723969

1

T20

31

T22

107

T23

342

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	471971	1			T20	6		T22	7		T23	46
values[0x0]	656847	1			T20	13		T22	51		T23	177
values[0x1]	762562	1			T20	21		T21	7		T22	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74864	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1816516

1

T20

31

T21

5

T22

107

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8116	1			T24	2		T55	51		T47	5
valid_sources[0x01]	7009	1			T47	3		T59	1		T60	1
valid_sources[0x02]	6715	1			T24	2		T46	1		T47	4
valid_sources[0x03]	8319	1			T24	2		T47	1		T45	6
valid_sources[0x04]	6769	1			T20	4		T24	9		T47	1
valid_sources[0x05]	7757	1			T24	5		T59	1		T107	1
valid_sources[0x06]	6839	1			T24	3		T47	1		T59	6
valid_sources[0x07]	7710	1			T23	61		T24	3		T46	1
valid_sources[0x08]	7653	1			T24	1		T47	1		T63	1
valid_sources[0x09]	7639	1			T24	4		T47	5		T62	2
valid_sources[0x0a]	7165	1			T47	2		T62	1		T57	1
valid_sources[0x0b]	6811	1			T24	1		T47	2		T56	1
valid_sources[0x0c]	6510	1			T24	1		T44	42		T47	2
valid_sources[0x0d]	7764	1			T24	5		T47	5		T59	3
valid_sources[0x0e]	8171	1			T24	1		T26	1		T47	4
valid_sources[0x0f]	6765	1			T24	1		T47	3		T56	1
valid_sources[0x10]	7570	1			T23	10		T24	1		T47	2
valid_sources[0x11]	6739	1			T24	1		T47	1		T45	12
valid_sources[0x12]	6700	1			T24	5		T44	10		T46	1
valid_sources[0x13]	6123	1			T24	2		T55	51		T47	3
valid_sources[0x14]	8673	1			T21	1		T24	3		T28	26
valid_sources[0x15]	7627	1			T28	26		T59	3		T107	1
valid_sources[0x16]	7923	1			T24	2		T28	39		T46	1
valid_sources[0x17]	6847	1			T21	1		T47	1		T56	1
valid_sources[0x18]	7111	1			T24	2		T47	2		T62	11
valid_sources[0x19]	7232	1			T24	7		T63	1		T59	1
valid_sources[0x1a]	7933	1			T24	7		T47	1		T57	1
valid_sources[0x1b]	7669	1			T24	4		T28	81		T46	3
valid_sources[0x1c]	7742	1			T24	1		T55	24		T47	1
valid_sources[0x1d]	6812	1			T26	1		T47	1		T62	25
valid_sources[0x1e]	7922	1			T23	9		T24	4		T27	65
valid_sources[0x1f]	8622	1			T24	4		T47	1		T63	1
valid_sources[0x20]	6844	1			T21	1		T24	4		T26	2
valid_sources[0x21]	7693	1			T24	4		T46	3		T47	2
valid_sources[0x22]	7593	1			T24	5		T45	10		T59	2
valid_sources[0x23]	7499	1			T24	4		T44	10		T47	1
valid_sources[0x24]	7822	1			T24	1		T45	18		T57	1
valid_sources[0x25]	7156	1			T24	2		T46	1		T47	3
valid_sources[0x26]	6981	1			T47	4		T62	3		T63	1
valid_sources[0x27]	7355	1			T24	1		T46	3		T47	4
valid_sources[0x28]	6172	1			T24	2		T26	3		T63	1
valid_sources[0x29]	7428	1			T24	2		T47	4		T57	1
valid_sources[0x2a]	7754	1			T47	1		T57	1		T59	2
valid_sources[0x2b]	7523	1			T24	1		T47	1		T56	1
valid_sources[0x2c]	7146	1			T24	1		T46	3		T47	2
valid_sources[0x2d]	9225	1			T47	1		T57	3		T59	2
valid_sources[0x2e]	7807	1			T24	6		T47	1		T57	2
valid_sources[0x2f]	8444	1			T24	3		T47	1		T57	1
valid_sources[0x30]	7926	1			T23	3		T24	5		T57	1
valid_sources[0x31]	7824	1			T20	4		T24	2		T55	21
valid_sources[0x32]	8085	1			T24	1		T47	2		T45	20
valid_sources[0x33]	7402	1			T24	4		T47	4		T57	1
valid_sources[0x34]	8363	1			T47	1		T63	1		T57	1
valid_sources[0x35]	8211	1			T24	2		T47	2		T64	9
valid_sources[0x36]	7610	1			T24	3		T44	10		T46	1
valid_sources[0x37]	7435	1			T24	4		T47	2		T57	2
valid_sources[0x38]	8340	1			T24	2		T47	2		T45	2
valid_sources[0x39]	6815	1			T24	1		T47	2		T57	2
valid_sources[0x3a]	6941	1			T24	1		T47	2		T57	2
valid_sources[0x3b]	6930	1			T24	2		T46	2		T63	1
valid_sources[0x3c]	7103	1			T24	5		T26	2		T47	8
valid_sources[0x3d]	7611	1			T24	1		T107	1		T58	2
valid_sources[0x3e]	6702	1			T24	4		T44	10		T47	3
valid_sources[0x3f]	6773	1			T57	1		T60	2		T61	3
valid_sources[0x40]	6532	1			T20	14		T24	3		T47	2
valid_sources[0x41]	8144	1			T22	9		T46	4		T47	6
valid_sources[0x42]	7852	1			T24	3		T47	3		T63	1
valid_sources[0x43]	7130	1			T24	5		T27	92		T47	3
valid_sources[0x44]	8134	1			T24	1		T47	1		T57	4
valid_sources[0x45]	7541	1			T24	1		T26	2		T46	2
valid_sources[0x46]	9299	1			T20	1		T24	1		T47	2
valid_sources[0x47]	7817	1			T24	1		T26	1		T29	8
valid_sources[0x48]	6976	1			T47	2		T45	2		T59	1
valid_sources[0x49]	6933	1			T21	1		T24	4		T29	3
valid_sources[0x4a]	6558	1			T23	2		T24	1		T26	1
valid_sources[0x4b]	7271	1			T24	5		T28	11		T47	3
valid_sources[0x4c]	7365	1			T24	3		T44	10		T46	2
valid_sources[0x4d]	7195	1			T24	1		T46	4		T47	6
valid_sources[0x4e]	7118	1			T24	4		T59	5		T107	1
valid_sources[0x4f]	7461	1			T24	1		T46	1		T47	2
valid_sources[0x50]	5973	1			T23	1		T26	1		T47	2
valid_sources[0x51]	7098	1			T47	1		T62	2		T56	1
valid_sources[0x52]	7905	1			T24	3		T27	141		T46	1
valid_sources[0x53]	7536	1			T24	5		T47	3		T59	3
valid_sources[0x54]	7427	1			T24	1		T59	2		T107	3
valid_sources[0x55]	6717	1			T24	3		T26	1		T46	13
valid_sources[0x56]	7504	1			T63	1		T107	1		T58	3
valid_sources[0x57]	6702	1			T26	1		T47	4		T59	3
valid_sources[0x58]	6801	1			T24	1		T47	2		T45	9
valid_sources[0x59]	7530	1			T20	3		T47	2		T56	1
valid_sources[0x5a]	6627	1			T22	1		T24	6		T26	7
valid_sources[0x5b]	8035	1			T24	3		T46	1		T47	4
valid_sources[0x5c]	7180	1			T24	10		T26	1		T47	2
valid_sources[0x5d]	7809	1			T23	10		T24	2		T26	1
valid_sources[0x5e]	6815	1			T24	6		T47	2		T59	1
valid_sources[0x5f]	7224	1			T24	2		T47	3		T57	1
valid_sources[0x60]	7324	1			T47	3		T59	3		T58	1
valid_sources[0x61]	8027	1			T24	1		T28	11		T46	1
valid_sources[0x62]	8195	1			T24	2		T47	2		T107	2
valid_sources[0x63]	6504	1			T22	11		T24	2		T47	3
valid_sources[0x64]	6614	1			T22	5		T47	3		T57	2
valid_sources[0x65]	8341	1			T24	2		T47	1		T62	3
valid_sources[0x66]	7302	1			T22	4		T24	2		T26	5
valid_sources[0x67]	6329	1			T24	3		T46	1		T47	1
valid_sources[0x68]	7578	1			T24	4		T26	3		T27	34
valid_sources[0x69]	8075	1			T24	2		T26	1		T46	1
valid_sources[0x6a]	7050	1			T24	4		T29	109		T46	1
valid_sources[0x6b]	7340	1			T24	3		T46	2		T47	1
valid_sources[0x6c]	7768	1			T29	24		T55	2		T47	1
valid_sources[0x6d]	7370	1			T46	2		T47	2		T59	3
valid_sources[0x6e]	7138	1			T44	10		T64	15		T60	1
valid_sources[0x6f]	7867	1			T47	2		T59	3		T107	4
valid_sources[0x70]	7417	1			T46	4		T47	5		T63	1
valid_sources[0x71]	7324	1			T24	3		T26	3		T47	2
valid_sources[0x72]	7103	1			T23	30		T24	1		T26	3
valid_sources[0x73]	7452	1			T24	4		T46	9		T47	2
valid_sources[0x74]	7546	1			T26	1		T29	203		T44	20
valid_sources[0x75]	7722	1			T47	2		T59	2		T58	1
valid_sources[0x76]	7907	1			T24	3		T47	1		T57	1
valid_sources[0x77]	7688	1			T24	3		T47	2		T57	2
valid_sources[0x78]	7258	1			T24	2		T26	6		T47	4
valid_sources[0x79]	6113	1			T24	2		T46	6		T47	3
valid_sources[0x7a]	7984	1			T23	4		T24	2		T47	1
valid_sources[0x7b]	7835	1			T29	16		T47	3		T57	2
valid_sources[0x7c]	6182	1			T24	1		T25	10		T46	2
valid_sources[0x7d]	7879	1			T46	2		T47	3		T63	1
valid_sources[0x7e]	7724	1			T26	1		T47	1		T59	4
valid_sources[0x7f]	8129	1			T23	20		T26	1		T47	2
valid_sources[0x80]	7395	1			T20	5		T24	1		T28	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

435776

1

T22

7

T23

9

T24

145

values[0x0]

all_enables

biggest_size

643626

1

T20

12

T22

51

T23

165

values[0x1]

all_enables

biggest_size

644567

1

T20

19

T22

49

T23

168

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	383935	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1689426

1

T21

198

T23

40

T24

348

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	469974	1			T21	51		T23	40		T24	91
values[0x0]	663215	1			T21	76		T24	142		T27	167
values[0x1]	940172	1			T21	147		T24	203		T27	184

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145260	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1928101

1

T21

240

T23

40

T24

402

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8919	1			T55	3		T44	1		T59	3
valid_sources[0x01]	7809	1			T23	2		T27	4		T29	3
valid_sources[0x02]	8580	1			T27	2		T55	1		T59	3
valid_sources[0x03]	7696	1			T27	4		T55	1		T46	2
valid_sources[0x04]	8294	1			T27	1		T29	2		T45	1
valid_sources[0x05]	8095	1			T55	3		T45	1		T107	2
valid_sources[0x06]	8929	1			T27	3		T29	2		T55	1
valid_sources[0x07]	7628	1			T29	2		T59	3		T107	1
valid_sources[0x08]	6555	1			T27	2		T29	1		T55	2
valid_sources[0x09]	8395	1			T23	1		T59	2		T80	1
valid_sources[0x0a]	8431	1			T27	3		T55	1		T108	1
valid_sources[0x0b]	7008	1			T29	2		T80	1		T109	2
valid_sources[0x0c]	7855	1			T27	3		T29	1		T55	1
valid_sources[0x0d]	6537	1			T27	2		T29	3		T55	1
valid_sources[0x0e]	7936	1			T27	8		T29	1		T59	6
valid_sources[0x0f]	8079	1			T29	3		T46	1		T107	1
valid_sources[0x10]	9528	1			T29	3		T55	1		T59	3
valid_sources[0x11]	7985	1			T27	2		T80	1		T110	1
valid_sources[0x12]	7193	1			T29	1		T55	3		T59	4
valid_sources[0x13]	7802	1			T27	3		T29	2		T55	2
valid_sources[0x14]	8571	1			T29	5		T107	1		T80	2
valid_sources[0x15]	7790	1			T27	6		T55	3		T110	3
valid_sources[0x16]	8626	1			T59	2		T107	1		T110	7
valid_sources[0x17]	7988	1			T27	2		T29	2		T55	2
valid_sources[0x18]	8643	1			T107	2		T80	1		T110	1
valid_sources[0x19]	8312	1			T29	2		T57	42		T110	1
valid_sources[0x1a]	8301	1			T27	11		T29	2		T107	1
valid_sources[0x1b]	8891	1			T27	1		T29	2		T55	3
valid_sources[0x1c]	10122	1			T27	5		T28	18		T29	1
valid_sources[0x1d]	7561	1			T29	1		T55	2		T44	1
valid_sources[0x1e]	8306	1			T27	3		T55	3		T45	2
valid_sources[0x1f]	7478	1			T27	3		T29	2		T45	1
valid_sources[0x20]	7600	1			T27	1		T29	3		T55	1
valid_sources[0x21]	8740	1			T27	2		T55	1		T57	2
valid_sources[0x22]	7058	1			T27	3		T29	1		T55	4
valid_sources[0x23]	10830	1			T29	1		T55	1		T44	1
valid_sources[0x24]	8419	1			T27	1		T59	5		T110	1
valid_sources[0x25]	8754	1			T29	4		T46	1		T59	1
valid_sources[0x26]	9062	1			T27	6		T29	2		T44	1
valid_sources[0x27]	7382	1			T29	1		T55	2		T44	1
valid_sources[0x28]	8933	1			T27	4		T29	4		T59	3
valid_sources[0x29]	8172	1			T29	1		T110	2		T108	7
valid_sources[0x2a]	7638	1			T27	6		T29	1		T55	1
valid_sources[0x2b]	7567	1			T27	10		T29	1		T55	1
valid_sources[0x2c]	8958	1			T29	2		T44	1		T59	2
valid_sources[0x2d]	9067	1			T29	2		T44	2		T59	5
valid_sources[0x2e]	7776	1			T46	1		T59	4		T111	1
valid_sources[0x2f]	8796	1			T55	1		T46	1		T59	5
valid_sources[0x30]	7553	1			T27	15		T29	2		T55	3
valid_sources[0x31]	8497	1			T29	2		T47	1		T59	1
valid_sources[0x32]	8015	1			T27	3		T29	2		T107	1
valid_sources[0x33]	8091	1			T23	3		T29	1		T55	1
valid_sources[0x34]	7837	1			T27	3		T29	4		T59	3
valid_sources[0x35]	7307	1			T23	1		T27	2		T29	1
valid_sources[0x36]	7879	1			T29	2		T55	1		T59	2
valid_sources[0x37]	7346	1			T27	2		T55	2		T80	1
valid_sources[0x38]	7324	1			T27	6		T29	1		T55	1
valid_sources[0x39]	8082	1			T27	3		T29	1		T55	1
valid_sources[0x3a]	7350	1			T27	2		T57	86		T110	2
valid_sources[0x3b]	7183	1			T29	2		T55	4		T46	1
valid_sources[0x3c]	8485	1			T29	2		T55	1		T59	3
valid_sources[0x3d]	8875	1			T29	1		T55	3		T59	1
valid_sources[0x3e]	9162	1			T29	2		T55	1		T107	1
valid_sources[0x3f]	8369	1			T27	2		T29	2		T59	6
valid_sources[0x40]	7484	1			T29	4		T59	2		T107	1
valid_sources[0x41]	7881	1			T27	2		T29	1		T80	1
valid_sources[0x42]	8097	1			T29	2		T46	2		T80	1
valid_sources[0x43]	7045	1			T46	1		T108	3		T2	236
valid_sources[0x44]	6967	1			T57	23		T59	2		T110	1
valid_sources[0x45]	7457	1			T23	1		T29	4		T55	1
valid_sources[0x46]	8173	1			T27	1		T29	2		T55	3
valid_sources[0x47]	7435	1			T29	1		T55	3		T59	3
valid_sources[0x48]	7948	1			T27	4		T55	2		T45	2
valid_sources[0x49]	7845	1			T29	2		T55	2		T59	2
valid_sources[0x4a]	6991	1			T29	2		T44	1		T45	3
valid_sources[0x4b]	7814	1			T29	1		T44	1		T59	2
valid_sources[0x4c]	7783	1			T23	2		T55	2		T44	2
valid_sources[0x4d]	7175	1			T27	1		T55	1		T57	6
valid_sources[0x4e]	7065	1			T27	3		T29	2		T44	1
valid_sources[0x4f]	9287	1			T29	1		T59	1		T110	1
valid_sources[0x50]	7106	1			T27	1		T55	1		T110	4
valid_sources[0x51]	7491	1			T27	2		T55	1		T59	2
valid_sources[0x52]	8568	1			T29	2		T55	2		T59	5
valid_sources[0x53]	7128	1			T29	2		T55	2		T59	4
valid_sources[0x54]	7756	1			T27	6		T59	6		T107	1
valid_sources[0x55]	8078	1			T27	4		T29	1		T55	1
valid_sources[0x56]	6975	1			T27	3		T29	2		T55	1
valid_sources[0x57]	9208	1			T27	3		T29	3		T55	2
valid_sources[0x58]	7998	1			T27	1		T29	2		T55	1
valid_sources[0x59]	8529	1			T29	2		T55	2		T59	2
valid_sources[0x5a]	7976	1			T27	3		T29	3		T55	2
valid_sources[0x5b]	7052	1			T29	3		T59	3		T107	1
valid_sources[0x5c]	6927	1			T27	1		T55	2		T44	1
valid_sources[0x5d]	7787	1			T29	1		T55	1		T59	1
valid_sources[0x5e]	7140	1			T29	4		T55	1		T56	1
valid_sources[0x5f]	9645	1			T29	1		T110	1		T109	1
valid_sources[0x60]	7760	1			T23	3		T27	2		T55	2
valid_sources[0x61]	7359	1			T27	1		T59	3		T107	1
valid_sources[0x62]	7275	1			T29	2		T55	1		T46	3
valid_sources[0x63]	9103	1			T29	3		T59	1		T61	1
valid_sources[0x64]	9933	1			T27	2		T29	1		T59	1
valid_sources[0x65]	7454	1			T29	1		T55	1		T80	1
valid_sources[0x66]	8784	1			T27	7		T29	3		T55	2
valid_sources[0x67]	9294	1			T29	2		T47	1		T45	1
valid_sources[0x68]	8175	1			T29	4		T55	1		T107	2
valid_sources[0x69]	8730	1			T27	2		T29	2		T55	1
valid_sources[0x6a]	7292	1			T27	1		T29	3		T80	2
valid_sources[0x6b]	7416	1			T27	1		T29	1		T78	1
valid_sources[0x6c]	9524	1			T27	2		T29	1		T45	1
valid_sources[0x6d]	8247	1			T27	2		T29	2		T109	1
valid_sources[0x6e]	8737	1			T55	5		T59	2		T80	1
valid_sources[0x6f]	9316	1			T29	1		T55	2		T46	1
valid_sources[0x70]	8615	1			T27	2		T29	1		T59	1
valid_sources[0x71]	7548	1			T29	3		T55	1		T44	2
valid_sources[0x72]	6913	1			T27	5		T55	1		T110	2
valid_sources[0x73]	7119	1			T29	1		T59	1		T106	2
valid_sources[0x74]	8998	1			T29	1		T55	3		T44	1
valid_sources[0x75]	6945	1			T27	6		T29	1		T55	1
valid_sources[0x76]	8163	1			T27	1		T29	1		T59	2
valid_sources[0x77]	6715	1			T23	2		T27	2		T55	1
valid_sources[0x78]	7240	1			T55	2		T59	2		T80	1
valid_sources[0x79]	6948	1			T29	1		T55	3		T59	4
valid_sources[0x7a]	9326	1			T29	1		T55	1		T107	1
valid_sources[0x7b]	6658	1			T23	2		T55	1		T59	6
valid_sources[0x7c]	7276	1			T29	1		T47	1		T59	1
valid_sources[0x7d]	8600	1			T27	4		T55	1		T45	2
valid_sources[0x7e]	7811	1			T27	6		T55	1		T59	3
valid_sources[0x7f]	6439	1			T27	1		T29	1		T55	1
valid_sources[0x80]	8984	1			T29	2		T55	1		T46	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

426703

1

T21

51

T23

40

T24

91

values[0x0]

all_enables

biggest_size

631288

1

T21

67

T24

131

T27

161

values[0x1]

all_enables

biggest_size

631435

1

T21

80

T24

126

T27

147