Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4663537

1

T21

812

T24

1677

T27

923

full_word

2022235

1

T21

254

T23

40

T24

472

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6685472	1			T21	1066		T23	40		T24	2149
auto[TlIntgErrCmd]	101	1			T28	4		T47	13		T58	2
auto[TlIntgErrData]	97	1			T28	9		T47	3		T58	4
auto[TlIntgErrBoth]	102	1			T28	7		T47	4		T58	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

808100

1

T21

98

T23

40

T24

233

auto[1]

5877672

1

T21

968

T24

1916

T27

1239

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	340441	1			T21	38		T24	129		T27	40
auto[TlIntgErrNone]	partial	auto[1]	4322817	1			T21	774		T24	1548		T27	883
auto[TlIntgErrNone]	full_word	auto[0]	467520	1			T21	60		T23	40		T24	104
auto[TlIntgErrNone]	full_word	auto[1]	1554694	1			T21	194		T24	368		T27	356
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T28	1		T47	7		T61	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T28	3		T47	6		T58	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T102	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T58	1		T103	1		T101	2
auto[TlIntgErrData]	partial	auto[0]	47	1			T28	6		T47	2		T58	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T28	2		T47	1		T58	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T61	1		T104	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T28	1		T78	1		T101	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T28	3		T47	2		T61	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T28	4		T47	2		T58	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T61	1		T78	1		T105	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T105	1		-	-		-	-