Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3028190

1

T2

191

T7

204

T9

55

full_word

1293476

1

T1

6

T2

22

T4

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4321406	1			T1	6		T2	213		T4	2
auto[TlIntgErrCmd]	79	1			T48	8		T49	2		T50	8
auto[TlIntgErrData]	83	1			T48	4		T49	2		T50	7
auto[TlIntgErrBoth]	98	1			T48	8		T49	6		T50	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

519270

1

T1

6

T2

213

T4

2

auto[1]

3802396

1

T13

297158

T14

132669

T15

154642

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	220712	1			T2	191		T7	204		T9	55
auto[TlIntgErrNone]	partial	auto[1]	2807246	1			T13	220660		T14	97755		T15	114636
auto[TlIntgErrNone]	full_word	auto[0]	298442	1			T1	6		T2	22		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	995006	1			T13	76498		T14	34914		T15	40006
auto[TlIntgErrCmd]	partial	auto[0]	25	1			T48	2		T49	1		T50	3
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T48	5		T49	1		T50	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T48	1		T86	2		T118	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T86	1		T118	2		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1			T48	1		T49	2		T50	3
auto[TlIntgErrData]	partial	auto[1]	33	1			T48	1		T50	4		T86	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T48	1		T116	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T48	1		T83	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T48	2		T49	3		T50	4
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T48	6		T49	2		T50	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T86	1		T121	1		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T49	1		T115	1		T120	2