Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	210061	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2109989

1

T20

169

T27

230

T28

113

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	578890	1			T20	69		T27	67		T28	6
values[0x0]	805028	1			T20	94		T27	83		T28	56
values[0x1]	936132	1			T20	88		T27	121		T28	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	93281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2226769

1

T20

193

T27

255

T28

113

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9677	1			T20	2		T30	3		T33	5
valid_sources[0x01]	9293	1			T20	2		T27	3		T33	1
valid_sources[0x02]	10741	1			T28	2		T33	3		T34	1
valid_sources[0x03]	9019	1			T28	3		T29	10		T33	1
valid_sources[0x04]	8752	1			T20	1		T30	1		T33	2
valid_sources[0x05]	9061	1			T27	4		T30	3		T31	3
valid_sources[0x06]	8761	1			T20	1		T27	1		T28	4
valid_sources[0x07]	8964	1			T27	5		T30	1		T33	1
valid_sources[0x08]	9954	1			T33	2		T35	1		T57	1
valid_sources[0x09]	8246	1			T27	1		T31	1		T56	6
valid_sources[0x0a]	9347	1			T29	30		T33	2		T35	2
valid_sources[0x0b]	9157	1			T20	1		T28	2		T30	1
valid_sources[0x0c]	8650	1			T27	2		T28	4		T33	3
valid_sources[0x0d]	9838	1			T34	4		T35	3		T57	1
valid_sources[0x0e]	8461	1			T27	1		T28	1		T33	1
valid_sources[0x0f]	8624	1			T27	1		T56	8		T66	2
valid_sources[0x10]	8871	1			T20	2		T34	3		T56	3
valid_sources[0x11]	8870	1			T27	3		T28	2		T30	7
valid_sources[0x12]	8813	1			T33	4		T56	2		T66	1
valid_sources[0x13]	8960	1			T30	1		T33	1		T35	4
valid_sources[0x14]	9343	1			T20	3		T27	1		T30	1
valid_sources[0x15]	8999	1			T30	2		T33	2		T58	2
valid_sources[0x16]	9894	1			T20	2		T28	2		T29	53
valid_sources[0x17]	9799	1			T33	1		T34	6		T66	2
valid_sources[0x18]	10049	1			T28	1		T33	1		T35	2
valid_sources[0x19]	9597	1			T33	5		T34	3		T35	1
valid_sources[0x1a]	9887	1			T30	2		T56	2		T66	1
valid_sources[0x1b]	9096	1			T33	5		T56	1		T85	1
valid_sources[0x1c]	9273	1			T27	1		T28	2		T30	1
valid_sources[0x1d]	8825	1			T20	1		T33	1		T35	1
valid_sources[0x1e]	8913	1			T27	2		T33	2		T34	3
valid_sources[0x1f]	9427	1			T27	15		T30	1		T33	2
valid_sources[0x20]	9209	1			T20	5		T33	2		T35	1
valid_sources[0x21]	8679	1			T29	20		T33	6		T34	2
valid_sources[0x22]	9052	1			T20	9		T27	1		T29	3
valid_sources[0x23]	8793	1			T20	1		T27	3		T33	2
valid_sources[0x24]	8903	1			T30	3		T33	1		T34	6
valid_sources[0x25]	8642	1			T20	2		T28	1		T29	10
valid_sources[0x26]	8839	1			T33	1		T35	2		T66	1
valid_sources[0x27]	8802	1			T30	5		T33	2		T35	1
valid_sources[0x28]	9286	1			T33	2		T56	4		T58	1
valid_sources[0x29]	8398	1			T20	1		T33	3		T56	6
valid_sources[0x2a]	8735	1			T20	4		T33	3		T56	1
valid_sources[0x2b]	9475	1			T27	1		T33	1		T56	1
valid_sources[0x2c]	9514	1			T27	1		T29	6		T30	4
valid_sources[0x2d]	9036	1			T33	2		T56	1		T58	1
valid_sources[0x2e]	9598	1			T27	3		T29	54		T30	1
valid_sources[0x2f]	8882	1			T30	2		T33	2		T35	2
valid_sources[0x30]	9205	1			T27	3		T33	1		T34	1
valid_sources[0x31]	8669	1			T20	3		T27	4		T30	1
valid_sources[0x32]	8995	1			T20	2		T27	1		T30	1
valid_sources[0x33]	9193	1			T20	8		T27	5		T33	1
valid_sources[0x34]	8774	1			T28	1		T30	9		T33	2
valid_sources[0x35]	8743	1			T33	3		T34	4		T56	6
valid_sources[0x36]	7877	1			T20	4		T28	3		T30	3
valid_sources[0x37]	9518	1			T27	4		T30	8		T33	1
valid_sources[0x38]	9137	1			T28	1		T33	3		T34	3
valid_sources[0x39]	8474	1			T33	2		T34	2		T35	1
valid_sources[0x3a]	9025	1			T27	3		T33	3		T34	2
valid_sources[0x3b]	8339	1			T27	8		T34	23		T56	3
valid_sources[0x3c]	8938	1			T29	45		T33	4		T34	4
valid_sources[0x3d]	8726	1			T27	2		T33	1		T34	4
valid_sources[0x3e]	8953	1			T30	1		T33	2		T35	2
valid_sources[0x3f]	9713	1			T33	1		T34	1		T66	1
valid_sources[0x40]	9833	1			T27	1		T30	1		T33	1
valid_sources[0x41]	8752	1			T27	1		T28	2		T33	1
valid_sources[0x42]	9152	1			T28	1		T33	1		T34	11
valid_sources[0x43]	8395	1			T30	2		T33	1		T56	1
valid_sources[0x44]	9322	1			T27	1		T31	5		T33	2
valid_sources[0x45]	9699	1			T20	10		T30	7		T33	2
valid_sources[0x46]	9312	1			T34	1		T35	2		T56	9
valid_sources[0x47]	9334	1			T20	1		T33	4		T34	8
valid_sources[0x48]	8968	1			T27	2		T28	4		T33	6
valid_sources[0x49]	9236	1			T33	3		T35	2		T56	4
valid_sources[0x4a]	8963	1			T27	3		T33	2		T34	1
valid_sources[0x4b]	10783	1			T28	2		T33	1		T56	6
valid_sources[0x4c]	9089	1			T28	2		T30	1		T33	1
valid_sources[0x4d]	8856	1			T27	4		T28	1		T35	1
valid_sources[0x4e]	9208	1			T20	3		T27	7		T29	10
valid_sources[0x4f]	7992	1			T27	3		T28	1		T31	5
valid_sources[0x50]	9001	1			T20	9		T30	1		T33	3
valid_sources[0x51]	8454	1			T33	2		T35	1		T56	2
valid_sources[0x52]	8817	1			T30	1		T35	2		T58	2
valid_sources[0x53]	8912	1			T33	3		T34	3		T35	1
valid_sources[0x54]	9486	1			T27	2		T33	2		T34	3
valid_sources[0x55]	9948	1			T27	1		T30	2		T33	2
valid_sources[0x56]	9787	1			T33	1		T34	7		T56	2
valid_sources[0x57]	8968	1			T27	1		T28	1		T33	3
valid_sources[0x58]	9550	1			T27	1		T30	2		T33	1
valid_sources[0x59]	9518	1			T27	3		T30	2		T33	1
valid_sources[0x5a]	9523	1			T33	1		T35	1		T56	5
valid_sources[0x5b]	8539	1			T33	3		T56	6		T66	2
valid_sources[0x5c]	9076	1			T20	6		T30	3		T33	2
valid_sources[0x5d]	7994	1			T27	1		T30	1		T33	3
valid_sources[0x5e]	9219	1			T28	1		T33	2		T34	5
valid_sources[0x5f]	9593	1			T27	2		T33	2		T34	3
valid_sources[0x60]	9250	1			T27	5		T33	1		T34	8
valid_sources[0x61]	9033	1			T20	4		T27	4		T33	3
valid_sources[0x62]	9944	1			T20	2		T33	2		T34	5
valid_sources[0x63]	8719	1			T27	2		T35	1		T56	3
valid_sources[0x64]	8270	1			T20	2		T27	4		T28	2
valid_sources[0x65]	9243	1			T20	8		T30	1		T33	3
valid_sources[0x66]	9402	1			T20	2		T30	15		T35	1
valid_sources[0x67]	9473	1			T30	5		T33	3		T34	5
valid_sources[0x68]	9163	1			T27	4		T107	1		T43	1
valid_sources[0x69]	8731	1			T31	2		T33	1		T34	2
valid_sources[0x6a]	8670	1			T30	1		T33	2		T34	3
valid_sources[0x6b]	8185	1			T33	2		T35	2		T56	5
valid_sources[0x6c]	9384	1			T20	1		T33	2		T34	1
valid_sources[0x6d]	9690	1			T20	1		T27	3		T28	1
valid_sources[0x6e]	10379	1			T27	1		T33	3		T34	2
valid_sources[0x6f]	9005	1			T27	1		T30	3		T56	1
valid_sources[0x70]	8869	1			T27	1		T33	1		T56	1
valid_sources[0x71]	10024	1			T20	4		T27	1		T30	2
valid_sources[0x72]	7714	1			T33	2		T34	4		T35	3
valid_sources[0x73]	9778	1			T28	2		T30	1		T33	2
valid_sources[0x74]	8577	1			T20	2		T27	1		T33	1
valid_sources[0x75]	9845	1			T30	1		T33	2		T34	1
valid_sources[0x76]	9045	1			T27	1		T66	2		T57	6
valid_sources[0x77]	8502	1			T20	2		T27	3		T30	1
valid_sources[0x78]	10509	1			T28	4		T33	2		T34	4
valid_sources[0x79]	8695	1			T20	4		T27	3		T33	3
valid_sources[0x7a]	9808	1			T20	1		T33	2		T34	3
valid_sources[0x7b]	8380	1			T20	2		T27	3		T29	20
valid_sources[0x7c]	8641	1			T20	5		T28	1		T33	3
valid_sources[0x7d]	8516	1			T20	2		T27	2		T28	1
valid_sources[0x7e]	8905	1			T27	2		T29	10		T33	1
valid_sources[0x7f]	9348	1			T20	4		T33	3		T35	2
valid_sources[0x80]	8821	1			T33	1		T58	1		T67	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

533737

1

T20

5

T27

65

T28

6

values[0x0]

all_enables

biggest_size

788455

1

T20

88

T27

82

T28

56

values[0x1]

all_enables

biggest_size

787797

1

T20

76

T27

83

T28

51

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	477393	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2104068

1

T27

285

T29

40

T33

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	582146	1			T20	6		T27	55		T29	40
values[0x0]	827527	1			T20	2		T27	113		T33	3
values[0x1]	1171788	1			T27	159		T33	4		T34	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	181145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2400316

1

T20

4

T27

314

T29

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10765	1			T27	3		T29	2		T35	8
valid_sources[0x01]	10278	1			T59	2		T63	1		T121	1
valid_sources[0x02]	10023	1			T27	1		T56	1		T59	2
valid_sources[0x03]	9773	1			T27	2		T57	1		T59	2
valid_sources[0x04]	9419	1			T27	1		T62	4		T63	7
valid_sources[0x05]	10813	1			T56	1		T60	1		T122	1
valid_sources[0x06]	9593	1			T56	1		T59	1		T61	1
valid_sources[0x07]	9696	1			T27	3		T56	2		T59	2
valid_sources[0x08]	9419	1			T27	1		T56	2		T62	2
valid_sources[0x09]	10109	1			T27	2		T59	3		T122	1
valid_sources[0x0a]	9233	1			T56	3		T57	1		T59	3
valid_sources[0x0b]	10940	1			T27	3		T29	2		T56	3
valid_sources[0x0c]	9913	1			T27	1		T56	4		T59	1
valid_sources[0x0d]	9241	1			T27	3		T56	5		T57	1
valid_sources[0x0e]	9990	1			T27	4		T29	3		T58	1
valid_sources[0x0f]	10924	1			T33	16		T56	4		T62	1
valid_sources[0x10]	10003	1			T56	9		T57	1		T122	1
valid_sources[0x11]	11130	1			T27	1		T58	1		T59	3
valid_sources[0x12]	10593	1			T27	3		T56	2		T59	5
valid_sources[0x13]	9791	1			T59	3		T74	1		T122	2
valid_sources[0x14]	9743	1			T58	1		T59	3		T122	1
valid_sources[0x15]	10014	1			T56	1		T57	3		T62	1
valid_sources[0x16]	9514	1			T27	1		T56	2		T122	4
valid_sources[0x17]	10048	1			T56	2		T59	1		T74	1
valid_sources[0x18]	10297	1			T27	2		T56	4		T59	3
valid_sources[0x19]	9782	1			T56	1		T74	1		T122	2
valid_sources[0x1a]	10089	1			T27	1		T59	1		T63	6
valid_sources[0x1b]	10766	1			T56	2		T58	1		T59	2
valid_sources[0x1c]	9562	1			T27	4		T29	1		T59	1
valid_sources[0x1d]	10107	1			T27	2		T59	1		T62	1
valid_sources[0x1e]	9340	1			T27	2		T56	5		T58	1
valid_sources[0x1f]	10129	1			T56	1		T57	1		T74	1
valid_sources[0x20]	10998	1			T59	1		T63	1		T74	2
valid_sources[0x21]	10373	1			T59	2		T62	6		T74	2
valid_sources[0x22]	10138	1			T27	2		T56	5		T59	5
valid_sources[0x23]	10180	1			T56	2		T59	2		T63	2
valid_sources[0x24]	9981	1			T27	3		T59	2		T62	11
valid_sources[0x25]	9209	1			T56	1		T57	1		T59	1
valid_sources[0x26]	10438	1			T27	1		T56	2		T59	1
valid_sources[0x27]	9952	1			T59	3		T62	2		T122	3
valid_sources[0x28]	9264	1			T27	2		T56	1		T58	1
valid_sources[0x29]	9065	1			T56	4		T59	4		T63	3
valid_sources[0x2a]	9816	1			T27	2		T57	1		T59	1
valid_sources[0x2b]	9338	1			T27	3		T56	4		T59	4
valid_sources[0x2c]	10277	1			T27	4		T74	1		T123	2
valid_sources[0x2d]	9566	1			T27	1		T59	5		T42	1
valid_sources[0x2e]	10022	1			T27	3		T59	2		T42	1
valid_sources[0x2f]	9622	1			T27	3		T56	4		T59	3
valid_sources[0x30]	9844	1			T27	2		T56	1		T59	2
valid_sources[0x31]	10609	1			T29	2		T56	4		T58	1
valid_sources[0x32]	10399	1			T56	2		T113	1		T123	4
valid_sources[0x33]	11028	1			T56	1		T59	1		T74	1
valid_sources[0x34]	10128	1			T27	1		T56	1		T59	1
valid_sources[0x35]	9310	1			T56	5		T62	4		T63	2
valid_sources[0x36]	9388	1			T59	2		T74	2		T123	5
valid_sources[0x37]	10066	1			T27	2		T56	3		T59	2
valid_sources[0x38]	11134	1			T27	2		T29	1		T59	1
valid_sources[0x39]	9308	1			T27	2		T58	2		T59	3
valid_sources[0x3a]	10434	1			T29	1		T56	1		T62	2
valid_sources[0x3b]	9651	1			T27	2		T56	2		T58	1
valid_sources[0x3c]	9608	1			T27	1		T56	5		T59	2
valid_sources[0x3d]	10167	1			T27	1		T56	2		T59	1
valid_sources[0x3e]	9905	1			T27	4		T56	3		T59	2
valid_sources[0x3f]	10407	1			T27	1		T29	1		T58	1
valid_sources[0x40]	10439	1			T27	4		T42	1		T63	2
valid_sources[0x41]	9916	1			T27	3		T56	5		T57	1
valid_sources[0x42]	8838	1			T27	1		T29	1		T56	1
valid_sources[0x43]	11209	1			T27	3		T56	1		T59	3
valid_sources[0x44]	9707	1			T56	4		T58	1		T59	3
valid_sources[0x45]	10256	1			T56	1		T59	5		T74	2
valid_sources[0x46]	9819	1			T56	1		T57	1		T59	2
valid_sources[0x47]	10186	1			T56	2		T59	2		T42	1
valid_sources[0x48]	9906	1			T27	3		T59	3		T62	6
valid_sources[0x49]	11112	1			T27	3		T56	1		T57	1
valid_sources[0x4a]	9411	1			T27	1		T56	3		T59	2
valid_sources[0x4b]	9230	1			T27	1		T56	5		T58	1
valid_sources[0x4c]	10157	1			T56	2		T122	2		T123	2
valid_sources[0x4d]	9141	1			T62	1		T74	1		T124	1
valid_sources[0x4e]	11248	1			T27	1		T57	1		T59	2
valid_sources[0x4f]	10598	1			T27	4		T56	7		T122	2
valid_sources[0x50]	9643	1			T27	2		T56	1		T59	5
valid_sources[0x51]	10275	1			T27	3		T59	1		T61	1
valid_sources[0x52]	9761	1			T59	2		T61	1		T122	1
valid_sources[0x53]	9152	1			T27	2		T56	2		T57	1
valid_sources[0x54]	9408	1			T27	2		T56	5		T57	1
valid_sources[0x55]	10401	1			T56	2		T58	1		T59	3
valid_sources[0x56]	9442	1			T27	3		T56	1		T58	2
valid_sources[0x57]	9739	1			T56	1		T59	3		T123	6
valid_sources[0x58]	10023	1			T35	1		T56	1		T59	1
valid_sources[0x59]	10245	1			T56	8		T58	1		T59	2
valid_sources[0x5a]	10096	1			T27	1		T56	1		T74	2
valid_sources[0x5b]	10107	1			T27	1		T58	1		T62	8
valid_sources[0x5c]	9666	1			T56	7		T59	3		T42	1
valid_sources[0x5d]	11542	1			T27	1		T56	5		T58	1
valid_sources[0x5e]	9771	1			T27	3		T56	1		T59	3
valid_sources[0x5f]	9988	1			T27	2		T59	3		T122	2
valid_sources[0x60]	9709	1			T27	1		T57	2		T58	1
valid_sources[0x61]	10056	1			T27	5		T56	5		T74	1
valid_sources[0x62]	10011	1			T27	1		T58	1		T59	2
valid_sources[0x63]	9270	1			T27	4		T56	3		T58	1
valid_sources[0x64]	9489	1			T29	1		T56	5		T59	2
valid_sources[0x65]	9626	1			T27	3		T56	1		T59	2
valid_sources[0x66]	10750	1			T27	1		T56	2		T58	1
valid_sources[0x67]	10380	1			T56	2		T58	1		T59	4
valid_sources[0x68]	10484	1			T27	2		T56	2		T59	5
valid_sources[0x69]	10686	1			T27	1		T56	2		T58	1
valid_sources[0x6a]	9924	1			T29	1		T56	4		T58	2
valid_sources[0x6b]	9429	1			T27	3		T56	1		T59	1
valid_sources[0x6c]	9932	1			T27	3		T56	2		T58	1
valid_sources[0x6d]	10590	1			T27	2		T58	1		T59	5
valid_sources[0x6e]	10104	1			T27	4		T56	2		T57	1
valid_sources[0x6f]	9594	1			T27	1		T56	3		T122	1
valid_sources[0x70]	9667	1			T56	3		T58	1		T59	3
valid_sources[0x71]	9206	1			T57	1		T61	1		T122	1
valid_sources[0x72]	9273	1			T63	4		T122	1		T123	1
valid_sources[0x73]	9694	1			T29	1		T56	2		T58	1
valid_sources[0x74]	11665	1			T27	2		T56	2		T57	1
valid_sources[0x75]	10881	1			T27	1		T35	1		T56	1
valid_sources[0x76]	10256	1			T27	4		T29	1		T57	1
valid_sources[0x77]	10010	1			T56	4		T59	2		T62	4
valid_sources[0x78]	11009	1			T27	1		T57	2		T59	5
valid_sources[0x79]	9745	1			T57	1		T59	3		T122	3
valid_sources[0x7a]	9294	1			T27	1		T59	4		T62	10
valid_sources[0x7b]	9868	1			T27	2		T29	1		T56	1
valid_sources[0x7c]	10973	1			T27	1		T56	4		T57	1
valid_sources[0x7d]	10652	1			T27	3		T59	1		T62	2
valid_sources[0x7e]	11128	1			T59	2		T60	1		T63	1
valid_sources[0x7f]	9503	1			T59	4		T122	2		T123	6
valid_sources[0x80]	9045	1			T59	4		T113	1		T122	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

530490

1

T27

55

T29

40

T33

2

values[0x0]

all_enables

biggest_size

787598

1

T27

112

T56

98

T57

19

values[0x1]

all_enables

biggest_size

785980

1

T27

118

T56

126

T57

14