Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5793290

1

T20

10

T27

440

T33

18

full_word

2517064

1

T27

307

T29

40

T33

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8310034	1			T27	747		T29	40		T35	20
auto[TlIntgErrCmd]	105	1			T20	2		T33	5		T34	7
auto[TlIntgErrData]	114	1			T20	5		T33	7		T34	8
auto[TlIntgErrBoth]	101	1			T20	3		T33	8		T34	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003146

1

T20

7

T27

64

T29

40

auto[1]

7307208

1

T20

3

T27

683

T33

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	422349	1			T27	9		T56	17		T57	14
auto[TlIntgErrNone]	partial	auto[1]	5370656	1			T27	431		T56	899		T57	113
auto[TlIntgErrNone]	full_word	auto[0]	580650	1			T27	55		T29	40		T35	20
auto[TlIntgErrNone]	full_word	auto[1]	1936379	1			T27	252		T56	272		T57	41
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T20	1		T33	2		T34	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T20	1		T33	3		T34	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T114	1		T115	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T34	1		T113	1		T112	2
auto[TlIntgErrData]	partial	auto[0]	53	1			T20	3		T33	3		T34	2
auto[TlIntgErrData]	partial	auto[1]	52	1			T20	2		T33	2		T34	6
auto[TlIntgErrData]	full_word	auto[0]	4	1			T33	2		T111	1		T117	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T64	1		T113	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T20	3		T33	2		T34	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T33	6		T34	1		T61	6
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T64	1		T111	1		T117	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T113	1		T117	1		T114	1