Group : dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
83.33 83.33 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_mubi4_cov_of_tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_rom_select_bus_o_cov_if 83.33 1 100 1 64 64




Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_rom_select_bus_o_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_rom_select_bus_o_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 1 5 83.33


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_rom_select_bus_o_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 1 5 83.33 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 1 5 83.33


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[1] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 102 1 T8 1 T10 3 T19 1
others[2] 12 1 T36 1 T37 3 T38 4
others[3] 17 1 T36 3 T37 3 T38 3
false 4295 1 T20 21 T27 1 T28 1
true 1855 1 T20 1 T27 1 T28 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%