Module Definition
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Module : prim_secded_inv_64_57_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_chk 100.00 100.00
tb.dut.u_reg_regs.u_chk.u_chk 100.00 100.00



Module Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_cmd_intg_check.u_cmd_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 232 232 100.00
Total Bits 0->1 116 116 100.00
Total Bits 1->0 116 116 100.00

Ports 4 4 100.00
Port Bits 232 232 100.00
Port Bits 0->1 116 116 100.00
Port Bits 1->0 116 116 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes T20,T27,*T29 Yes T20,T27,T29 INPUT
data_i[56:43] Unreachable Unreachable Unreachable INPUT
data_i[63:57] Yes Yes T20,T27,T28 Yes T20,T27,T28 INPUT
data_o[56:0] Yes Yes T20,T27,T29 Yes T20,T27,T29 OUTPUT
syndrome_o[6:0] Yes Yes T20,T33,T34 Yes T20,T31,T32 OUTPUT
err_o[1:0] Yes Yes T20,T31,T32 Yes T20,T33,T34 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 232 232 100.00
Total Bits 0->1 116 116 100.00
Total Bits 1->0 116 116 100.00

Ports 4 4 100.00
Port Bits 232 232 100.00
Port Bits 0->1 116 116 100.00
Port Bits 1->0 116 116 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes T20,T27,*T33 Yes T20,T27,T33 INPUT
data_i[56:43] Unreachable Unreachable Unreachable INPUT
data_i[63:57] Yes Yes T20,T27,T29 Yes T20,T27,T29 INPUT
data_o[56:0] Yes Yes T20,T27,T33 Yes T20,T27,T33 OUTPUT
syndrome_o[6:0] Yes Yes T20,T33,T34 Yes T20,T31,T33 OUTPUT
err_o[1:0] Yes Yes T20,T31,T33 Yes T20,T33,T34 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 232 232 100.00
Total Bits 0->1 116 116 100.00
Total Bits 1->0 116 116 100.00

Ports 4 4 100.00
Port Bits 232 232 100.00
Port Bits 0->1 116 116 100.00
Port Bits 1->0 116 116 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T20,T27,*T29 Yes T20,T27,T29 INPUT
data_i[56:43] Unreachable Unreachable Unreachable INPUT
data_i[63:57] Yes Yes T20,T27,T28 Yes T20,T27,T28 INPUT
data_o[56:0] Yes Yes T20,T27,T29 Yes T20,T27,T29 OUTPUT
syndrome_o[6:0] Yes Yes T20,T33,T34 Yes T20,T32,T33 OUTPUT
err_o[1:0] Yes Yes T20,T32,T33 Yes T20,T33,T34 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%