Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 180601 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1883020 1 T24 245 T25 119 T26 30



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 513920 1 T24 53 T25 20 T26 4
values[0x0] 718130 1 T24 112 T25 46 T26 19
values[0x1] 831571 1 T24 118 T25 53 T26 14



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 80316 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1983305 1 T24 266 T25 119 T26 30



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 8232 1 T24 2 T28 1 T29 4
valid_sources[0x01] 8148 1 T25 1 T28 1 T45 5
valid_sources[0x02] 7903 1 T24 3 T29 1 T65 1
valid_sources[0x03] 8750 1 T65 1 T67 4 T72 4
valid_sources[0x04] 8340 1 T29 3 T66 2 T67 1
valid_sources[0x05] 8336 1 T24 2 T28 2 T45 1
valid_sources[0x06] 8032 1 T24 1 T27 1 T29 1
valid_sources[0x07] 7943 1 T67 1 T49 10 T72 4
valid_sources[0x08] 8007 1 T24 1 T29 1 T45 3
valid_sources[0x09] 8485 1 T24 1 T29 2 T45 2
valid_sources[0x0a] 7843 1 T24 3 T29 1 T65 1
valid_sources[0x0b] 8006 1 T28 2 T45 1 T65 1
valid_sources[0x0c] 8747 1 T24 1 T27 1 T29 1
valid_sources[0x0d] 7623 1 T29 1 T30 8 T115 1
valid_sources[0x0e] 8578 1 T24 2 T28 2 T29 1
valid_sources[0x0f] 8862 1 T28 1 T70 2 T75 3
valid_sources[0x10] 7493 1 T29 1 T45 3 T84 1
valid_sources[0x11] 8250 1 T24 9 T28 1 T29 2
valid_sources[0x12] 7845 1 T27 4 T29 2 T65 2
valid_sources[0x13] 7504 1 T28 3 T29 2 T45 1
valid_sources[0x14] 8425 1 T24 1 T27 11 T45 1
valid_sources[0x15] 7338 1 T45 1 T67 2 T71 9
valid_sources[0x16] 7886 1 T24 2 T29 1 T30 1
valid_sources[0x17] 8400 1 T28 1 T29 2 T45 1
valid_sources[0x18] 7815 1 T24 1 T28 5 T45 2
valid_sources[0x19] 8022 1 T27 2 T45 2 T51 1
valid_sources[0x1a] 8537 1 T24 2 T84 1 T86 1
valid_sources[0x1b] 7780 1 T24 3 T27 3 T110 2
valid_sources[0x1c] 8061 1 T24 4 T28 1 T45 2
valid_sources[0x1d] 7512 1 T27 1 T29 1 T45 1
valid_sources[0x1e] 7460 1 T24 4 T27 2 T45 1
valid_sources[0x1f] 7680 1 T24 5 T28 1 T29 1
valid_sources[0x20] 7477 1 T28 2 T45 2 T86 6
valid_sources[0x21] 7730 1 T28 1 T45 1 T75 1
valid_sources[0x22] 7694 1 T32 1 T45 1 T51 1
valid_sources[0x23] 7941 1 T28 1 T45 1 T86 1
valid_sources[0x24] 7454 1 T24 2 T28 6 T29 2
valid_sources[0x25] 7823 1 T24 1 T28 2 T29 2
valid_sources[0x26] 8294 1 T28 4 T29 1 T45 3
valid_sources[0x27] 8176 1 T24 2 T29 3 T45 1
valid_sources[0x28] 8002 1 T28 2 T29 1 T45 3
valid_sources[0x29] 8924 1 T24 1 T27 2 T29 1
valid_sources[0x2a] 8220 1 T27 2 T46 11 T65 5
valid_sources[0x2b] 8495 1 T31 3 T45 1 T86 1
valid_sources[0x2c] 8534 1 T24 6 T27 1 T30 2
valid_sources[0x2d] 9031 1 T51 1 T72 1 T70 5
valid_sources[0x2e] 8209 1 T30 1 T33 17 T45 2
valid_sources[0x2f] 8588 1 T28 6 T45 1 T87 11
valid_sources[0x30] 7916 1 T25 9 T27 5 T29 3
valid_sources[0x31] 8131 1 T31 1 T45 1 T65 2
valid_sources[0x32] 8173 1 T24 1 T29 5 T33 12
valid_sources[0x33] 7512 1 T27 1 T28 1 T30 3
valid_sources[0x34] 8296 1 T24 1 T27 1 T48 2
valid_sources[0x35] 8050 1 T28 1 T45 1 T65 3
valid_sources[0x36] 8942 1 T27 1 T29 1 T72 1
valid_sources[0x37] 8761 1 T24 1 T28 4 T45 2
valid_sources[0x38] 8416 1 T28 1 T29 1 T45 2
valid_sources[0x39] 8572 1 T24 7 T45 2 T74 1
valid_sources[0x3a] 8831 1 T24 6 T29 1 T45 1
valid_sources[0x3b] 8497 1 T29 2 T45 1 T65 2
valid_sources[0x3c] 7784 1 T29 1 T45 1 T48 4
valid_sources[0x3d] 8148 1 T25 1 T29 1 T30 2
valid_sources[0x3e] 7421 1 T24 1 T28 1 T29 1
valid_sources[0x3f] 8047 1 T28 5 T29 1 T45 2
valid_sources[0x40] 8116 1 T24 1 T45 2 T86 2
valid_sources[0x41] 7383 1 T24 1 T48 2 T86 3
valid_sources[0x42] 8167 1 T24 4 T25 13 T29 2
valid_sources[0x43] 8086 1 T25 8 T30 1 T31 4
valid_sources[0x44] 10028 1 T45 2 T87 4 T66 1
valid_sources[0x45] 7735 1 T24 2 T25 2 T29 1
valid_sources[0x46] 8152 1 T25 5 T29 1 T72 1
valid_sources[0x47] 7508 1 T33 5 T45 2 T67 4
valid_sources[0x48] 8804 1 T24 2 T28 1 T67 1
valid_sources[0x49] 7829 1 T24 2 T27 5 T45 1
valid_sources[0x4a] 7659 1 T24 2 T29 1 T67 2
valid_sources[0x4b] 7522 1 T27 1 T28 2 T29 2
valid_sources[0x4c] 7657 1 T29 3 T65 1 T67 5
valid_sources[0x4d] 7712 1 T24 1 T25 1 T27 2
valid_sources[0x4e] 8760 1 T24 2 T29 1 T45 1
valid_sources[0x4f] 7299 1 T24 2 T30 1 T45 2
valid_sources[0x50] 7817 1 T28 2 T45 1 T46 1
valid_sources[0x51] 8924 1 T67 2 T77 1 T131 2
valid_sources[0x52] 8151 1 T26 11 T29 1 T86 1
valid_sources[0x53] 7417 1 T24 4 T115 1 T51 1
valid_sources[0x54] 7917 1 T28 4 T29 1 T45 1
valid_sources[0x55] 8541 1 T27 2 T45 1 T86 4
valid_sources[0x56] 7611 1 T27 2 T29 1 T45 1
valid_sources[0x57] 8156 1 T27 4 T29 3 T31 1
valid_sources[0x58] 7773 1 T27 3 T30 1 T45 1
valid_sources[0x59] 8196 1 T24 1 T45 2 T65 3
valid_sources[0x5a] 7585 1 T27 7 T45 3 T86 1
valid_sources[0x5b] 7287 1 T25 3 T28 1 T29 3
valid_sources[0x5c] 7753 1 T24 3 T86 3 T51 1
valid_sources[0x5d] 8812 1 T24 1 T25 1 T67 3
valid_sources[0x5e] 7561 1 T25 1 T27 2 T30 2
valid_sources[0x5f] 8314 1 T45 2 T84 1 T72 1
valid_sources[0x60] 8312 1 T24 1 T51 1 T72 2
valid_sources[0x61] 8031 1 T24 1 T28 1 T29 1
valid_sources[0x62] 8483 1 T24 2 T25 3 T27 1
valid_sources[0x63] 7782 1 T24 1 T27 1 T29 2
valid_sources[0x64] 7741 1 T27 2 T28 1 T29 2
valid_sources[0x65] 8273 1 T24 2 T45 1 T87 5
valid_sources[0x66] 8607 1 T24 1 T28 4 T29 2
valid_sources[0x67] 8655 1 T24 1 T27 2 T86 1
valid_sources[0x68] 8255 1 T25 2 T29 2 T45 1
valid_sources[0x69] 8161 1 T26 6 T27 3 T29 1
valid_sources[0x6a] 7547 1 T29 1 T45 2 T86 2
valid_sources[0x6b] 7882 1 T24 1 T28 3 T45 1
valid_sources[0x6c] 7789 1 T24 2 T28 2 T29 1
valid_sources[0x6d] 7804 1 T25 3 T27 6 T28 5
valid_sources[0x6e] 8971 1 T24 2 T25 1 T45 2
valid_sources[0x6f] 8061 1 T27 1 T45 1 T86 1
valid_sources[0x70] 7758 1 T27 2 T29 1 T45 3
valid_sources[0x71] 7391 1 T24 3 T31 3 T45 1
valid_sources[0x72] 7555 1 T24 3 T67 1 T70 3
valid_sources[0x73] 8393 1 T24 1 T31 1 T67 1
valid_sources[0x74] 7361 1 T24 1 T27 3 T28 3
valid_sources[0x75] 7011 1 T25 2 T28 3 T45 2
valid_sources[0x76] 7963 1 T28 2 T29 3 T45 2
valid_sources[0x77] 7699 1 T24 2 T26 7 T27 3
valid_sources[0x78] 8516 1 T24 4 T29 1 T45 2
valid_sources[0x79] 8671 1 T24 1 T46 7 T86 2
valid_sources[0x7a] 8115 1 T27 5 T84 1 T86 2
valid_sources[0x7b] 7913 1 T24 1 T28 1 T29 2
valid_sources[0x7c] 8075 1 T24 1 T25 1 T45 2
valid_sources[0x7d] 7790 1 T25 3 T45 2 T115 1
valid_sources[0x7e] 8185 1 T24 1 T29 2 T31 1
valid_sources[0x7f] 7598 1 T25 3 T27 2 T45 1
valid_sources[0x80] 8064 1 T29 1 T46 9 T115 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 475436 1 T24 50 T25 20 T27 18
values[0x0] all_enables biggest_size 703795 1 T24 105 T25 46 T26 17
values[0x1] all_enables biggest_size 703789 1 T24 90 T25 53 T26 13


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 422527 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1869805 1 T24 216 T29 20 T45 81



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 514367 1 T24 50 T29 20 T45 14
values[0x0] 735208 1 T24 93 T45 35 T46 106
values[0x1] 1042757 1 T24 152 T45 58 T46 135



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 160704 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2131628 1 T24 268 T29 20 T45 97



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 8956 1 T46 2 T50 1 T72 2
valid_sources[0x01] 9609 1 T45 1 T46 1 T72 1
valid_sources[0x02] 8523 1 T46 3 T66 1 T72 3
valid_sources[0x03] 8557 1 T72 1 T73 1 T76 7
valid_sources[0x04] 8544 1 T46 2 T72 1 T75 1
valid_sources[0x05] 8056 1 T45 1 T46 2 T72 1
valid_sources[0x06] 8377 1 T45 1 T74 1 T75 2
valid_sources[0x07] 9401 1 T46 1 T75 2 T73 4
valid_sources[0x08] 7962 1 T46 2 T75 1 T73 4
valid_sources[0x09] 9507 1 T29 1 T46 1 T69 1
valid_sources[0x0a] 9224 1 T46 2 T75 1 T73 2
valid_sources[0x0b] 9929 1 T45 1 T50 1 T72 3
valid_sources[0x0c] 8796 1 T46 1 T75 4 T73 1
valid_sources[0x0d] 9555 1 T45 1 T46 2 T72 2
valid_sources[0x0e] 11256 1 T46 2 T51 3 T72 1
valid_sources[0x0f] 10509 1 T45 1 T46 2 T72 2
valid_sources[0x10] 8824 1 T45 2 T46 2 T72 3
valid_sources[0x11] 9049 1 T72 3 T73 2 T12 304
valid_sources[0x12] 10376 1 T45 1 T50 1 T69 2
valid_sources[0x13] 8868 1 T46 2 T69 1 T72 1
valid_sources[0x14] 8720 1 T72 1 T75 1 T73 6
valid_sources[0x15] 7570 1 T45 1 T46 3 T69 1
valid_sources[0x16] 8684 1 T46 1 T48 1 T75 3
valid_sources[0x17] 10315 1 T45 1 T46 3 T73 2
valid_sources[0x18] 7103 1 T50 1 T72 2 T75 1
valid_sources[0x19] 8443 1 T45 1 T46 3 T66 1
valid_sources[0x1a] 8504 1 T72 1 T75 1 T73 3
valid_sources[0x1b] 10469 1 T46 2 T50 1 T72 4
valid_sources[0x1c] 9910 1 T45 1 T74 2 T72 2
valid_sources[0x1d] 9478 1 T45 1 T46 1 T121 1
valid_sources[0x1e] 8279 1 T45 1 T46 2 T51 1
valid_sources[0x1f] 8897 1 T46 1 T51 1 T66 1
valid_sources[0x20] 7734 1 T45 1 T46 2 T75 1
valid_sources[0x21] 10433 1 T69 1 T72 1 T73 5
valid_sources[0x22] 8138 1 T45 1 T72 1 T73 2
valid_sources[0x23] 10270 1 T46 1 T66 1 T72 1
valid_sources[0x24] 7639 1 T72 1 T75 1 T73 3
valid_sources[0x25] 9245 1 T72 1 T73 6 T132 1
valid_sources[0x26] 8636 1 T65 144 T72 1 T73 3
valid_sources[0x27] 8176 1 T75 1 T73 3 T79 1
valid_sources[0x28] 8092 1 T73 1 T132 1 T133 2
valid_sources[0x29] 9072 1 T29 1 T45 1 T46 1
valid_sources[0x2a] 8374 1 T46 1 T75 1 T85 2
valid_sources[0x2b] 8544 1 T45 1 T46 2 T72 2
valid_sources[0x2c] 9472 1 T50 1 T72 2 T75 2
valid_sources[0x2d] 9406 1 T69 1 T72 1 T75 5
valid_sources[0x2e] 10200 1 T45 1 T46 1 T48 1
valid_sources[0x2f] 9404 1 T72 2 T73 3 T132 1
valid_sources[0x30] 8091 1 T72 2 T75 1 T73 3
valid_sources[0x31] 10029 1 T46 2 T72 3 T75 2
valid_sources[0x32] 9367 1 T72 1 T75 1 T73 4
valid_sources[0x33] 8920 1 T45 1 T46 2 T72 3
valid_sources[0x34] 8419 1 T69 1 T72 5 T73 4
valid_sources[0x35] 9060 1 T46 2 T72 2 T75 1
valid_sources[0x36] 8531 1 T29 1 T72 2 T75 1
valid_sources[0x37] 9024 1 T29 1 T45 1 T46 3
valid_sources[0x38] 8431 1 T45 1 T46 1 T69 1
valid_sources[0x39] 9594 1 T29 1 T48 1 T75 4
valid_sources[0x3a] 8679 1 T45 1 T49 20 T72 2
valid_sources[0x3b] 8646 1 T72 1 T73 2 T79 1
valid_sources[0x3c] 9567 1 T72 1 T73 5 T133 1
valid_sources[0x3d] 8586 1 T45 2 T75 2 T73 1
valid_sources[0x3e] 9440 1 T29 1 T46 2 T74 3
valid_sources[0x3f] 9666 1 T72 4 T73 1 T76 3
valid_sources[0x40] 10499 1 T29 1 T46 2 T72 2
valid_sources[0x41] 8519 1 T72 2 T75 3 T73 2
valid_sources[0x42] 8889 1 T46 1 T74 1 T75 2
valid_sources[0x43] 8796 1 T45 1 T46 2 T69 1
valid_sources[0x44] 9124 1 T45 1 T51 1 T72 1
valid_sources[0x45] 9621 1 T45 1 T72 3 T73 4
valid_sources[0x46] 7950 1 T45 1 T46 1 T69 1
valid_sources[0x47] 8548 1 T45 1 T69 3 T72 1
valid_sources[0x48] 8415 1 T45 1 T46 1 T69 2
valid_sources[0x49] 9145 1 T46 1 T69 1 T72 1
valid_sources[0x4a] 8099 1 T29 2 T45 1 T72 3
valid_sources[0x4b] 9264 1 T45 1 T46 1 T72 6
valid_sources[0x4c] 8369 1 T46 1 T48 1 T72 4
valid_sources[0x4d] 8846 1 T46 1 T48 1 T72 3
valid_sources[0x4e] 9223 1 T50 2 T69 3 T72 1
valid_sources[0x4f] 10080 1 T46 3 T69 2 T72 3
valid_sources[0x50] 9036 1 T29 1 T46 2 T69 1
valid_sources[0x51] 8425 1 T45 1 T75 3 T73 1
valid_sources[0x52] 8208 1 T45 1 T46 1 T50 1
valid_sources[0x53] 8639 1 T45 1 T48 1 T72 1
valid_sources[0x54] 8022 1 T45 1 T46 6 T75 1
valid_sources[0x55] 10168 1 T46 2 T74 1 T75 6
valid_sources[0x56] 9543 1 T69 1 T72 1 T73 6
valid_sources[0x57] 9849 1 T46 4 T48 1 T51 4
valid_sources[0x58] 8430 1 T45 1 T46 1 T69 1
valid_sources[0x59] 8427 1 T45 1 T46 1 T72 3
valid_sources[0x5a] 7840 1 T29 1 T46 1 T69 1
valid_sources[0x5b] 8237 1 T46 2 T72 2 T73 1
valid_sources[0x5c] 8792 1 T29 1 T74 2 T75 5
valid_sources[0x5d] 8450 1 T69 1 T75 1 T73 1
valid_sources[0x5e] 8963 1 T72 1 T75 3 T73 2
valid_sources[0x5f] 8171 1 T46 2 T69 1 T72 1
valid_sources[0x60] 9321 1 T45 3 T46 7 T72 3
valid_sources[0x61] 8907 1 T46 1 T69 1 T72 1
valid_sources[0x62] 10269 1 T69 2 T72 2 T73 2
valid_sources[0x63] 9616 1 T46 2 T72 1 T75 1
valid_sources[0x64] 11333 1 T29 1 T45 1 T46 1
valid_sources[0x65] 8762 1 T29 1 T46 1 T72 1
valid_sources[0x66] 10530 1 T46 4 T51 1 T72 2
valid_sources[0x67] 8698 1 T45 1 T46 3 T69 1
valid_sources[0x68] 10508 1 T46 1 T50 1 T72 1
valid_sources[0x69] 8362 1 T45 2 T46 2 T50 1
valid_sources[0x6a] 8493 1 T73 3 T134 2 T130 2
valid_sources[0x6b] 10447 1 T45 1 T46 3 T75 2
valid_sources[0x6c] 7912 1 T45 1 T46 1 T72 1
valid_sources[0x6d] 9537 1 T45 1 T75 1 T73 5
valid_sources[0x6e] 8322 1 T46 1 T72 1 T75 1
valid_sources[0x6f] 8412 1 T72 2 T75 1 T73 2
valid_sources[0x70] 9077 1 T46 2 T50 1 T72 2
valid_sources[0x71] 8002 1 T46 2 T66 1 T69 1
valid_sources[0x72] 9622 1 T45 2 T46 2 T69 1
valid_sources[0x73] 10639 1 T72 3 T73 3 T85 3
valid_sources[0x74] 11110 1 T45 1 T46 1 T72 2
valid_sources[0x75] 8672 1 T45 1 T46 1 T72 1
valid_sources[0x76] 7954 1 T46 2 T75 2 T73 2
valid_sources[0x77] 9334 1 T46 1 T75 1 T73 3
valid_sources[0x78] 9144 1 T46 4 T50 1 T73 1
valid_sources[0x79] 8223 1 T46 1 T73 8 T134 2
valid_sources[0x7a] 8968 1 T45 1 T46 4 T50 1
valid_sources[0x7b] 9054 1 T46 1 T50 1 T73 1
valid_sources[0x7c] 9245 1 T45 1 T46 1 T72 1
valid_sources[0x7d] 9100 1 T29 1 T72 3 T75 2
valid_sources[0x7e] 10839 1 T29 1 T72 1 T73 3
valid_sources[0x7f] 8802 1 T46 1 T74 2 T72 1
valid_sources[0x80] 8953 1 T46 1 T73 3 T121 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 470549 1 T24 50 T29 20 T45 14
values[0x0] all_enables biggest_size 699513 1 T24 87 T45 33 T46 102
values[0x1] all_enables biggest_size 699743 1 T24 79 T45 34 T46 98

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%