Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5181534

1

T24

1115

T45

477

T46

615

full_word

2240381

1

T24

288

T29

20

T45

123

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7421625	1			T24	1403		T29	20		T45	600
auto[TlIntgErrCmd]	107	1			T67	7		T70	10		T71	7
auto[TlIntgErrData]	97	1			T67	1		T70	7		T71	6
auto[TlIntgErrBoth]	86	1			T67	2		T70	3		T71	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

893102

1

T24

153

T29

20

T45

68

auto[1]

6528813

1

T24

1250

T45

532

T46

789

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	377062	1			T24	92		T45	46		T46	64
auto[TlIntgErrNone]	partial	auto[1]	4804202	1			T24	1023		T45	431		T46	551
auto[TlIntgErrNone]	full_word	auto[0]	515914	1			T24	61		T29	20		T45	22
auto[TlIntgErrNone]	full_word	auto[1]	1724447	1			T24	227		T45	101		T46	238
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T67	2		T70	2		T71	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T67	5		T70	8		T71	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T71	1		T119	1		T120	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T67	1		T70	3		T71	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T70	3		T71	3		T121	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T70	1		T71	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T122	1		T123	1		T124	2
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T70	2		T71	3		T125	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T67	2		T70	1		T71	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T71	1		T126	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T120	1		T127	1		T128	1