Module Definition
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Module Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.85 100.00 65.38 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.96 100.00 65.38 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.22 96.92 83.05 88.89 100.00 u_tl_adapter_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00



Module Instance : tb.dut.u_tl_adapter_rom.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 80.77 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 80.77 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.22 96.92 83.05 88.89 100.00 u_tl_adapter_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00



Module Instance : tb.dut.u_tl_adapter_rom.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.32 100.00 85.29 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.22 100.00 81.08 90.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.22 96.92 83.05 88.89 100.00 u_tl_adapter_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 74.44 100.00 33.33 90.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
95.19 100.00
tb.dut.u_tl_adapter_rom.u_reqfifo

SCORELINE
88.85 100.00
tb.dut.u_tl_adapter_rom.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
96.32 100.00
tb.dut.u_tl_adapter_rom.u_rspfifo

Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1


Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
95.19 80.77
tb.dut.u_tl_adapter_rom.u_reqfifo

TotalCoveredPercent
Conditions262180.77
Logical262180.77
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T16,T20

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT3,T4,T5

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T10,T16
110Not Covered
111CoveredT3,T4,T5

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT10,T16,T20
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T16,T20

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
96.32 85.29
tb.dut.u_tl_adapter_rom.u_rspfifo

TotalCoveredPercent
Conditions342985.29
Logical342985.29
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T16,T20

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT3,T10,T16
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT3,T10,T16
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT3,T4,T5

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T10,T16
110Not Covered
111CoveredT3,T4,T5

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT10,T16,T20
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T16,T20

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT10,T16,T20
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT3,T10,T16
10CoveredT3,T4,T5
11CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
88.85 65.38
tb.dut.u_tl_adapter_rom.u_sramreqfifo

TotalCoveredPercent
Conditions261765.38
Logical261765.38
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT3,T4,T5

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT3,T4,T5

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
95.19 100.00
tb.dut.u_tl_adapter_rom.u_reqfifo

SCOREBRANCH
88.85 90.00
tb.dut.u_tl_adapter_rom.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 88 3 3 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T10,T16,T20
0 1 Covered T1,T2,T3
0 0 Covered T3,T4,T5


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
96.32 100.00
tb.dut.u_tl_adapter_rom.u_rspfifo

Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 88 3 3 100.00
TERNARY 172 2 2 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T10,T16,T20
0 1 Covered T1,T2,T3
0 0 Covered T3,T10,T16


LineNo. Expression -1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 713736288 16152408 0 0
DepthKnown_A 713736288 713190357 0 0
RvalidKnown_A 713736288 713190357 0 0
WreadyKnown_A 713736288 713190357 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 713736288 16152408 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 713736288 16152408 0 0
T3 342624 104 0 0
T4 103995 999 0 0
T5 741552 174 0 0
T6 296295 0 0 0
T7 1237950 0 0 0
T8 609369 18 0 0
T9 24996 0 0 0
T10 470091 507 0 0
T11 587562 0 0 0
T12 0 169672 0 0
T13 0 339 0 0
T16 0 5066 0 0
T21 0 213 0 0
T22 0 27 0 0
T23 416304 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 713736288 713190357 0 0
T1 617934 617370 0 0
T2 1004526 1004193 0 0
T3 342624 342165 0 0
T4 103995 103761 0 0
T5 741552 741069 0 0
T6 296295 296142 0 0
T7 1237950 1237527 0 0
T8 609369 608706 0 0
T9 24996 24783 0 0
T10 470091 469620 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 713736288 713190357 0 0
T1 617934 617370 0 0
T2 1004526 1004193 0 0
T3 342624 342165 0 0
T4 103995 103761 0 0
T5 741552 741069 0 0
T6 296295 296142 0 0
T7 1237950 1237527 0 0
T8 609369 608706 0 0
T9 24996 24783 0 0
T10 470091 469620 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 713736288 713190357 0 0
T1 617934 617370 0 0
T2 1004526 1004193 0 0
T3 342624 342165 0 0
T4 103995 103761 0 0
T5 741552 741069 0 0
T6 296295 296142 0 0
T7 1237950 1237527 0 0
T8 609369 608706 0 0
T9 24996 24783 0 0
T10 470091 469620 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 713736288 16152408 0 0
T3 342624 104 0 0
T4 103995 999 0 0
T5 741552 174 0 0
T6 296295 0 0 0
T7 1237950 0 0 0
T8 609369 18 0 0
T9 24996 0 0 0
T10 470091 507 0 0
T11 587562 0 0 0
T12 0 169672 0 0
T13 0 339 0 0
T16 0 5066 0 0
T21 0 213 0 0
T22 0 27 0 0
T23 416304 0 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
TotalCoveredPercent
Conditions261765.38
Logical261765.38
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT3,T4,T5

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT3,T4,T5

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T3,T4,T5


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 237912096 48433 0 0
DepthKnown_A 237912096 237730119 0 0
RvalidKnown_A 237912096 237730119 0 0
WreadyKnown_A 237912096 237730119 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 237912096 48433 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 48433 0 0
T3 114208 12 0 0
T4 34665 333 0 0
T5 247184 58 0 0
T6 98765 0 0 0
T7 412650 0 0 0
T8 203123 6 0 0
T9 8332 0 0 0
T10 156697 63 0 0
T11 195854 0 0 0
T12 0 376 0 0
T13 0 113 0 0
T16 0 408 0 0
T21 0 71 0 0
T22 0 9 0 0
T23 138768 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 237730119 0 0
T1 205978 205790 0 0
T2 334842 334731 0 0
T3 114208 114055 0 0
T4 34665 34587 0 0
T5 247184 247023 0 0
T6 98765 98714 0 0
T7 412650 412509 0 0
T8 203123 202902 0 0
T9 8332 8261 0 0
T10 156697 156540 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 237730119 0 0
T1 205978 205790 0 0
T2 334842 334731 0 0
T3 114208 114055 0 0
T4 34665 34587 0 0
T5 247184 247023 0 0
T6 98765 98714 0 0
T7 412650 412509 0 0
T8 203123 202902 0 0
T9 8332 8261 0 0
T10 156697 156540 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 237730119 0 0
T1 205978 205790 0 0
T2 334842 334731 0 0
T3 114208 114055 0 0
T4 34665 34587 0 0
T5 247184 247023 0 0
T6 98765 98714 0 0
T7 412650 412509 0 0
T8 203123 202902 0 0
T9 8332 8261 0 0
T10 156697 156540 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 48433 0 0
T3 114208 12 0 0
T4 34665 333 0 0
T5 247184 58 0 0
T6 98765 0 0 0
T7 412650 0 0 0
T8 203123 6 0 0
T9 8332 0 0 0
T10 156697 63 0 0
T11 195854 0 0 0
T12 0 376 0 0
T13 0 113 0 0
T16 0 408 0 0
T21 0 71 0 0
T22 0 9 0 0
T23 138768 0 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
TotalCoveredPercent
Conditions262180.77
Logical262180.77
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T16,T20

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT3,T4,T5

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T10,T16
110Not Covered
111CoveredT3,T4,T5

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT10,T16,T20
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T16,T20

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 88 3 3 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T10,T16,T20
0 1 Covered T1,T2,T3
0 0 Covered T3,T4,T5


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 237912096 16005447 0 0
DepthKnown_A 237912096 237730119 0 0
RvalidKnown_A 237912096 237730119 0 0
WreadyKnown_A 237912096 237730119 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 237912096 16005447 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 16005447 0 0
T3 114208 46 0 0
T4 34665 333 0 0
T5 247184 58 0 0
T6 98765 0 0 0
T7 412650 0 0 0
T8 203123 6 0 0
T9 8332 0 0 0
T10 156697 222 0 0
T11 195854 0 0 0
T12 0 168920 0 0
T13 0 113 0 0
T16 0 2329 0 0
T21 0 71 0 0
T22 0 9 0 0
T23 138768 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 237730119 0 0
T1 205978 205790 0 0
T2 334842 334731 0 0
T3 114208 114055 0 0
T4 34665 34587 0 0
T5 247184 247023 0 0
T6 98765 98714 0 0
T7 412650 412509 0 0
T8 203123 202902 0 0
T9 8332 8261 0 0
T10 156697 156540 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 237730119 0 0
T1 205978 205790 0 0
T2 334842 334731 0 0
T3 114208 114055 0 0
T4 34665 34587 0 0
T5 247184 247023 0 0
T6 98765 98714 0 0
T7 412650 412509 0 0
T8 203123 202902 0 0
T9 8332 8261 0 0
T10 156697 156540 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 237730119 0 0
T1 205978 205790 0 0
T2 334842 334731 0 0
T3 114208 114055 0 0
T4 34665 34587 0 0
T5 247184 247023 0 0
T6 98765 98714 0 0
T7 412650 412509 0 0
T8 203123 202902 0 0
T9 8332 8261 0 0
T10 156697 156540 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 16005447 0 0
T3 114208 46 0 0
T4 34665 333 0 0
T5 247184 58 0 0
T6 98765 0 0 0
T7 412650 0 0 0
T8 203123 6 0 0
T9 8332 0 0 0
T10 156697 222 0 0
T11 195854 0 0 0
T12 0 168920 0 0
T13 0 113 0 0
T16 0 2329 0 0
T21 0 71 0 0
T22 0 9 0 0
T23 138768 0 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
TotalCoveredPercent
Conditions342985.29
Logical342985.29
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T16,T20

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT3,T10,T16
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT3,T10,T16
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT3,T4,T5

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T10,T16
110Not Covered
111CoveredT3,T4,T5

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT10,T16,T20
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T16,T20

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT10,T16,T20
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT3,T10,T16
10CoveredT3,T4,T5
11CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T4,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 88 3 3 100.00
TERNARY 172 2 2 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T10,T16,T20
0 1 Covered T1,T2,T3
0 0 Covered T3,T10,T16


LineNo. Expression -1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 237912096 98528 0 0
DepthKnown_A 237912096 237730119 0 0
RvalidKnown_A 237912096 237730119 0 0
WreadyKnown_A 237912096 237730119 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 237912096 98528 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 98528 0 0
T3 114208 46 0 0
T4 34665 333 0 0
T5 247184 58 0 0
T6 98765 0 0 0
T7 412650 0 0 0
T8 203123 6 0 0
T9 8332 0 0 0
T10 156697 222 0 0
T11 195854 0 0 0
T12 0 376 0 0
T13 0 113 0 0
T16 0 2329 0 0
T21 0 71 0 0
T22 0 9 0 0
T23 138768 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 237730119 0 0
T1 205978 205790 0 0
T2 334842 334731 0 0
T3 114208 114055 0 0
T4 34665 34587 0 0
T5 247184 247023 0 0
T6 98765 98714 0 0
T7 412650 412509 0 0
T8 203123 202902 0 0
T9 8332 8261 0 0
T10 156697 156540 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 237730119 0 0
T1 205978 205790 0 0
T2 334842 334731 0 0
T3 114208 114055 0 0
T4 34665 34587 0 0
T5 247184 247023 0 0
T6 98765 98714 0 0
T7 412650 412509 0 0
T8 203123 202902 0 0
T9 8332 8261 0 0
T10 156697 156540 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 237730119 0 0
T1 205978 205790 0 0
T2 334842 334731 0 0
T3 114208 114055 0 0
T4 34665 34587 0 0
T5 247184 247023 0 0
T6 98765 98714 0 0
T7 412650 412509 0 0
T8 203123 202902 0 0
T9 8332 8261 0 0
T10 156697 156540 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 237912096 98528 0 0
T3 114208 46 0 0
T4 34665 333 0 0
T5 247184 58 0 0
T6 98765 0 0 0
T7 412650 0 0 0
T8 203123 6 0 0
T9 8332 0 0 0
T10 156697 222 0 0
T11 195854 0 0 0
T12 0 376 0 0
T13 0 113 0 0
T16 0 2329 0 0
T21 0 71 0 0
T22 0 9 0 0
T23 138768 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%