Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	208026	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2124758

1

T28

89

T30

431

T31

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	582021	1			T28	19		T30	103		T31	2
values[0x0]	810597	1			T28	39		T30	172		T31	11
values[0x1]	940166	1			T28	48		T30	190		T31	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	92220	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2240564

1

T28

97

T30

450

T31

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9916	1			T32	1		T34	1		T35	2
valid_sources[0x01]	9216	1			T28	2		T30	6		T32	3
valid_sources[0x02]	9151	1			T35	5		T71	1		T63	1
valid_sources[0x03]	9055	1			T32	1		T35	1		T61	2
valid_sources[0x04]	7850	1			T30	3		T33	23		T35	1
valid_sources[0x05]	8141	1			T30	2		T35	3		T37	1
valid_sources[0x06]	9249	1			T30	1		T32	3		T35	5
valid_sources[0x07]	9482	1			T30	4		T32	3		T35	3
valid_sources[0x08]	9720	1			T32	1		T70	2		T63	2
valid_sources[0x09]	10230	1			T30	3		T35	3		T71	1
valid_sources[0x0a]	9314	1			T35	3		T70	1		T64	5
valid_sources[0x0b]	8812	1			T30	2		T32	1		T35	3
valid_sources[0x0c]	8729	1			T32	3		T35	4		T60	3
valid_sources[0x0d]	9277	1			T30	2		T31	1		T32	1
valid_sources[0x0e]	9843	1			T30	2		T32	1		T35	1
valid_sources[0x0f]	9136	1			T35	2		T37	3		T45	2
valid_sources[0x10]	10142	1			T30	9		T35	2		T63	3
valid_sources[0x11]	8736	1			T35	2		T61	9		T71	1
valid_sources[0x12]	9441	1			T28	5		T32	1		T35	2
valid_sources[0x13]	8383	1			T32	1		T35	6		T71	1
valid_sources[0x14]	8698	1			T35	3		T36	2		T37	2
valid_sources[0x15]	8741	1			T32	1		T35	1		T72	1
valid_sources[0x16]	10007	1			T35	1		T36	3		T60	4
valid_sources[0x17]	8732	1			T30	1		T35	2		T36	3
valid_sources[0x18]	8532	1			T30	5		T35	2		T37	1
valid_sources[0x19]	10064	1			T30	5		T32	1		T35	2
valid_sources[0x1a]	9011	1			T30	1		T32	2		T35	2
valid_sources[0x1b]	9461	1			T31	1		T35	4		T45	4
valid_sources[0x1c]	9279	1			T32	2		T35	1		T61	2
valid_sources[0x1d]	8813	1			T36	1		T71	3		T63	1
valid_sources[0x1e]	9728	1			T30	4		T31	1		T32	1
valid_sources[0x1f]	8877	1			T35	1		T60	5		T61	11
valid_sources[0x20]	9113	1			T31	1		T32	5		T35	3
valid_sources[0x21]	8908	1			T30	9		T32	4		T35	1
valid_sources[0x22]	8465	1			T32	1		T36	2		T63	1
valid_sources[0x23]	8823	1			T36	4		T63	1		T66	1
valid_sources[0x24]	9227	1			T32	2		T35	1		T70	3
valid_sources[0x25]	9168	1			T30	3		T32	1		T46	20
valid_sources[0x26]	9603	1			T35	3		T37	3		T70	2
valid_sources[0x27]	8914	1			T30	1		T35	6		T36	32
valid_sources[0x28]	8537	1			T35	5		T70	1		T71	2
valid_sources[0x29]	9680	1			T30	7		T35	6		T70	1
valid_sources[0x2a]	9486	1			T30	1		T32	1		T35	1
valid_sources[0x2b]	9168	1			T30	12		T32	2		T37	1
valid_sources[0x2c]	8144	1			T32	1		T35	1		T70	1
valid_sources[0x2d]	9848	1			T30	10		T35	3		T45	1
valid_sources[0x2e]	9655	1			T37	1		T45	3		T63	3
valid_sources[0x2f]	8471	1			T32	1		T37	1		T60	3
valid_sources[0x30]	8553	1			T30	1		T32	1		T35	3
valid_sources[0x31]	9754	1			T35	1		T61	6		T63	1
valid_sources[0x32]	8923	1			T32	1		T35	4		T71	1
valid_sources[0x33]	9186	1			T30	1		T32	2		T35	2
valid_sources[0x34]	8521	1			T30	10		T32	1		T35	2
valid_sources[0x35]	9044	1			T35	3		T60	1		T61	1
valid_sources[0x36]	8430	1			T30	2		T32	1		T35	2
valid_sources[0x37]	9306	1			T28	3		T30	4		T35	2
valid_sources[0x38]	8104	1			T30	1		T35	1		T72	1
valid_sources[0x39]	9519	1			T30	7		T32	2		T71	1
valid_sources[0x3a]	9111	1			T30	12		T35	2		T70	2
valid_sources[0x3b]	9573	1			T32	4		T35	1		T36	2
valid_sources[0x3c]	8659	1			T30	2		T32	1		T35	1
valid_sources[0x3d]	9836	1			T30	2		T32	2		T35	7
valid_sources[0x3e]	8470	1			T30	3		T32	1		T35	2
valid_sources[0x3f]	8268	1			T32	2		T35	6		T60	7
valid_sources[0x40]	9381	1			T35	3		T37	1		T61	17
valid_sources[0x41]	8781	1			T35	7		T37	5		T70	2
valid_sources[0x42]	8178	1			T32	1		T35	2		T70	1
valid_sources[0x43]	7594	1			T30	8		T32	1		T35	2
valid_sources[0x44]	8412	1			T30	5		T32	1		T35	2
valid_sources[0x45]	9153	1			T28	19		T30	1		T32	3
valid_sources[0x46]	9939	1			T30	2		T34	1		T35	4
valid_sources[0x47]	9385	1			T32	6		T35	4		T71	2
valid_sources[0x48]	8358	1			T30	1		T32	2		T35	1
valid_sources[0x49]	8601	1			T33	28		T35	4		T63	3
valid_sources[0x4a]	8557	1			T32	3		T35	1		T60	4
valid_sources[0x4b]	9267	1			T32	1		T35	2		T71	2
valid_sources[0x4c]	8942	1			T35	3		T37	5		T70	1
valid_sources[0x4d]	8628	1			T32	2		T35	3		T70	2
valid_sources[0x4e]	9480	1			T33	26		T34	3		T35	2
valid_sources[0x4f]	10275	1			T32	1		T35	6		T37	1
valid_sources[0x50]	9361	1			T32	2		T35	2		T70	1
valid_sources[0x51]	8646	1			T32	1		T35	3		T70	1
valid_sources[0x52]	9300	1			T30	9		T32	1		T35	1
valid_sources[0x53]	10190	1			T30	5		T32	4		T35	2
valid_sources[0x54]	8311	1			T32	1		T35	4		T70	1
valid_sources[0x55]	10360	1			T32	3		T35	1		T37	2
valid_sources[0x56]	8192	1			T35	6		T37	1		T72	1
valid_sources[0x57]	8879	1			T30	9		T32	4		T35	2
valid_sources[0x58]	9291	1			T30	2		T32	2		T35	4
valid_sources[0x59]	9684	1			T30	1		T33	11		T61	1
valid_sources[0x5a]	9162	1			T30	2		T32	2		T35	1
valid_sources[0x5b]	8790	1			T28	1		T35	2		T37	1
valid_sources[0x5c]	10903	1			T30	14		T32	1		T34	6
valid_sources[0x5d]	9159	1			T35	3		T72	1		T81	1
valid_sources[0x5e]	10347	1			T35	2		T37	2		T63	3
valid_sources[0x5f]	9406	1			T35	4		T37	2		T45	2
valid_sources[0x60]	8696	1			T30	2		T35	3		T63	3
valid_sources[0x61]	8960	1			T28	1		T35	2		T37	3
valid_sources[0x62]	7630	1			T34	4		T35	4		T70	1
valid_sources[0x63]	9780	1			T32	1		T35	1		T70	1
valid_sources[0x64]	8232	1			T32	1		T35	2		T45	1
valid_sources[0x65]	9175	1			T30	20		T35	2		T36	8
valid_sources[0x66]	9336	1			T30	2		T32	1		T37	8
valid_sources[0x67]	8870	1			T34	2		T35	1		T66	1
valid_sources[0x68]	9480	1			T31	1		T32	1		T35	5
valid_sources[0x69]	8491	1			T28	4		T30	2		T32	1
valid_sources[0x6a]	8470	1			T34	2		T35	5		T37	1
valid_sources[0x6b]	9371	1			T31	1		T32	1		T35	1
valid_sources[0x6c]	9039	1			T28	1		T30	2		T33	10
valid_sources[0x6d]	9637	1			T30	4		T35	6		T63	1
valid_sources[0x6e]	8489	1			T32	1		T35	2		T46	21
valid_sources[0x6f]	9937	1			T72	1		T81	1		T64	4
valid_sources[0x70]	9529	1			T30	4		T32	2		T35	2
valid_sources[0x71]	8925	1			T28	4		T30	3		T32	1
valid_sources[0x72]	9787	1			T30	3		T32	4		T35	2
valid_sources[0x73]	10488	1			T30	4		T32	3		T35	5
valid_sources[0x74]	9895	1			T32	1		T35	2		T37	2
valid_sources[0x75]	8940	1			T35	1		T71	1		T45	1
valid_sources[0x76]	7915	1			T35	2		T63	1		T81	4
valid_sources[0x77]	8959	1			T35	1		T70	1		T71	3
valid_sources[0x78]	9181	1			T32	7		T36	1		T70	1
valid_sources[0x79]	9975	1			T30	3		T35	3		T60	2
valid_sources[0x7a]	8104	1			T32	1		T46	42		T63	1
valid_sources[0x7b]	9281	1			T32	1		T35	1		T63	1
valid_sources[0x7c]	9482	1			T35	2		T36	7		T37	5
valid_sources[0x7d]	8387	1			T32	1		T35	3		T70	1
valid_sources[0x7e]	9077	1			T30	1		T32	1		T34	3
valid_sources[0x7f]	9101	1			T30	11		T32	2		T35	3
valid_sources[0x80]	8561	1			T32	1		T35	5		T37	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

537448

1

T28

18

T30

102

T31

1

values[0x0]

all_enables

biggest_size

793912

1

T28

38

T30

170

T31

10

values[0x1]

all_enables

biggest_size

793398

1

T28

33

T30

159

T31

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	477799	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2085468

1

T28

124

T30

437

T33

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	573135	1			T28	29		T30	104		T33	2
values[0x0]	820504	1			T28	62		T30	174		T33	1
values[0x1]	1169628	1			T28	91		T30	284		T33	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	180884	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2382383

1

T28

156

T30

512

T33

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10329	1			T28	1		T35	3		T63	2
valid_sources[0x01]	10033	1			T28	1		T30	3		T35	4
valid_sources[0x02]	9414	1			T35	5		T63	2		T67	2
valid_sources[0x03]	9573	1			T35	4		T63	3		T67	1
valid_sources[0x04]	10641	1			T35	4		T46	1		T63	1
valid_sources[0x05]	9593	1			T28	3		T35	1		T46	1
valid_sources[0x06]	10148	1			T30	3		T35	4		T63	4
valid_sources[0x07]	9844	1			T28	1		T35	2		T60	1
valid_sources[0x08]	9801	1			T30	6		T63	4		T67	2
valid_sources[0x09]	10297	1			T35	2		T63	3		T117	1
valid_sources[0x0a]	9570	1			T35	1		T63	1		T67	2
valid_sources[0x0b]	9363	1			T28	1		T30	7		T35	4
valid_sources[0x0c]	10334	1			T28	2		T30	2		T35	4
valid_sources[0x0d]	11262	1			T30	2		T35	4		T46	1
valid_sources[0x0e]	10775	1			T28	1		T35	1		T67	2
valid_sources[0x0f]	10341	1			T35	2		T63	5		T67	4
valid_sources[0x10]	9610	1			T30	1		T35	2		T46	1
valid_sources[0x11]	9619	1			T28	1		T35	4		T63	4
valid_sources[0x12]	10061	1			T28	1		T30	2		T35	3
valid_sources[0x13]	9553	1			T28	2		T30	2		T63	2
valid_sources[0x14]	9399	1			T35	2		T60	1		T63	2
valid_sources[0x15]	10168	1			T30	19		T35	1		T63	1
valid_sources[0x16]	10174	1			T28	2		T30	2		T63	1
valid_sources[0x17]	11126	1			T30	3		T35	1		T63	3
valid_sources[0x18]	9493	1			T28	1		T35	1		T63	2
valid_sources[0x19]	9770	1			T28	1		T30	12		T35	1
valid_sources[0x1a]	10829	1			T28	1		T35	3		T62	1
valid_sources[0x1b]	9810	1			T35	4		T62	1		T63	1
valid_sources[0x1c]	10507	1			T28	2		T33	9		T35	3
valid_sources[0x1d]	9488	1			T35	3		T63	3		T67	2
valid_sources[0x1e]	9739	1			T28	1		T46	1		T63	1
valid_sources[0x1f]	9940	1			T35	2		T63	1		T66	2
valid_sources[0x20]	11436	1			T28	1		T30	1		T35	1
valid_sources[0x21]	10849	1			T28	1		T35	1		T63	5
valid_sources[0x22]	10099	1			T30	2		T35	3		T60	1
valid_sources[0x23]	9940	1			T30	5		T35	3		T60	2
valid_sources[0x24]	9716	1			T28	1		T30	4		T35	1
valid_sources[0x25]	10316	1			T28	1		T30	4		T35	5
valid_sources[0x26]	10301	1			T30	4		T35	4		T63	2
valid_sources[0x27]	9990	1			T28	1		T30	3		T35	1
valid_sources[0x28]	9798	1			T28	1		T30	1		T35	2
valid_sources[0x29]	9464	1			T28	2		T30	4		T35	2
valid_sources[0x2a]	9725	1			T30	6		T35	5		T63	1
valid_sources[0x2b]	10342	1			T28	1		T30	3		T35	3
valid_sources[0x2c]	10150	1			T28	1		T30	2		T35	2
valid_sources[0x2d]	9618	1			T30	2		T35	1		T60	2
valid_sources[0x2e]	9942	1			T30	5		T35	3		T48	1
valid_sources[0x2f]	9895	1			T30	1		T35	4		T63	1
valid_sources[0x30]	9404	1			T28	1		T30	5		T35	4
valid_sources[0x31]	9647	1			T28	1		T35	3		T63	2
valid_sources[0x32]	10575	1			T28	1		T30	2		T35	1
valid_sources[0x33]	10299	1			T30	11		T63	1		T67	2
valid_sources[0x34]	11064	1			T28	1		T30	2		T35	3
valid_sources[0x35]	11695	1			T28	3		T30	4		T35	2
valid_sources[0x36]	9602	1			T28	1		T30	5		T35	2
valid_sources[0x37]	10638	1			T28	1		T30	1		T34	8
valid_sources[0x38]	9917	1			T35	3		T63	4		T67	3
valid_sources[0x39]	9283	1			T30	4		T35	2		T60	1
valid_sources[0x3a]	10251	1			T28	1		T30	3		T35	3
valid_sources[0x3b]	9318	1			T28	2		T30	13		T35	1
valid_sources[0x3c]	9930	1			T35	4		T46	1		T63	1
valid_sources[0x3d]	9342	1			T28	1		T30	13		T35	2
valid_sources[0x3e]	10223	1			T28	1		T30	2		T35	3
valid_sources[0x3f]	10000	1			T28	1		T30	2		T35	5
valid_sources[0x40]	9546	1			T28	2		T35	5		T48	2
valid_sources[0x41]	9587	1			T28	1		T35	2		T63	4
valid_sources[0x42]	9479	1			T28	1		T30	2		T35	3
valid_sources[0x43]	9731	1			T30	1		T35	2		T60	1
valid_sources[0x44]	9710	1			T35	1		T60	1		T63	2
valid_sources[0x45]	9957	1			T28	2		T35	1		T48	3
valid_sources[0x46]	10090	1			T30	2		T35	3		T63	5
valid_sources[0x47]	9911	1			T35	1		T63	2		T68	2
valid_sources[0x48]	9808	1			T30	1		T35	1		T63	2
valid_sources[0x49]	9712	1			T28	1		T30	1		T35	2
valid_sources[0x4a]	11217	1			T28	1		T30	3		T35	2
valid_sources[0x4b]	10816	1			T30	2		T35	5		T63	2
valid_sources[0x4c]	9565	1			T35	1		T63	4		T67	2
valid_sources[0x4d]	10811	1			T30	5		T35	1		T63	3
valid_sources[0x4e]	10851	1			T63	6		T67	1		T68	3
valid_sources[0x4f]	10024	1			T28	1		T30	2		T35	1
valid_sources[0x50]	9658	1			T28	1		T35	3		T48	1
valid_sources[0x51]	10741	1			T35	3		T63	3		T67	1
valid_sources[0x52]	9729	1			T63	2		T67	1		T115	2
valid_sources[0x53]	9427	1			T35	1		T63	3		T67	2
valid_sources[0x54]	9913	1			T30	11		T35	3		T61	2
valid_sources[0x55]	10505	1			T28	1		T30	3		T35	1
valid_sources[0x56]	10536	1			T30	5		T63	1		T67	2
valid_sources[0x57]	9295	1			T30	2		T35	1		T62	2
valid_sources[0x58]	10721	1			T28	2		T30	1		T35	2
valid_sources[0x59]	10279	1			T30	1		T35	1		T63	4
valid_sources[0x5a]	9293	1			T30	4		T35	4		T67	4
valid_sources[0x5b]	9418	1			T28	1		T62	2		T63	2
valid_sources[0x5c]	10693	1			T35	2		T60	1		T62	1
valid_sources[0x5d]	9285	1			T28	1		T30	1		T35	1
valid_sources[0x5e]	9876	1			T28	1		T30	5		T35	1
valid_sources[0x5f]	9468	1			T28	1		T35	4		T63	6
valid_sources[0x60]	10689	1			T35	2		T63	2		T67	5
valid_sources[0x61]	10897	1			T35	2		T60	1		T63	2
valid_sources[0x62]	10186	1			T30	17		T35	3		T61	5
valid_sources[0x63]	10300	1			T28	2		T35	6		T63	1
valid_sources[0x64]	10029	1			T28	1		T30	3		T35	2
valid_sources[0x65]	10256	1			T28	1		T46	4		T63	3
valid_sources[0x66]	10678	1			T28	1		T30	3		T35	6
valid_sources[0x67]	9776	1			T35	3		T63	3		T67	2
valid_sources[0x68]	10124	1			T28	1		T35	1		T62	1
valid_sources[0x69]	10650	1			T28	1		T35	3		T63	1
valid_sources[0x6a]	10024	1			T35	5		T62	3		T63	1
valid_sources[0x6b]	9872	1			T30	3		T35	2		T48	5
valid_sources[0x6c]	10098	1			T28	1		T35	1		T60	1
valid_sources[0x6d]	10063	1			T35	2		T63	3		T67	1
valid_sources[0x6e]	9584	1			T35	4		T62	1		T63	4
valid_sources[0x6f]	9756	1			T28	1		T30	1		T35	3
valid_sources[0x70]	10276	1			T35	3		T62	1		T63	3
valid_sources[0x71]	9646	1			T28	2		T30	1		T60	1
valid_sources[0x72]	9991	1			T35	3		T63	3		T67	4
valid_sources[0x73]	9887	1			T30	2		T35	2		T63	1
valid_sources[0x74]	10208	1			T30	1		T35	2		T63	1
valid_sources[0x75]	10050	1			T28	1		T46	1		T63	3
valid_sources[0x76]	9964	1			T30	2		T63	6		T68	4
valid_sources[0x77]	10684	1			T35	2		T62	3		T63	4
valid_sources[0x78]	10041	1			T28	1		T35	5		T63	2
valid_sources[0x79]	10077	1			T35	1		T63	1		T47	2
valid_sources[0x7a]	9896	1			T30	17		T35	2		T63	3
valid_sources[0x7b]	9926	1			T28	1		T30	5		T35	1
valid_sources[0x7c]	10196	1			T30	6		T35	3		T62	1
valid_sources[0x7d]	9916	1			T30	9		T35	2		T63	4
valid_sources[0x7e]	9679	1			T46	2		T63	4		T64	1
valid_sources[0x7f]	9880	1			T30	6		T35	1		T62	1
valid_sources[0x80]	10148	1			T28	2		T35	4		T63	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

524159

1

T28

29

T30

104

T34

4

values[0x0]

all_enables

biggest_size

779967

1

T28

52

T30

166

T34

4

values[0x1]

all_enables

biggest_size

781342

1

T28

43

T30

167

T33

1