Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_rom_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5816308

1

T28

671

T30

1198

T33

9

full_word

2498867

1

T28

189

T30

518

T33

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8314855	1			T28	860		T30	1716		T34	34
auto[TlIntgErrCmd]	107	1			T33	4		T61	6		T64	4
auto[TlIntgErrData]	110	1			T33	4		T61	3		T64	8
auto[TlIntgErrBoth]	103	1			T33	2		T61	1		T64	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

992172

1

T28

80

T30

177

T33

2

auto[1]

7323003

1

T28

780

T30

1539

T33

8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	418012	1			T28	39		T30	66		T34	3
auto[TlIntgErrNone]	partial	auto[1]	5398002	1			T28	632		T30	1132		T34	13
auto[TlIntgErrNone]	full_word	auto[0]	574004	1			T28	41		T30	111		T34	5
auto[TlIntgErrNone]	full_word	auto[1]	1924837	1			T28	148		T30	407		T34	13
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T33	1		T61	3		T64	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T33	2		T61	3		T64	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T105	1		T108	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T33	1		T82	1		T106	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T33	1		T64	4		T66	4
auto[TlIntgErrData]	partial	auto[1]	50	1			T33	3		T61	3		T64	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T66	1		T69	1		T108	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T64	1		T84	1		T110	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T64	2		T66	3		T69	4
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T33	2		T61	1		T64	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T84	1		T105	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T82	1		T111	1		T107	1