Line Coverage for Module :
prim_generic_rom
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 2 | 66.67 |
CONT_ASSIGN | 22 | 1 | 0 | 0.00 |
ALWAYS | 27 | 2 | 2 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' or '../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
22 |
0 |
1 |
27 |
1 |
1 |
28 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Module :
prim_generic_rom
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
27 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' or '../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 27 if (req_i)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_generic_rom
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
noXOnCsI |
261853698 |
261853698 |
0 |
0 |
noXOnCsI
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
261853698 |
261853698 |
0 |
0 |
T1 |
78751 |
78751 |
0 |
0 |
T2 |
368926 |
368926 |
0 |
0 |
T3 |
70440 |
70440 |
0 |
0 |
T4 |
71606 |
71606 |
0 |
0 |
T5 |
16682 |
16682 |
0 |
0 |
T6 |
336170 |
336170 |
0 |
0 |
T7 |
328140 |
328140 |
0 |
0 |
T8 |
181081 |
181081 |
0 |
0 |
T9 |
181749 |
181749 |
0 |
0 |
T10 |
17829 |
17829 |
0 |
0 |