Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rom_ctrl_csr_assert_0/rom_ctrl_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rom_ctrl_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rom_ctrl_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 98.28 97.33 100.00 79.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rom_ctrl_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 298335274 3809116 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 298335274 3809116 0 0
T28 8416 318 0 0
T29 86331 0 0 0
T30 188883 796 0 0
T31 200569 0 0 0
T32 197586 0 0 0
T33 141649 2 0 0
T34 8516 4 0 0
T35 20737 841 0 0
T36 186336 0 0 0
T37 8973 0 0 0
T48 0 12 0 0
T60 0 42 0 0
T61 0 6 0 0
T62 0 42 0 0
T63 0 551 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%