Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
75.00 75.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
rom_ctrl_tlul_cg 75.00 1 100 1 64 64




Group Instance : rom_ctrl_tlul_cg
Comment: TLUL interface behaviors
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
75.00 1 100 1 64 64




Summary for Group Instance rom_ctrl_tlul_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 2 6 75.00


Variables for Group Instance rom_ctrl_tlul_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regs_req_check 3 1 2 66.67 100 1 1 0
cp_rom_invalid_condition 2 1 1 50.00 100 1 1 0
cp_rom_req_check 3 0 3 100.00 100 1 1 0


Summary for Variable cp_regs_req_check

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 1 2 66.67


User Defined Bins for cp_regs_req_check

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
req_and_done 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
req_after_done 4156838 1 T3 64 T5 160 T6 32
req_before_done 4 1 T11 2 T111 1 T112 1



Summary for Variable cp_rom_invalid_condition

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_rom_invalid_condition

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
check_invalid 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
check_valid 314117348 1 T20 9340 T21 115412 T22 89954



Summary for Variable cp_rom_req_check

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rom_req_check

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
req_after_done 4694889 1 T23 20 T29 10 T46 30
req_and_done 96 1 T46 1 T81 3 T82 2
req_before_done 550 1 T23 20 T29 10 T46 9

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%