Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_rom_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 213955 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2187150 1 T20 112 T21 102 T22 105



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 597063 1 T20 32 T21 9 T22 26
values[0x0] 835377 1 T20 47 T21 49 T22 47
values[0x1] 968665 1 T20 40 T21 44 T22 50



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 95131 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2305974 1 T20 114 T21 102 T22 115



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 9736 1 T22 1 T46 1 T89 2
valid_sources[0x01] 9001 1 T22 1 T45 1 T68 5
valid_sources[0x02] 7959 1 T20 5 T22 1 T23 10
valid_sources[0x03] 9240 1 T47 1 T68 2 T70 1
valid_sources[0x04] 11342 1 T25 17 T68 2 T70 3
valid_sources[0x05] 9695 1 T47 2 T45 2 T68 1
valid_sources[0x06] 8464 1 T22 1 T23 10 T68 7
valid_sources[0x07] 9260 1 T22 1 T29 3 T45 3
valid_sources[0x08] 9292 1 T29 2 T47 1 T68 3
valid_sources[0x09] 9433 1 T20 1 T45 1 T68 1
valid_sources[0x0a] 8552 1 T22 1 T70 16 T93 16
valid_sources[0x0b] 9369 1 T29 1 T68 2 T46 1
valid_sources[0x0c] 10528 1 T22 2 T68 3 T93 7
valid_sources[0x0d] 8392 1 T47 1 T69 5 T68 2
valid_sources[0x0e] 8419 1 T20 3 T47 1 T45 3
valid_sources[0x0f] 9284 1 T47 2 T45 9 T68 1
valid_sources[0x10] 10747 1 T29 1 T68 1 T46 1
valid_sources[0x11] 8586 1 T23 21 T47 1 T68 1
valid_sources[0x12] 9691 1 T47 1 T45 1 T68 2
valid_sources[0x13] 8870 1 T47 4 T68 1 T70 10
valid_sources[0x14] 8265 1 T23 31 T29 2 T47 1
valid_sources[0x15] 9539 1 T23 2 T45 1 T68 4
valid_sources[0x16] 8937 1 T45 2 T68 2 T46 1
valid_sources[0x17] 10423 1 T69 3 T68 2 T46 10
valid_sources[0x18] 10529 1 T47 2 T45 3 T88 1
valid_sources[0x19] 9133 1 T29 2 T68 3 T70 9
valid_sources[0x1a] 9019 1 T21 3 T69 21 T45 1
valid_sources[0x1b] 10132 1 T21 8 T45 1 T68 1
valid_sources[0x1c] 9282 1 T68 4 T70 1 T124 2
valid_sources[0x1d] 8902 1 T22 5 T29 2 T47 2
valid_sources[0x1e] 9382 1 T68 4 T110 1 T124 2
valid_sources[0x1f] 9037 1 T22 1 T68 3 T46 6
valid_sources[0x20] 7905 1 T29 2 T68 2 T70 1
valid_sources[0x21] 8971 1 T20 26 T45 1 T68 1
valid_sources[0x22] 8076 1 T22 1 T28 10 T29 3
valid_sources[0x23] 9677 1 T46 1 T88 1 T73 1
valid_sources[0x24] 9639 1 T22 1 T23 5 T29 1
valid_sources[0x25] 9927 1 T22 1 T68 2 T70 2
valid_sources[0x26] 10037 1 T20 1 T47 1 T45 1
valid_sources[0x27] 9196 1 T69 6 T45 5 T68 2
valid_sources[0x28] 8523 1 T45 2 T68 1 T46 2
valid_sources[0x29] 8623 1 T29 1 T69 1 T45 1
valid_sources[0x2a] 9811 1 T22 2 T68 2 T46 2
valid_sources[0x2b] 9722 1 T69 4 T45 2 T88 3
valid_sources[0x2c] 8132 1 T22 1 T45 1 T68 1
valid_sources[0x2d] 9479 1 T22 2 T46 2 T88 2
valid_sources[0x2e] 11186 1 T47 1 T69 19 T45 1
valid_sources[0x2f] 8340 1 T22 1 T29 4 T45 1
valid_sources[0x30] 9864 1 T45 1 T68 1 T46 1
valid_sources[0x31] 9459 1 T21 6 T29 1 T47 1
valid_sources[0x32] 10140 1 T22 1 T45 2 T68 2
valid_sources[0x33] 9452 1 T68 1 T70 6 T93 3
valid_sources[0x34] 10095 1 T25 16 T47 4 T45 3
valid_sources[0x35] 8372 1 T68 1 T48 1 T93 1
valid_sources[0x36] 9720 1 T22 1 T29 1 T46 2
valid_sources[0x37] 9188 1 T22 1 T46 1 T72 6
valid_sources[0x38] 8847 1 T29 4 T70 1 T88 3
valid_sources[0x39] 9070 1 T22 1 T29 1 T47 2
valid_sources[0x3a] 9412 1 T22 1 T45 4 T70 3
valid_sources[0x3b] 9267 1 T21 24 T22 2 T68 1
valid_sources[0x3c] 8929 1 T21 2 T27 1 T29 1
valid_sources[0x3d] 9914 1 T68 5 T70 1 T46 1
valid_sources[0x3e] 11115 1 T23 3 T47 1 T46 2
valid_sources[0x3f] 8246 1 T23 33 T27 2 T29 1
valid_sources[0x40] 11178 1 T70 1 T46 1 T110 1
valid_sources[0x41] 9553 1 T25 7 T29 6 T70 12
valid_sources[0x42] 8794 1 T22 1 T29 3 T47 2
valid_sources[0x43] 8436 1 T45 2 T46 2 T88 2
valid_sources[0x44] 8704 1 T22 1 T68 1 T73 1
valid_sources[0x45] 9357 1 T22 1 T29 3 T47 1
valid_sources[0x46] 9299 1 T22 1 T29 1 T68 1
valid_sources[0x47] 8774 1 T22 2 T27 3 T68 2
valid_sources[0x48] 7900 1 T47 1 T68 1 T70 1
valid_sources[0x49] 8685 1 T23 21 T68 1 T73 1
valid_sources[0x4a] 9120 1 T29 4 T45 3 T68 1
valid_sources[0x4b] 8557 1 T25 3 T29 1 T45 1
valid_sources[0x4c] 8497 1 T45 1 T68 3 T70 1
valid_sources[0x4d] 9338 1 T70 1 T46 1 T73 2
valid_sources[0x4e] 9442 1 T22 1 T70 2 T46 2
valid_sources[0x4f] 9559 1 T23 10 T29 4 T68 3
valid_sources[0x50] 9737 1 T22 4 T25 5 T45 3
valid_sources[0x51] 11310 1 T29 6 T68 2 T70 1
valid_sources[0x52] 9710 1 T47 2 T69 7 T45 1
valid_sources[0x53] 9616 1 T23 10 T45 2 T46 1
valid_sources[0x54] 9630 1 T25 3 T47 3 T45 2
valid_sources[0x55] 9471 1 T22 3 T45 1 T68 2
valid_sources[0x56] 9600 1 T23 20 T47 2 T68 3
valid_sources[0x57] 9051 1 T20 3 T25 2 T47 2
valid_sources[0x58] 8567 1 T27 1 T68 1 T70 3
valid_sources[0x59] 9368 1 T21 1 T22 1 T29 1
valid_sources[0x5a] 10575 1 T23 12 T45 3 T70 2
valid_sources[0x5b] 9849 1 T22 2 T68 2 T88 1
valid_sources[0x5c] 8241 1 T29 2 T45 4 T68 2
valid_sources[0x5d] 9420 1 T29 6 T45 5 T68 1
valid_sources[0x5e] 8297 1 T20 3 T68 2 T70 3
valid_sources[0x5f] 8983 1 T23 24 T45 2 T46 1
valid_sources[0x60] 9680 1 T23 5 T47 1 T45 2
valid_sources[0x61] 9661 1 T21 2 T22 1 T45 1
valid_sources[0x62] 10836 1 T47 1 T68 1 T46 3
valid_sources[0x63] 8431 1 T47 4 T45 2 T70 1
valid_sources[0x64] 8924 1 T45 3 T68 1 T70 3
valid_sources[0x65] 10409 1 T22 2 T70 6 T46 3
valid_sources[0x66] 9475 1 T20 9 T23 1 T69 13
valid_sources[0x67] 10315 1 T22 2 T29 2 T68 1
valid_sources[0x68] 10711 1 T29 8 T45 1 T68 2
valid_sources[0x69] 9254 1 T22 2 T29 3 T47 1
valid_sources[0x6a] 8328 1 T22 1 T29 1 T68 2
valid_sources[0x6b] 8820 1 T68 1 T46 1 T88 4
valid_sources[0x6c] 9249 1 T25 1 T29 2 T68 2
valid_sources[0x6d] 10400 1 T47 1 T46 2 T89 1
valid_sources[0x6e] 10363 1 T22 1 T27 4 T29 3
valid_sources[0x6f] 9159 1 T45 3 T68 4 T48 4
valid_sources[0x70] 9780 1 T20 1 T68 2 T70 1
valid_sources[0x71] 9157 1 T22 1 T45 1 T46 3
valid_sources[0x72] 9781 1 T47 1 T70 3 T46 5
valid_sources[0x73] 10005 1 T22 4 T69 5 T45 2
valid_sources[0x74] 8498 1 T29 4 T70 4 T46 1
valid_sources[0x75] 10336 1 T45 1 T46 3 T93 3
valid_sources[0x76] 11199 1 T22 1 T68 2 T70 2
valid_sources[0x77] 9945 1 T68 1 T46 1 T88 3
valid_sources[0x78] 8525 1 T22 1 T68 2 T46 2
valid_sources[0x79] 10074 1 T23 12 T47 1 T45 3
valid_sources[0x7a] 8736 1 T23 10 T29 2 T47 1
valid_sources[0x7b] 11343 1 T24 10 T68 3 T46 1
valid_sources[0x7c] 9975 1 T22 1 T23 18 T45 1
valid_sources[0x7d] 10178 1 T29 1 T47 3 T68 1
valid_sources[0x7e] 8443 1 T47 1 T69 8 T68 1
valid_sources[0x7f] 8733 1 T25 16 T47 1 T68 1
valid_sources[0x80] 9903 1 T22 3 T68 4 T46 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 551727 1 T20 28 T21 9 T22 23
values[0x0] all_enables biggest_size 818291 1 T20 46 T21 49 T22 46
values[0x1] all_enables biggest_size 817132 1 T20 38 T21 44 T22 36


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 488777 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2182081 1 T20 30 T22 144 T23 40



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 597237 1 T20 10 T22 31 T23 40
values[0x0] 859686 1 T20 9 T22 52 T68 42
values[0x1] 1213935 1 T20 19 T22 84 T45 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 185919 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2484939 1 T20 36 T22 159 T23 40



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 10821 1 T75 9 T77 1 T78 2
valid_sources[0x01] 10742 1 T22 2 T75 7 T125 3
valid_sources[0x02] 10994 1 T22 1 T71 4 T75 4
valid_sources[0x03] 10863 1 T22 1 T23 1 T72 3
valid_sources[0x04] 11412 1 T75 6 T87 3 T125 2
valid_sources[0x05] 9612 1 T75 2 T87 5 T125 1
valid_sources[0x06] 9987 1 T22 3 T71 1 T75 1
valid_sources[0x07] 10059 1 T75 5 T82 1 T125 2
valid_sources[0x08] 9651 1 T22 1 T68 31 T75 5
valid_sources[0x09] 11336 1 T22 2 T75 4 T76 1
valid_sources[0x0a] 9248 1 T22 2 T75 4 T77 1
valid_sources[0x0b] 10450 1 T75 2 T76 1 T78 1
valid_sources[0x0c] 9585 1 T22 1 T23 1 T75 1
valid_sources[0x0d] 9473 1 T75 4 T78 1 T84 4
valid_sources[0x0e] 10622 1 T22 1 T74 8 T75 1
valid_sources[0x0f] 10274 1 T75 1 T76 1 T123 1
valid_sources[0x10] 10971 1 T75 3 T87 2 T126 24
valid_sources[0x11] 9717 1 T22 2 T73 1 T75 5
valid_sources[0x12] 11773 1 T22 2 T75 5 T125 1
valid_sources[0x13] 9541 1 T75 2 T87 1 T125 4
valid_sources[0x14] 10658 1 T75 6 T78 3 T83 1
valid_sources[0x15] 10771 1 T75 4 T76 4 T87 1
valid_sources[0x16] 10012 1 T75 2 T76 1 T127 1
valid_sources[0x17] 10551 1 T75 4 T76 2 T87 2
valid_sources[0x18] 10927 1 T73 1 T75 5 T76 2
valid_sources[0x19] 12034 1 T75 1 T84 1 T128 1
valid_sources[0x1a] 9257 1 T76 1 T77 2 T78 2
valid_sources[0x1b] 11797 1 T22 5 T75 9 T76 1
valid_sources[0x1c] 11990 1 T73 2 T75 6 T78 3
valid_sources[0x1d] 9103 1 T22 1 T73 1 T75 2
valid_sources[0x1e] 10096 1 T75 3 T78 3 T87 1
valid_sources[0x1f] 10687 1 T75 2 T125 3 T127 1
valid_sources[0x20] 10809 1 T76 1 T78 2 T87 3
valid_sources[0x21] 10822 1 T70 84 T75 1 T77 1
valid_sources[0x22] 10468 1 T75 2 T82 1 T125 2
valid_sources[0x23] 11152 1 T75 1 T76 1 T78 1
valid_sources[0x24] 8636 1 T75 1 T76 3 T125 2
valid_sources[0x25] 10590 1 T75 5 T76 1 T77 7
valid_sources[0x26] 9638 1 T22 1 T75 6 T78 2
valid_sources[0x27] 10985 1 T75 5 T77 2 T78 1
valid_sources[0x28] 9164 1 T75 2 T76 1 T87 1
valid_sources[0x29] 11044 1 T22 3 T75 2 T82 1
valid_sources[0x2a] 9073 1 T22 2 T45 5 T75 2
valid_sources[0x2b] 10426 1 T71 1 T125 1 T113 1
valid_sources[0x2c] 10328 1 T23 1 T75 5 T78 11
valid_sources[0x2d] 9454 1 T20 1 T73 1 T87 1
valid_sources[0x2e] 11595 1 T22 1 T72 1 T75 3
valid_sources[0x2f] 9871 1 T22 1 T75 11 T78 2
valid_sources[0x30] 9738 1 T22 1 T75 3 T78 1
valid_sources[0x31] 9018 1 T22 3 T75 4 T77 3
valid_sources[0x32] 10569 1 T75 14 T87 5 T125 3
valid_sources[0x33] 10996 1 T22 1 T75 6 T87 1
valid_sources[0x34] 8979 1 T22 1 T70 173 T73 1
valid_sources[0x35] 12009 1 T75 2 T78 3 T87 3
valid_sources[0x36] 10440 1 T125 1 T127 3 T113 1
valid_sources[0x37] 10882 1 T23 1 T73 1 T75 7
valid_sources[0x38] 9067 1 T22 2 T23 1 T73 1
valid_sources[0x39] 11589 1 T22 1 T75 1 T78 8
valid_sources[0x3a] 9125 1 T22 4 T75 4 T78 10
valid_sources[0x3b] 10978 1 T20 2 T22 2 T75 3
valid_sources[0x3c] 9202 1 T20 1 T22 1 T71 2
valid_sources[0x3d] 10182 1 T22 2 T75 1 T78 4
valid_sources[0x3e] 10215 1 T23 1 T75 9 T77 3
valid_sources[0x3f] 11370 1 T75 6 T78 1 T87 3
valid_sources[0x40] 10521 1 T22 1 T23 3 T87 1
valid_sources[0x41] 10173 1 T22 1 T75 1 T77 6
valid_sources[0x42] 12198 1 T75 4 T76 1 T77 2
valid_sources[0x43] 11062 1 T22 2 T75 9 T78 1
valid_sources[0x44] 10109 1 T75 8 T78 1 T81 1
valid_sources[0x45] 9813 1 T71 3 T75 6 T78 5
valid_sources[0x46] 9638 1 T75 1 T78 5 T87 1
valid_sources[0x47] 11159 1 T22 2 T71 1 T75 2
valid_sources[0x48] 10720 1 T75 3 T83 1 T113 1
valid_sources[0x49] 10044 1 T22 1 T75 1 T78 1
valid_sources[0x4a] 10570 1 T22 1 T23 1 T73 1
valid_sources[0x4b] 10352 1 T22 1 T75 7 T76 2
valid_sources[0x4c] 10137 1 T75 11 T83 1 T125 3
valid_sources[0x4d] 10272 1 T22 1 T23 3 T75 8
valid_sources[0x4e] 10610 1 T22 1 T75 5 T125 4
valid_sources[0x4f] 9613 1 T46 15 T75 1 T77 3
valid_sources[0x50] 8917 1 T73 1 T75 3 T87 1
valid_sources[0x51] 10639 1 T22 1 T23 1 T75 3
valid_sources[0x52] 12400 1 T22 2 T75 9 T78 3
valid_sources[0x53] 10333 1 T22 2 T75 3 T77 7
valid_sources[0x54] 9341 1 T20 2 T75 1 T77 4
valid_sources[0x55] 10558 1 T75 11 T77 5 T78 3
valid_sources[0x56] 10293 1 T22 2 T75 8 T78 7
valid_sources[0x57] 12444 1 T73 1 T75 1 T78 1
valid_sources[0x58] 10741 1 T22 1 T75 3 T87 1
valid_sources[0x59] 10953 1 T20 2 T72 2 T75 6
valid_sources[0x5a] 10238 1 T23 1 T75 3 T76 3
valid_sources[0x5b] 10023 1 T22 1 T75 5 T78 2
valid_sources[0x5c] 11240 1 T23 1 T75 1 T77 2
valid_sources[0x5d] 9922 1 T72 1 T75 4 T77 3
valid_sources[0x5e] 10252 1 T22 1 T75 2 T87 1
valid_sources[0x5f] 9478 1 T23 1 T75 5 T77 2
valid_sources[0x60] 10782 1 T68 106 T75 1 T76 1
valid_sources[0x61] 10491 1 T75 5 T77 4 T83 1
valid_sources[0x62] 10877 1 T75 1 T76 1 T78 2
valid_sources[0x63] 11023 1 T22 2 T46 9 T75 4
valid_sources[0x64] 11426 1 T73 1 T75 5 T87 3
valid_sources[0x65] 11376 1 T75 6 T78 1 T81 1
valid_sources[0x66] 9695 1 T22 1 T75 2 T78 3
valid_sources[0x67] 10749 1 T22 1 T48 1 T75 5
valid_sources[0x68] 9684 1 T22 1 T75 3 T77 1
valid_sources[0x69] 13083 1 T23 1 T75 7 T76 2
valid_sources[0x6a] 11553 1 T20 1 T75 1 T87 1
valid_sources[0x6b] 11013 1 T75 6 T78 1 T87 1
valid_sources[0x6c] 9423 1 T22 1 T23 1 T75 9
valid_sources[0x6d] 9451 1 T73 1 T75 3 T77 1
valid_sources[0x6e] 10628 1 T75 6 T78 2 T127 1
valid_sources[0x6f] 10474 1 T75 1 T86 3 T78 1
valid_sources[0x70] 9913 1 T22 1 T68 77 T78 1
valid_sources[0x71] 11113 1 T48 1 T75 3 T76 1
valid_sources[0x72] 9602 1 T22 1 T75 4 T76 1
valid_sources[0x73] 9021 1 T75 2 T87 1 T125 3
valid_sources[0x74] 9226 1 T75 11 T76 2 T77 3
valid_sources[0x75] 10316 1 T75 5 T87 1 T125 2
valid_sources[0x76] 12243 1 T75 3 T125 4 T127 4
valid_sources[0x77] 10916 1 T22 1 T23 1 T75 3
valid_sources[0x78] 9469 1 T75 9 T76 2 T86 2
valid_sources[0x79] 10239 1 T22 3 T46 3 T75 1
valid_sources[0x7a] 10690 1 T75 4 T125 3 T11 1027
valid_sources[0x7b] 9964 1 T75 1 T125 2 T127 1
valid_sources[0x7c] 9366 1 T72 1 T75 7 T77 1
valid_sources[0x7d] 9606 1 T75 12 T78 1 T87 1
valid_sources[0x7e] 10220 1 T22 2 T48 1 T75 3
valid_sources[0x7f] 9976 1 T75 6 T76 1 T125 5
valid_sources[0x80] 9854 1 T22 5 T23 2 T75 10



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 548415 1 T20 10 T22 31 T23 40
values[0x0] all_enables biggest_size 817822 1 T20 8 T22 50 T68 37
values[0x1] all_enables biggest_size 815844 1 T20 12 T22 63 T68 42

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%